Datasheet STM8S003FS Specification

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Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory,
LQFP32 7x7 mm
TSSOP20
6.5x6.4 mm
UFQFPN20
3x3 mm
128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C
Features
Core
Extended instruction set
Memories
Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
RAM: 1 Kbyte
Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low-power 128 kHz RC
Clock security system with clock monitor
Power management
– Low-power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually – Permanently active, low-consumption
power-on and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
STM8S003F3 STM8S003K3
Datasheet - production data
Timers
Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wakeup timer
Window and independent watchdog timers
Communications interfaces
UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
2
I
C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit ADC, ± 1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21 high-sink outputs
Highly robust I/O design, immune against current injection
Development support
Embedded single-wire interface module (SWIM) for fast on-chip programming and non­intrusive debugging
August 2018 DS7147 Rev 10 1/103
This is information on a product in full production.
www.st.com
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Contents STM8S003F3 STM8S003K3
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11 TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.3 I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 STM8S003K3 LQFP32 pinout and pin description . . . . . . . . . . . . . . . . . . 22
5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description . . . . . . 25
5.3 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Contents
6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 39
7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 61
9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 63
9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.3.9 I
9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2
C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.2 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3 UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 97
DS7147 Rev 10 3/103
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Contents STM8S003F3 STM8S003K3
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 List of tables
List of tables
Table 1. STM8S003F3/K3 value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15
Table 3. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Legend/abbreviations for STM8S003F3/K3 pin description tables. . . . . . . . . . . . . . . . . . . 21
Table 5. STM8S003K3 descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. STM8S003F3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 13. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices. . . . . . . . . . . . . . . . . . 44
Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices . . . . . . . . . . . . . . . . . . 45
Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. Total current consumption with code execution in run mode at V Table 22. Total current consumption with code execution in run mode at V Table 23. Total current consumption in wait mode at V Table 24. Total current consumption in wait mode at V Table 25. Total current consumption in active halt mode at V Table 26. Total current consumption in active halt mode at V Table 27. Total current consumption in halt mode at V Table 28. Total current consumption in halt mode at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DD
DD
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . 55
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . 55
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 31. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 33. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 36. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37. Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 38. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 39. Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 41. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 42. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 44. I
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 46. ADC accuracy with R Table 47. ADC accuracy with R
< 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AIN
< 10 kΩ R
AIN
AIN
, V
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DD
Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
= 5 V . . . . . . . . . . . . 52
DD
= 3.3 V . . . . . . . . . . . 53
DD
DS7147 Rev 10 5/103
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List of tables STM8S003F3 STM8S003K3
Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 89
Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 55. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 56. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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STM8S003F3 STM8S003K3 List of figures
List of figures
Figure 1. STM8S003F3/K3 value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. STM8S003K3 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. STM8S003F3 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. STM8S003F3 UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 9. f
CPUmax
Figure 10. External capacitor C Figure 11. Typ. I Figure 12. Typ. I Figure 13. Typ. I Figure 14. Typ. I Figure 15. Typ. I Figure 16. Typ. I
Figure 17. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19. Typical HSI frequency variation vs V Figure 20. Typical LSI frequency variation vs V Figure 21. Typical V Figure 22. Typical pull-up resistance vs V Figure 23. Typical pull-up current vs V Figure 24. Typ. V Figure 25. Typ. V Figure 26. Typ. V Figure 27. Typ. V Figure 28. Typ. V Figure 29. Typ. V Figure 30. Typ. V Figure 31. Typ. V Figure 32. Typ. V Figure 33. Typ. V Figure 34. Typical NRST V Figure 35. Typical NRST pull-up resistance vs V Figure 36. Typical NRST pull-up current vs V
Figure 37. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. SPI timing diagram - slave mode and CPHA = 1 Figure 40. SPI timing diagram - master mode Figure 41. Typical application with I
Figure 42. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 88
Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 89
Figure 46. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DD(RUN)
DD(RUN)
DD(RUN)
DD(WFI)
DD(WFI)
DD(WFI)
OL
OL
OL
OL
OL
OL
DD
DD
DD
DD
vs VDD, HSE user external clock, f vs f
vs VDD, HSI RC osc, f vs. VDD HSE user external clock, f vs. f vs VDD, HSI RC osc, f
and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
IL
@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
@ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
@ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
@ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
- V
OH
- V
OH
- V
OH
- V
OH
EXT
, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 58
CPU
, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 60
CPU
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DD
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CPU
at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 64
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 64
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
= 16 MHz . . . . . . . . . . . . . . . . . . . . 58
CPU
= 16MHz . . . . . . . . . . . . . . . . . . . . . 59
CPU
@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
@ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IL
2
C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 76
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DD
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DS7147 Rev 10 7/103
8
Page 8
List of figures STM8S003F3 STM8S003K3
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 49. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 52. UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 53. STM8S003F3/K3 value line ordering information scheme
(1)
. . . . . . . . . . . . . . . . . . . . . . . 98
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STM8S003F3 STM8S003K3 Introduction

1 Introduction

This datasheet contains the description of the STM8S003F3/K3 value line features, pinout,
electrical characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).
For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM).
For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).
DS7147 Rev 10 9/103
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Description STM8S003F3 STM8S003K3

2 Description

The STM8S003F3/K3 value line 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. They are referred to as low-density devices in the STM8S microcontroller family reference manual (RM0016).
The STM8S003F3/K3 value line devices provide the following benefits: performance, robustness and reduced system cost.
Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 clock source, and a clock security system.
The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
MHz clock frequency, robust I/Os, independent watchdogs with separate

Table 1. STM8S003F3/K3 value line features

Features STM8S003K3 STM8S003F3
Pin count 32 20
Max. number of GPIOs (I/O) 28 16
External interrupt pins 27 16
Timer CAPCOM channels 7 7
Timer complementary outputs 3 2
A/D converter channels 4 5
High-sink I/Os 21 12
Low-density Flash program memory (byte)
RAM (byte) 1 K 1 K
True data EEPROM (byte) 128
Peripheral set
1. Without read-while-write capability.
Multi purpose timer (TIM1), SPI, I2C, UART, Window WDG,
independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)
8 K 8 K
(1)
128
(1)
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STM8S003F3 STM8S003K3 Block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
UART1
I2C
SPI
AWU t imer
Reset block
Reset
POR
BOR
Clock controller
Detector
Clock to peripherals and core
400 Kbit/s
8Mbit/s
up to 5
Address and data bus
Window WDG
8 Kbyte
128 byte
1 Kbyte RAM
ADC1
Reset
Single wire debug interface
program Flash
data EEPROM
16-bit general purpose
16-bit advanced control
timer (TIM1)
timer (TIM2)
8-bit basic timer
(TIM4)
Beeper
1/2/4 kHz beep
Independent WDG
4 CAPCOM
channels
Up to
3 CAPCOM
channels
Up to
+ 3 complementary
outputs
LIN master
channels
SPI emul.

3 Block diagram

Figure 1. STM8S003F3/K3 value line block diagram

DS7147 Rev 10 11/103
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Product overview STM8S003F3 STM8S003K3

4 Product overview

The following section intends to give an overview of the basic features of the STM8S003F3/K3 value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual (RM0016).

4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.
It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
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STM8S003F3 STM8S003K3 Product overview

4.2 Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time in­circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real­time by means of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations

4.3 Interrupt controller

Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 27 external interrupts on six vectors including TLI
Trap and reset interrupts

4.4 Flash program memory and data EEPROM

8 Kbyte of Flash program single voltage Flash memory
128 byte true data EEPROM
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to
DS7147 Rev 10 13/103
Figure 2.
29
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Product overview STM8S003F3 STM8S003K3
The size of the UBC is programmable through the UBC option byte (Ta ble 13), in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: 8 Kbyte minus UBC
User-specific boot code (UBC): Configurable up to 8 Kbyte
The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2. Flash memory organization

Option bytes
Data EEPROM (128 bytes)
Programmable
UBC area
Remains write protected during IAP
Low density Flash program memory (8 Kbytes)
Program memory area
Write access possible for IAP
area from 64 bytes (1 page) up to 8 Kbytes (in 1 page steps)
Read-out protection (ROP)
The read-out protection blocks reading and writing from/to the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
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MS36408V1
Page 15
STM8S003F3 STM8S003K3 Product overview

4.5 Clock controller

The clock controller distributes the system clock (f
MASTER)
coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit
PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC
PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved
PCKEN14 TIM4 PCKEN10 I
Peripheral
clock
Bit
Peripheral
clock
2
C PCKEN24 Reserved PCKEN20 Reserved
DS7147 Rev 10 15/103
Bit
Peripheral
clock
Bit
Peripheral
clock
29
Page 16
Product overview STM8S003F3 STM8S003K3

4.6 Power management

For efficient power management, the application can be put in one of four different low­power modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application perfectly.
The application software must refresh the counter before time-out and during a limited time window.
A reset is generated in two situations:
1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64
ms.
2. Refresh out of window: the down-counter is refreshed before its value is lower than the
one stored in the window register.
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STM8S003F3 STM8S003K3 Product overview
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.

4.8 Auto wakeup counter

Used for auto wakeup from active halt mode
Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

4.9 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.

4.10 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11 TIM2 - 16-bit general purpose timer

16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
3 individually configurable capture/compare channels
PWM mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
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Product overview STM8S003F3 STM8S003K3

4.12 TIM4 - 8-bit basic timer

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update

Table 3. TIM timer features

Counter
Timer
TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes
TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No
TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No
size
(bits)
Prescaler
Counting
mode
CAPCOM
channels
Complem.
outputs

4.13 Analog-to-digital converter (ADC1)

STM8S003F3/K3 value line products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed input channels and the following main features:
Input voltage range: 0 to V
Conversion time: 14 clock cycles
Single and continuous, buffered continuous conversion modes
Buffer size (10 x 10 bits)
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
DDA
Ext.
trigger
Timer
synchr-
onization/
chaining
No
Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog.
Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

4.14 Communication interfaces

The following communication interfaces are implemented:
UART1: full feature UART, synchronous mode, SPI master mode, SmartCard mode,
IrDA mode, LIN2.1 master capability
SPI: full and half-duplex, 8 Mbit/s
I²C: up to 400 Kbit/s
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STM8S003F3 STM8S003K3 Product overview

4.14.1 UART1

Main features
1 Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
Address bit (MSB)
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
/16) and capable of
CPU
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
LIN master mode
Emission: generates 13-bit synch. break frame
Reception: detects 11-bit break frame

4.14.2 SPI

Maximum speed: 8 Mbit/s (f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
MASTER
/16)
CPU
/2) both for master and slave
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Product overview STM8S003F3 STM8S003K3

4.14.3 I2C

I2C master features
Clock generation
Start and stop generation
2
I
C slave features
Programmable I
Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds
Standard speed (up to 100 kHz)
Fast speed (up to 400 kHz)
2
C address detection
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STM8S003F3 STM8S003K3 Pinouts and pin descriptions

5 Pinouts and pin descriptions

Table 4. Legend/abbreviations for STM8S003F3/K3 pin description tables

Type I = input, O = output, S = power supply
Level
Output speed
Port and control configuration
Reset state
Input CM = CMOS
Output HS = high sink
O1 = slow (up to 2 MHz) O2 = fast (up to 10 MHz) O3 = fast/slow programmability with slow as default state after reset O4 = fast/slow programmability with fast as default state after reset
Input float = floating, wpu = weak pull-up
Output T = true open drain, OD = open drain, PP = push pull
(pin state after internal reset release)
Bold x Unless otherwise specified, the pin state is the same during the reset phase
and after the internal reset release.
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Pinouts and pin descriptions STM8S003F3 STM8S003K3
MS37740V1
TIM1_CH2N/ AIN1/(HS) PB1
TIM1_CH1N/AIN0/(HS) PB0
PB7
PB6
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
9 101112131415
16
1 2 3 4 5 6 7 8
VCAP
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
PC3 (HS)/TIM1_CH3
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS) [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/ TIM1_BKIN [CLK_CCO]
PD6 (HS)/UART1_RX
PD5 (HS)/UART1_TX
PD4 (HS)/BEEP/TIM2_CH1
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
PC2 (HS)/TIM1_CH2
I2C_SDA/(T) PB5
I2C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH3N/AIN2/(HS) PB2
VDD
PD7 (HS)/TLI [TIM1_CH4]

5.1 STM8S003K3 LQFP32 pinout and pin description

Figure 3. STM8S003K3 LQFP32 pinout

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Table 5. STM8S003K3 descriptions

Input Output
Pin name
LQFP32
1 NRST I/O - X - - - - - Reset -
2 PA1/OSCIN
(2)
Typ e
I/O X XX -O1XXPort A1
wpu
floating
(1)
Speed
High sink
Ext. interrupt
OD
PP
Main function
(after reset)
Default
alternate
function
Resonator/ crystal in
Alternate
function
after remap
[option bit]
-
Page 23
STM8S003F3 STM8S003K3 Pinouts and pin descriptions
Table 5. STM8S003K3 descriptions (continued)
Input Output
Alternate
function
after remap
[option bit]
Ext. interrupt
(1)
Speed
High sink
OD
PP
Main function
LQFP32
Pin name
Typ e
wpu
floating
3 PA2/OSCOUT I/O X XX -O1XXPort A2
4V
SS
S - - - - - - - Digital ground -
Default
alternate
function
(after reset)
Resonator/ crystal out
5 VCAP S - - - - - - - 1.8 V regulator capacitor -
6V
DD
PA3/TIM2_CH3
7
[SPI_NSS]
8PF4 I/OX
9 PB7 I/O X
10 PB6 I/O X
2
11 PB5/I
12 PB4/I
13
C_SDA I/O X -X-O1T
2
C_SCL I/O X -X-O1T
PB3/AIN3 [TIM1_ETR]
S - - - - - - - Digital power supply -
SPI master/ slave select
[AFR1]
I/O X
XXHSO3XXPort A3
Timer 2
channel 3
X--O1XXPort F4 --
X--O1XXPort B7 --
X--O1XXPort B6 --
(3)
- Port B5 I2C data -
(3)
- Port B4 I2C clock -
Analog
I/O X
XXHSO3XXPort B3
input 3/Timer 1 external trigger
Analog
PB2/AIN2
14
[TIM1_CH3N]
I/O X
XXHSO3XXPort B2
input 2/Timer 1
- inverted channel 3
Analog
PB1/AIN1
15
[TIM1_CH2N]
I/O X
XXHSO3XXPort B1
input 1/Timer 1
- inverted channel 2
-
-
-
-
PB0/AIN0
16
[TIM1_CH1N]
I/O X
17 PE5/SPI_NSS I/O X
PC1/TIM1_CH1/
18
UART1_CK
I/O X
19 PC2/TIM1_CH2 I/O X
20 PC3/TIM1_CH3 I/O X
Analog
XXHSO3XXPort B0
input 0/Timer 1
- inverted
-
channel 1
SPI
XXHSO3XXPort E5
master/slave
-
select
Timer 1 -
XXHSO3XXPort C1
channel 1
-
UART1 clock
XXHSO3XXPort C2
XXHSO3XXPort C3
Timer 1­channel 2
Timer 1 ­channel 3
-
-
DS7147 Rev 10 23/103
29
Page 24
Pinouts and pin descriptions STM8S003F3 STM8S003K3
Table 5. STM8S003K3 descriptions (continued)
Input Output
Ext. interrupt
(1)
Speed
High sink
OD
PP
Main function
Pin name
LQFP32
PC4/TIM1_CH4/C
21
LK_CCO
Typ e
I/O X XXHSO3XXPort C4
22 PC5/SPI_SCK I/O X
wpu
floating
XXHSO3XXPort C5 SPI clock -
23 PC6/SPI_MOSI I/O X XXHSO3XXPort C6
24 PC7/SPI_MISO I/O X
PD0/[TIM1_BKIN
25
[CLK_CCO]
26 PD1/SWIM
PD2
27
[TIM2_CH3]
PD3/TIM2_CH2
28
[ADC_ETR]
PD4/BEEP/
29
TIM2_CH1
(4)
I/O X
I/O X X XHSO4X XPort D1
I/O X
I/O X
I/O X
30 PD5/ UART1_TX I/O X
31 PD6/ UART1_RX I/O X
XXHSO3XXPort C7
XXHSO3XXPort D0
XXHSO3XXPort D2 -
XXHSO3XXPort D3
XXHSO3XXPort D4
XXHSO3XXPort D5
XXHSO3XXPort D6
Default
alternate
function
(after reset)
Timer 1 ­channel 4/configurable clock output
SPI master out/slave in
SPI master in/ slave out
Timer 1 - break input
SWIM data interface
Timer 2 ­channel 2/ADC external trigger
Timer 2 ­channel 1/BEEP output
UART1 data transmit
UART1 data receive
Alternate
function
after remap
[option bit]
-
-
-
Configurable clock output [AFR5]
-
Timer 2 ­channel 3 [AFR1]
-
-
-
-
PD7/TLI
32
[TIM1_CH4]
1. I/O pins used simultaneously for high-current source/sink must be uniformly spaced around the package. In
addition, the total driven current must respect the absolute maximum ratings given in Section 9: Electrical
characteristics.
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and
cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection
diode to V
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
are not implemented).
DD
I/O X
XXHSO3XXPort D7
24/103 DS7147 Rev 10
Top level interrupt
Timer 1 -
channel 4
[AFR6]
Page 25
STM8S003F3 STM8S003K3 Pinouts and pin descriptions

5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description

Figure 4. STM8S003F3 TSSOP20 pinout

UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
UART1_RX/AIN6/(HS) PD6
NRST
OSCIN/PA1
OSCOUT/PA2
V
SS
VCAP
V
DD
[SPI_NSS] TIM2_CH3/(HS) PA3
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
10
1
2
3
4
5
6
7
8
9
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
20
19
PD2(HS)/AIN3/[TIM2_CH3]
18
PD1(HS)/SWIM
17
PC7(HS)/SPI_MISO [TIM1_CH2]
16
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
15
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
14
PC3(HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
13
12
PB4(T)/I2C_SCL [ADC_ETR]
11
PB5(T)/I2C_SDA [TIM1_BKIN]
MS37741V1
DS7147 Rev 10 25/103
29
Page 26
Pinouts and pin descriptions STM8S003F3 STM8S003K3
MS36409V1
2
1
3
4
5
67 8
9
11
12
13
14
15
16171819
VCAP
V
SS
OSCOUT/PA2
OSCIN/PA1
[SPI_NSS] TIM2_CH3/(HS) PA3
NRST
PD4 (HS)/BEEP / TIM2_CH1/UART1_CK
PD5(HS)/AIN5/UART1_TX
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2(HS)/AIN3/{TIM2_CH3]
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC7(HS)/SPI_MISO[TIM1_CH2]
PD1(HS)/SWIM
[TIM1_BKIN] I2C_SDA/(T)PB5
10
[TIM1_CH1N] [TLI] TIM1_CH3 /(HS)PC3
PD6(HS)/AIN6/UART1_RX
20
V
DD
[ADC_ETR] I2C_SCL/(T)PB4

Figure 5. STM8S003F3 UFQFPN20 pinout

26/103 DS7147 Rev 10
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Page 27
STM8S003F3 STM8S003K3 Pinouts and pin descriptions
Pin no.

Table 6. STM8S003F3 pin description

Input Output
Pin name Type
TSSOP20
UFQFPN20
floating
PD4/ BEEP/
118
TIM2_ CH1/
I/O X X X HS O3 X X Port D4
UART1 _CK
219
320
PD5/ AIN5/ UART1 _TX
PD6/ AIN6/ UART1 _RX
I/O X
I/O X
4 1 NRST I/O - X
5 2 PA1/ OSCIN
(2)
I/O X X X - O1 X X Port A1
Main
function
High
(1)
wpu
sink
OD PP
Speed
(after
reset)
Default
alternate
function
Ext. interr.
Timer 2 ­channel 1/BEEP output/ UART1 clock
Analog input
XX HS O3 XX Port D5
5/ UART1 data transmit
Analog input
XX HS O3 XX Port D6
6/ UART1 data receive
- - ---Reset -
Resonator/ crystal in
Alternate
function
after remap
[option bit]
-
-
-
-
6 3 PA2/ OSCOUT I/O X
X X - O1 X X Port A2
Resonator/ crystal out
-
7 4 VSS S - - - - - - - Digital ground -
8 5VCAP S - -- - ---
1.8 V regulator capacitor
-
96VDD S - -- - ---Digital power supply -
SPI master/ slave select [AFR1]
Timer 1 ­break input [AFR4]
10
11
PA3/ TIM2_ CH3
7
[SPI_ NSS]
PB5/ I2C_ SDA
8
[TIM1_ BKIN]
I/O X
I/O X
X X HS O3 X X Port A3
- X - O1 T
(3)
- Port B5 I2C data
Timer 2 channel 3
ADC
9 PB4/ I2C_ SCL I/O X
12
- X - O1 T
(3)
- Port B4 I2C clock
external
trigger
[AFR4]
Top level interrupt [AFR3] Timer 1 ­inverted
13
PC3/ TIM1_CH3
10
[TLI] [TIM1_ CH1N]
I/O X
X X HS O3 X X Port C3
Timer 1 ­channel 3
channel 1 [AFR7]
DS7147 Rev 10 27/103
29
Page 28
Pinouts and pin descriptions STM8S003F3 STM8S003K3
Table 6. STM8S003F3 pin description (continued)
Pin no.
TSSOP20
UFQFPN20
PC4/ CLK_CCO/ TIM1_
11
14
CH4/AIN2/ [TIM1_ CH2N]
PC5/ SPI_SCK
12
15
16
17
18
19
20
[TIM2_ CH1]
PC6/ SPI_MOSI
13
[TIM1_ CH1]
PC7/ SPI_MISO
14
[TIM1_ CH2]
15 PD1/ SWIM
PD2/AIN3/
16
[TIM2_ CH3]
PD3/ AIN4/
17
TIM2_ CH2/ ADC_ ETR
Pin name Type
I/O X
I/O X
I/O X
I/O X
(4)
I/O X X X HS O4 X X Port D1
I/O X
I/O X
Input Output
Main
function
(after
reset)
wpu
floating
Ext. interr.
High
sink
(1)
OD PP
Speed
X X HS O3 X X Port C4
X X HS O3 X X Port C5 SPI clock
X X HS O3 X X Port C6
X X HS O3 X X Port C7
X X HS O3 X X Port D2
X X HS O3 X X Port D3
Default
alternate
function
Configurable clock output/Timer 1 - channel 4/Analog input 2
SPI master out/slave in
SPI master in/ slave out
SWIM data
interface
Analog input 3
Analog input 4/ Timer 2 ­channel 2/ADC external trigger
Alternate
function
after remap
[option bit]
Timer 1 ­inverted channel 2 [AFR7]
Timer 2 ­channel 1 [AFR0]
Timer 1 ­channel 1 [AFR0]
Timer 1 ­channel 2 [AFR0]
-
Timer 2 ­channel 3 [AFR1]
-
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings.
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode if halt/active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
28/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Pinouts and pin descriptions

5.3 Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).
Section 8: Option bytes. When the remapping option is active,
DS7147 Rev 10 29/103
29
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Memory and register map STM8S003F3 STM8S003K3

6 Memory and register map

6.1 Memory map

Figure 6. Memory map

0x00 0000
0x00 03FF
0x00 0800
0x00 4000
0x00 407F
0x00 47FF
0x00 4800
0x00 480A 0x00 480B
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
RAM
(1 Kbyte)
513 byte stack
Reserved
Data EEPROM
Reserved
Option bytes
Reserved
GPIO and periph. reg.
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F 0x00 8080
0x00 9FFF
0x00 A000
0x02 7FFF
CPU/SWIM/debug/ITC
32 interrupt vectors
Flash program memory
30/103 DS7147 Rev 10
registers
(8 Kbyte)
Reserved
MS36410V1
Page 31
STM8S003F3 STM8S003K3 Memory and register map
Tabl e 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Flash program memory 8 K 0x00 8000 0x00 9FFF
Data EEPROM 128 0x00 4000 0x00 407F

Table 7. Flash, Data EEPROM and RAM boundary addresses

Memory area Size (byte) Start address End address
RAM 1 K 0x00 0000 0x00 03FF

6.2 Register map

6.2.1 I/O port hardware register map

Address Block Register label Register name
0x00 5000
Table 8. I/O port hardware register map
Reset
status
PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 PA_DDR Port A data direction register 0x00
Port A
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005
PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 PB_DDR Port B data direction register 0x00
Port B
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A
PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX
0x00 500C PC_DDR Port C data direction register 0x00
Port C
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F
PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 PD_DDR Port D data direction register 0x00
Port D
0x00 5012 PD_CR1 Port D control register 1 0x02
(1)
(1)
(1)
(1)
0x00 5013 PD_CR2 Port D control register 2 0x00
DS7147 Rev 10 31/103
41
Page 32
Memory and register map STM8S003F3 STM8S003K3
Table 8. I/O port hardware register map (continued)
Address Block Register label Register name
0x00 5014
0x00 5015 PE_IDR Port E input pin value register 0xXX
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
1. Depends on the external circuitry.
Port E
Port F
PE_ODR Port E data output latch register 0x00
PF_ODR Port F data output latch register 0x00

6.2.2 General hardware register map

Reset
status
(1)
(1)
32/103 DS7147 Rev 10
Page 33
STM8S003F3 STM8S003K3 Memory and register map
Address Block Register label Register name
0x00 501E to
0x00 5059
0x00 505A
Table 9. General hardware register map
Reset
status
Reserved area (60 byte)
FLASH_CR1 Flash control register 1 0x00
0x00 505B FLASH_CR2 Flash control register 2 0x00
0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF
0x00 505D FLASH _FPR Flash protection register 0x00
Flash
0x00 505E FLASH _NFPR Flash complementary protection register 0xFF
0x00 505F FLASH _IAPSR
0x00 5060 to
0x00 5061
0x00 5062 Flash FLASH _PUKR
Flash in-application programming status
register
Reserved area (2 byte)
Flash Program memory unprotection
register
0x00
0x00
0x00 5063 Reserved area (1 byte)
0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00
0x00 5065 to
0x00 509F
0x00 50A0
EXTI_CR1 External interrupt control register 1 0x00
Reserved area (59 byte)
ITC
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 to
0x00 50B2
Reserved area (17 byte)
0x00 50B3 RST RST_SR Reset status register 0xXX
0x00 50B4 to
0x00 50BF
0x00 50C0
CLK_ICKR Internal clock control register 0x01
Reserved area (12 byte)
CLK
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)
0x00 50C3
CLK_CMSR Clock master status register 0xE1
0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
CLK
0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF
0x00 50C8 CLK_CSSR Clock security system register 0x00
0x00 50C9 CLK_CCOR Configurable clock control register 0x00
0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF
0x00 50CB Reserved area (1 byte)
(1)
DS7147 Rev 10 33/103
41
Page 34
Memory and register map STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Address Block Register label Register name
0x00 50CC
CLK_HSITRIMR HSI clock calibration trimming register 0x00
CLK
0x00 50CD CLK_SWIMCCR SWIM clock control register
0x00 50CE to
0x00 50D0
0x00 50D1
WWDG_CR WWDG control register 0x7F
Reserved area (3 byte)
Reset
status
0bXXXX
XXX0
WWDG
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to
0x00 50DF
0x00 50E0
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
IWDG
IWDG_KR IWDG key register 0xXX
Reserved area (13 byte)
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to
0x00 50EF
0x00 50F0
0x00 50F1 AWU_APR AWU asynchronous prescaler buffer register 0x3F
AWU
AWU_CSR1 AWU control/status register 1 0x00
Reserved area (13 byte)
0x00 50F2 AWU_TBR AWU timebase selection register 0x00
(2)
0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F
0x00 50F4 to
0x00 50FF
0x00 5200
SPI_CR1 SPI control register 1 0x00
Reserved area (12 byte)
0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
SPI
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0x00
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0x00
0x00 5208 to
0x00 520F
0x00 5210
I2C_CR1 I2C control register 1 0x00
0x00 5211 I2C_CR2 I
0x00 5212 I2C_FREQR I
2
C
I
0x00 5213 I2C_OARL I
0x00 5214 I2C_OARH I
Reserved area (8 byte)
2
C control register 2 0x00
2
C frequency register 0x00
2
C own address register low 0x00
2
C own address register high 0x00
0x00 5215 Reserved
34/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Memory and register map
Table 9. General hardware register map (continued)
Address Block Register label Register name
0x00 5216
I2C_DR I
0x00 5217 I2C_SR1 I
0x00 5218 I2C_SR2 I
0x00 5219 I2C_SR3 I
2
I
0x00 521A I2C_ITR I
C
0x00 521B I2C_CCRL I
0x00 521C I2C_CCRH I
0x00 521D I2C_TRISER I
0x00 521E I2C_PECR I
0x00 521F to
0x00 522F
0x00 5230
UART1_SR UART1 status register 0xC0
2
Reserved area (17 byte)
2
C data register 0x00
2
C status register 1 0x00
2
C status register 2 0x00
2
C status register 3 0x00
2
C interrupt control register 0x00
2
C clock control register low 0x00
2
C clock control register high 0x00
2
C TRISE register 0x02
C packet error checking register 0x00
Reset
status
0x00 5231 UART1_DR UART1 data register 0xXX
0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00
0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00
0x00 5234 UART1_CR1 UART1 control register 1 0x00
0x00 5235 UART1_CR2 UART1 control register 2 0x00
UART1
0x00 5236 UART1_CR3 UART1 control register 3 0x00
0x00 5237 UART1_CR4 UART1 control register 4 0x00
0x00 5238 UART1_CR5 UART1 control register 5 0x00
0x00 5239 UART1_GTR UART1 guard time register 0x00
0x00 523A UART1_PSCR UART1 prescaler register 0x00
0x00 523B to
0x00523F
Reserved area (21 byte)
DS7147 Rev 10 35/103
41
Page 36
Memory and register map STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Address Block Register label Register name
0x00 5250
0x00 5251 TIM1_CR2 TIM1 control register 2 0x00
0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00
0x00 5253 TIM1_ETR TIM1 external trigger register 0x00
0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 5255 TIM1_SR1 TIM1 status register 1 0x00
0x00 5256 TIM1_SR2 TIM1 status register 2 0x00
0x00 5257 TIM1_EGR TIM1 event generation register 0x00
0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00
0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00
0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00
0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00
0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00
0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00
0x00 525E TIM1_CNTRH TIM1 counter high 0x00
0x00 525F TIM1_CNTRL TIM1 counter low 0x00
TIM1
0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00
TIM1_CR1 TIM1 control register 1 0x00
Reset
status
0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF
0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF
0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00
0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00
0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00
0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00
0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00
0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00
0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00
0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00
0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00
0x00 526D TIM1_BKR TIM1 break register 0x00
0x00 526E TIM1_DTR TIM1 dead-time register 0x00
0x00 526F TIM1_OISR TIM1 output idle state register 0x00
0x00 5270 to
0x00 52FF
Reserved area (147 byte)
36/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Memory and register map
Table 9. General hardware register map (continued)
Address Block Register label Register name
0x00 5300
TIM2_CR1 TIM2 control register 1 0x00
Reset
status
0x00 5301 Reserved
0x00 5302 Reserved
0x00 5303 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5304 TIM2_SR1 TIM2 status register 1 0x00
0x00 5305 TIM2_SR2 TIM2 status register 2 0x00
0x00 5306 TIM2_EGR TIM2 event generation register 0x00
0x00 5307 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 5308 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 5309 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00
0x00 530A TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 530B TIM2_CCER2 TIM2 capture/compare enable register 2 0x00
TIM2
0x00 530C TIM2_CNTRH TIM2 counter high 0x00
0x00 530D TIM2_CNTRL TIM2 counter low 0x00
0x00 530E TIM2_PSCR TIM2 prescaler register 0x00
0x00 530F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5310 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5311 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
0x00 5312 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5313 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00
0x00 5314 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5315 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00
0x00 5316 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00
0x00 5317 to
0x00 533F
0x00 5340
TIM4_CR1 TIM4 control register 1 0x00
Reserved area (43 byte)
0x00 5341 Reserved
0x00 5342 Reserved
0x00 5343 TIM4_IER TIM4 interrupt enable register 0x00
0x00 5344 TIM4_SR TIM4 status register 0x00
TIM4
0x00 5345 TIM4_EGR TIM4 event generation register 0x00
0x00 5346 TIM4_CNTR TIM4 counter 0x00
0x00 5347 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5348 TIM4_ARR TIM4 auto-reload register 0xFF
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Memory and register map STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Address Block Register label Register name
0x00 5349 to
0x00 53DF
0x00 53E0 to
0x00 53F3
0x00 53F4 to
0x00 53FF
0x00 5400
ADC1 ADC_DBxR ADC data buffer registers 0x00
ADC _CSR ADC control/status register 0x00
Reserved area (153 byte)
Reserved area (12 byte)
Reset
status
0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5402 ADC_CR2 ADC configuration register 2 0x00
0x00 5403 ADC_CR3 ADC configuration register 3 0x00
0x00 5404 ADC_DRH ADC data register high 0xXX
0x00 5405 ADC_DRL ADC data register low 0xXX
0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00
0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00
ADC1
0x00 5408 ADC_HTRH ADC high threshold register high 0x03
0x00 5409 ADC_HTRL ADC high threshold register low 0xFF
0x00 540A ADC_LTRH ADC low threshold register high 0x00
0x00 540B ADC_LTRL ADC low threshold register low 0x00
0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00
0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00
0x00 540E ADC_AWCRH ADC analog watchdog control register high 0x00
0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00
0x00 5410 to
0x00 57FF
1. Depends on the previous reset source.
2. Write only register.
Reserved area (1008 byte)
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STM8S003F3 STM8S003K3 Memory and register map

6.2.3 CPU/SWIM/debug module/interrupt controller registers

Table 10. CPU/SWIM/debug module/interrupt controller registers
Address Block Register Label Register Name
0x00 7F00
A Accumulator 0x00
Reset
Status
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
(1)
0x00 7F05 XL X index register low 0x00
CPU
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to
0x00 7F5F
Reserved area (85 byte)
0x00 7F60 CPU CFG_GCR Global configuration register 0x00
0x00 7F70
ITC_SPR1 Interrupt software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF
ITC
0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF
0x00 7F78 to
0x00 7F79
Reserved area (2 byte)
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81 to
0x00 7F8F
Reserved area (15 byte)
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Memory and register map STM8S003F3 STM8S003K3
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Address Block Register Label Register Name
0x00 7F90
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM debug module control register 1 0x00
0x00 7F97 DM_CR2 DM debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to
0x00 7F9F
1. Accessible by debug module only
DM
DM_BK1RE DM breakpoint 1 register extended byte 0xFF
Reserved area (5 byte)
Reset
Status
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STM8S003F3 STM8S003K3 Interrupt vector mapping

7 Interrupt vector mapping

IRQ
no.
Source
block
Description

Table 11. Interrupt mapping

Wakeup from
Halt mode
Wakeup from
Active-halt mode
Vector address
- RESET Reset Yes Yes 0x00 8000
- TRAP Software interrupt - - 0x00 8004
0 TLI External top level interrupt - - 0x00 8008
1 AWU Auto wake up from halt - Yes 0x00 800C
2 CLK Clock controller - - 0x00 8010
3 EXTI0 Port A external interrupts Yes
(1)
Yes
(1)
0x00 8014
4 EXTI1 Port B external interrupts Yes Yes 0x00 8018
5 EXTI2 Port C external interrupts Yes Yes 0x00 801C
6 EXTI3 Port D external interrupts Yes Yes 0x00 8020
7 EXTI4 Port E external interrupts Yes Yes 0x00 8024
8 - Reserved 0x00 8028
9 - Reserved 0x00 802C
10 SPI End of transfer Yes Yes 0x00 8030
11 TI M1
TIM1 update/overflow/underflow/ trigger/break
- - 0x00 8034
12 TIM1 TIM1 capture/compare - - 0x00 8038
13 TIM2 TIM2 update /overflow - - 0x00 803C
14 TIM2 TIM2 capture/compare - - 0x00 8040
15 - Reserved 0x00 8044
16 - Reserved 0x00 8048
17 UART1 Tx complete - - 0x00 804C
18 UART1 Receive register DATA FULL - - 0x00 8050
19 I
2
CI
2
C interrupt Yes Yes 0x00 8054
20 - Reserved 0x00 8058
21 - Reserved 0x00 805C
22 ADC1
ADC1 end of conversion/analog watchdog interrupt
- - 0x00 8060
23 TIM4 TIM4 update/overflow - - 0x00 8064
24 Flash EOP/WR_PG_DIS - - 0x00 8068
Reserved
1. Except PA1
0x00 806C to
0x00 807C
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Option bytes STM8S003F3 STM8S003K3

8 Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.
Tabl e 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the

Table 12. Option bytes

Addr.
0x4800
0x4801
0x4802 NOPT1 NUBC[7:0] 0xFF
0x4803 Alternate
0x4804 NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
0x4805
0x4806 NOPT3 Reserved
0x4807
0x4808 NOPT4 Reserved
0x4809
0x480A NOPT5 NHSECNT[7:0] 0xFF
Option
name
Read-out protection (ROP)
User boot code (UBC)
function remapping (AFR)
Misc. option
Clock option
HSE clock startup
Option
byte no.
OPT0 ROP[7:0] 0x00
OPT1 UBC[7:0] 0x00
OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
OPT3 Reserved HSITRIM
OPT4 Reserved
OPT5 HSECNT[7:0] 0x00
76543210

Table 13. Option byte description

Option bits Factory
default setting
NHSI TRIM
LSI
_EN
NLSI
_EN
EXT CLK
NEXT
CLK
IWDG
_HW
NIWDG
_HW
CKAWU
SEL
NCKAW
USEL
WWDG
_HW
NWWDG
_HW
PRS
C1
NPR
SC1
WWDG
_HALT
NWWDG
_HALT
PRS
C0
NPR
SC0
0x00
0xFF
0x00
0xFF
Option byte no. Description
ROP[7:0] Memory readout protection (ROP)
OPT0
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.
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Table 13. Option byte description (continued)
Option byte no. Description
UBC[7:0] User boot code area
0x00: no UBC, no write-protection 0x01: Pages 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected
OPT1
OPT2
OPT3
Page 0 and page 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory-write protected.
Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details.
AFR[7:0]
Refer to the following section for alternate function remapping descriptions of bits [7:2] and [1:0] respectively.
HSITRIM: high-speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware
OPT4
OPT5
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles
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Option bytes STM8S003F3 STM8S003K3

8.1 Alternate function remapping bits

Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices

Option byte number Description
AFR7Alternate function remapping option 7
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: default alternate function 1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: default alternate function
OPT2
1: Port D0 alternate function = CLK_CCO.
AFR[4:2] Alternate function remapping option 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: default alternate function 1: Port A3 alternate function = SPI_NSS; port D2 alternate function TIM2_CH3
AFR0 Alternate function remapping option 0
Reserved.
1. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0
2. Refer to the pinout description.
(1)
(2)
(2)
(2)
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Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices

Option byte number Description
AFR7Alternate function remapping option 7
(1)
0: AFR7 remapping option inactive: default alternate function 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
(1)
0: AFR4 remapping option inactive: default alternate function
. 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN.
OPT2
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: default alternate function
(1)
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: default alternate function
(2)
(1)
1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate functions
(2)
(1)
1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1; port C7 alternate function = TIM1_CH2.
1. Refer to the pinout description.
2. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0.
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Electrical characteristics STM8S003F3 STM8S003K3
50 pF
STM8 pin

9 Electrical characteristics

9.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

9.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3

9.1.2 Typical values

= 25 °C and TA = T
A
Σ).
Amax
(given by
Unless otherwise specified, typical data are based on TA = 25 °C, V only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

9.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.
(mean ± 2 Σ).
Figure 7. Pin loading conditions
= 5 V. They are given
DD

9.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.
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V
IN
STM8 pin
Figure 8. Pin input voltage

9.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Tab le 16: Voltage characteristics,
Tabl e 17: Current characteristics and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability.
The device’s mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 16. Voltage characteristics

Symbol Ratings Min Max Unit
V
- VSSSupply voltage
DDx
Input voltage on true open drain pins
V
IN
- VDD| Variations between different power pins - 50
|V
DDx
- VSS| Variations between all the different ground pins - 50
|V
SSx
Input voltage on any other pin
(1)
(2)
(2)
-0.3 6.5
V
- 0.3 6.5
SS
V
- 0.3 V
SS
DD
+ 0.3
see Absolute maximum
V
ESD
Electrostatic discharge voltage
ratings (electrical
sensitivity) on page 86
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. I
must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
INJ(PIN)
cannot be respected, the injection current must be limited externally to the I injection is induced by V there is no positive injection current, and the corresponding V
while a negative injection is induced by VIN<VSS. For true open-drain pads,
IN>VDD
maximum must always be respected
IN
value. A positive
INJ(PIN)
V
mV
-
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Electrical characteristics STM8S003F3 STM8S003K3
Symbol Ratings Max.
I
VDD
I
VSS
Total current into V
Total current out of V

Table 17. Current characteristics

power lines (source)
DD
ground lines (sink)
SS
(2)
(2)
(1)
100
80
Output current sunk by any I/O and control pin 20
I
IO
Output current source by any I/Os and control pin -20
Injected current on NRST pin ±4
(3)(4)
I
INJ(PIN)
ΣI
INJ(PIN)
1. Data based on characterization results.
2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.
3. I
4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
5. When several inputs are submitted to a current injection, the maximum ΣI
must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
INJ(PIN)
cannot be respected, the injection current must be limited externally to the I injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I
ΣI
INJ(PIN)
positive and negative injected currents (instantaneous values). These results are based on characterization with
Σ
I
INJ(PIN)
Injected current on OSCIN pin ±4
Injected current on any other pin
(3)
Total injected current (sum of all I/O and control pins)
in the I/O port pin characteristics section does not affect the ADC accuracy.
maximum current injection on four I/O port pins of the device.
(5)
(5)
INJ(PIN)
is the absolute sum of the
INJ(PIN)
±4
±20
value. A positive
INJ(PIN)
Unit
mA
and

Table 18. Thermal characteristics

Symbol Ratings Value Unit
T
STG
T
J
Storage temperature range -65 to 150
Maximum junction temperature 150
°C
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9.3 Operating conditions

The device must be used in operating conditions that respect the parameters in Tab le 19. In addition, full account must be taken of all physical capacitor characteristics and tolerances.
Symbol Parameter Conditions Min Max Unit

Table 19. General operating conditions

V
f
CPU
V
DD
CAP
Internal CPU clock frequency - 0 16 MHz
Standard operating voltage - 2.95 5.5 V
C
: capacitance of external
EXT
capacitor
(1)
ESR of external capacitor
At 1 MHz
- 470 3300 nF
(2)
-0.3ohm
ESL of external capacitor - 15 nH
TSSOP20 - 238
D
= 85° C for suffix 6
T
A
Power dissipation at
(3)
P
LQFP32 - 330
T
A
T
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum values must be respected for the full application range.
2. This frequency of 1 MHz as a condition for V
3. To calculate P
characteristics on page 96) with the value for T Table 55: Thermal characteristics.
Ambient temperature for 6 suffix version
Junction temperature range
J
for 6 suffix version
), use the formula P
Dmax(TA
Figure 9. f
Maximum power dissipation -40 85
- -40 105
parameters is given by the design of the internal regulator.
CAP
= (T
Dmax
- TA)/Θ
Jmax
given in Table 19 above and the value for Θ
Jmax
CPUmax
versus VDD
(see Section 10.4: Thermal
JA
JA
mWUFQFPN20 - 220
°C
given in
f
Functionality not guaranteed in this area
CPU (MHz)
16
12
8
4
0
Functionality guaranteed
A
-40 to 85 °C
@T
2.95
4.0
Supply voltage
5.0
5.5
MS36411V1
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Electrical characteristics STM8S003F3 STM8S003K3

Table 20. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ
VDD rise time rate - 2 -
t
VDD
t
TEMP
V
IT+
V
IT-
V
HYS(BOR)
1. Reset is always generated after a t minimum operating voltage (V
fall time rate
V
DD
Reset release delay
Power-on reset threshold
Brown-out reset threshold
Brown-out reset hysteresis
(1)
delay. The application must ensure that VDD is still above the
TEMP
min) when the t
DD
-2-
rising - - 1.7 ms
V
DD
-2.62.72.85V
- 2.5 2.65 2.8 V
--70-mV
delay has elapsed.
TEMP
Max Unit
µs/V
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MSv36488V1
ESR
RLeak
ESL
C

9.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C V
CAP
pin. C
is specified in Table 19. Care should be taken to limit the series inductance
EXT
to less than 15 nH.
Figure 10. External capacitor C
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

9.3.2 Supply current characteristics

The current consumption is measured as described in Section 9.1.5: Pin input voltage.
Total current consumption in run mode
The MCU is placed under the following conditions:
All I/O pins in input mode with a static value at VDD or VSS (no load)
All peripherals are disabled (clock stopped by Peripheral Clock Gating registers)
except if explicitly mentioned.
EXT
EXT
to the
Subject to general operating conditions for VDD and TA.
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Electrical characteristics STM8S003F3 STM8S003K3
Table 21. Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter Conditions Typ Max
HSE crystal osc. (16 MHz) 2.3 -
= f
f
CPU
MASTER
Supply current in run mode,
f
= f
CPU
code
MASTER
executed from RAM
f
CPU
= f
MASTER
15.625 kHz
= f
f
CPU
CPU
= f
MASTER
MASTER
I
DD(RUN)
f
Supply current in run mode, code executed from Flash
f
f
f
CPU
CPU
CPU
= f
= f
= f
MASTER
MASTER
MASTER
15.625 kHz
= f
f
CPU
MASTER
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
= 16 MHz
HSE user ext. clock (16 MHz) 2 2.35
HSI RC osc. (16 MHz) 1.7 2
HSE user ext. clock (16 MHz) 0.86 -
/128 = 125 kHz
HSI RC osc. (16 MHz) 0.7 0.87
/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
= 128 kHz LSI RC osc. (128 kHz) 0.41 0.55
HSE crystal osc. (16 MHz) 4.5 -
= 16 MHz
HSE user ext. clock (16 MHz) 4.3 4.75
HSI RC osc.(16 MHz) 3.7 4.5
= 2 MHz HSI RC osc. (16 MHz/8)
(2)
0.84 1.05
/128 = 125 kHz HSI RC osc. (16 MHz) 0.72 0.9
/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
= 128 kHz LSI RC osc. (128 kHz) 0.42 0.57
(1)
Unit
mA
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Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V
Symbol Parameter Conditions Typ Max
HSE crystal osc. (16 MHz) 1.8 -
(1)
Unit
f
CPU
= f
MASTER
= 16 MHz
Supply current in run mode, code
CPU
= f
MASTER
/128 = 125 kHz
f
executed from RAM
f
CPU
= f
MASTER
/128 =
15.625 kHz
I
DD(RUN)
f
CPU
CPU
= f
= f
= 128 kHz LSI RC osc. (128 kHz) 0.41 0.55
MASTER
MASTER
= 16 MHz
f
Supply current in run mode, code executed from Flash
f
f
CPU
CPU
CPU
= f
= f
= f
MASTER
MASTER
MASTER
= 2 MHz HSI RC osc. (16 MHz/8)
/128 = 125 kHz HSI RC osc. (16 MHz) 0.72 0.9
/128 =
f
15.625 kHz
f
= f
CPU
1. Data based on characterization results.
2. Default clock configuration, measured with all peripherals off.
= 128 kHz LSI RC osc. (128 kHz) 0.42 0.57
MASTER
HSE user ext. clock (16 MHz) 2 2.3
HSI RC osc. (16 MHz) 1.5 2
HSE user ext. clock (16 MHz) 0.81 -
HSI RC osc. (16 MHz) 0.7 0.87
HSI RC osc. (16MHz/8) 0.46 0.58
HSE crystal osc. (16 MHz) 4 -
HSE user ext. clock (16 MHz) 3.9 4.7
HSI RC osc. (16 MHz) 3.7 4.5
(2)
0.84 1.05
HSI RC osc. (16 MHz/8) 0.46 0.58
mA
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Total current consumption in wait mode
Table 23. Total current consumption in wait mode at VDD = 5 V
Symbol Parameter Conditions Typ Max
HSE crystal osc. (16 MHz) 1.6 -
f
CPU
= f
MASTER
= 16 MHz
Supply
I
DD(WFI)
current in wait mode
f
f
CPU
CPU
= f
= f
MASTER
MASTER
/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88
/128 =
15.625 kHz
f
= f
CPU
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
Table 24. Total current consumption in wait mode at VDD = 3.3 V
MASTER
= 128 kHz LSI RC osc. (128 kHz) 0.4 0.54
HSE user ext. clock (16 MHz) 1.1 1.3
HSI RC osc. (16 MHz) 0.89 1.1
HSI RC osc. (16 MHz/8)
(2)
0.45 0.57
Symbol Parameter Conditions Typ Max
HSE crystal osc. (16 MHz) 1.1 -
(1)
Unit
(1)
mA
Unit
f
CPU
= f
MASTER
= 16 MHz
Supply
I
DD(WFI)
current in wait mode
f
f
CPU
CPU
= f
= f
/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88
MASTER
/128 =
MASTER
15.625 kHz
f
CPU
= f
MASTER
/128 =
15.625 kHz
1. Data based on characterization results.
2. Default clock configuration measured with all peripherals off.
HSE user ext. clock (16 MHz) 1.1 1.3
HSI RC osc. (16 MHz) 0.89 1.1
HSI RC osc. (16 MHz/8)
(2)
0.45 0.57
LSI RC osc. (128 kHz) 0.4 0.54
mA
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Total current consumption in active halt mode
Table 25. Total current consumption in active halt mode at VDD = 5 V
Conditions
Max at
Symbol Parameter
Main voltage
regulator
(2)
(MVR)
Flash mode
(3)
Clock source
Typ
85° C
(1)
Unit
Operating mode
On
I
DD(AH)
Supply current in active halt mode
Power-down mode
Operating mode
Off
Power-down mode 10 20
1. Data based on characterization results.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Table 26. Total current consumption in active halt mode at VDD = 3.3 V
Symbol Parameter
Main voltage
regulator
(2)
(MVR)
Flash mode
Operating mode
On
Power-down mode
I
DD(AH)
Supply current in active halt mode
Operating mode
Off
Power-down mode 10 18
Conditions
(3)
HSE crystal oscillator (16 MHz)
LSI RC oscillator (128 kHz)
HSE crystal oscillator (16 MHz)
LSI RC oscillator (128 kHz)
LSI RC oscillator
1030 -
200 260
970 -
150 200
66 85
(128 kHz)
Max
Typ
Clock source
at
85° C
(1)
HSE crystal osc. (16 MHz) 550 -
LSI RC osc. (128 kHz) 200 260
HSE crystal osc. (16 MHz) 970 -
LSI RC osc. (128 kHz) 150 200
66 80
LSI RC osc. (128 kHz)
µA
Unit
µA
1. Data based on characterization results.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
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Total current consumption in halt mode
Table 27. Total current consumption in halt mode at VDD = 5 V
Symbol Parameter Conditions Typ
Flash in operating mode, HSI clock after wakeup
I
DD(H)
Supply current in halt mode
Flash in power-down mode, HSI clock after wakeup
1. Data based on characterization results.
Table 28. Total current consumption in halt mode at VDD = 3.3 V
Symbol Parameter Conditions Typ
Flash in operating mode, HSI clock after wakeup
I
DD(H)
Supply current in halt mode
Flash in power-down mode, HSI clock after wakeup
1. Data based on characterization results.
63 75
6.0 20
Max at 85°C
Max at
85° C
60 75
4.5 17
Low-power mode wakeup times
Symbol Parameter Conditions Typ Max
t
WU(WFI)
t
WU(AH)
t
WU(H)
Wakeup time from wait mode to run mode
Wakeup time active halt mode to run mode.
Wakeup time from halt mode to run mode
(3)
(3)
(3)
Table 29. Wakeup times
0 to 16 MHz - -
f
= f
CPU
MASTER
MVR voltage
regulator on
MVR voltage
regulator off
Flash in operating mode
Flash in power-down mode
= 16 MHz. 0.56 -
Flash in operating
(5)
mode
(4)
Flash in power-down
(5)
mode
Flash in operating
(5)
mode
(4)
Flash in power-down
(5)
mode
(5)
(5)
HSI (after wakeup)
(6)
1
(6)
3
(6)
48
(6)
50
52 -
54 -
(1)
(1)
2
(2)
(6)
-
-
-
(1)
Unit
Unit
µA
Unit
µA
µs
1. Data guaranteed by design.
WU(WFI)
= 2 x 1/f
2. t
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
master
+ 7 x 1/f
CPU
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Total current consumption and timing in forced reset state
Table 30. Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Max
(1)
Unit
I
DD(R)
t
RESETBL
1. Data guaranteed by design.
2. Characterized with all I/Os tied to V
Supply current in reset state
Reset pin release to vector fetch - - 150 µs
Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/f
Symbol Parameter Typ. Unit
I
DD(TIM1)
I
DD(TIM2)
I
DD(TIM4)
I
DD(UART1)
I
DD(SPI)
I
DD(I2C)
I
DD(ADC1)
1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
TIM1 supply current
TIM2 supply current
TIM4 timer supply current
UART1 supply current
SPI supply current
I2C supply current
ADC1 supply current when converting
VDD = 5 V 400 -
= 3.3 V 300 -
V
DD
= 16 MHz, VDD = 5 V.
SS
CPU
.
= f
(2)
MASTER
Table 31. Peripheral current consumption
(1)
(1)
130
(1)
50
(1)
120
(1)
45
(1)
(1)
µA
210
µA
65
1000
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Current consumption curves
The following figures show the typical current consumption measured with code executing in RAM.
Figure 11. Typ. I
Figure 12. Typ. I
DD(RUN)
DD(RUN)
vs VDD, HSE user external clock, f
vs f
, HSE user external clock, VDD = 5 V
CPU
= 16 MHz
CPU
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Figure 13. Typ. I
DD(RUN)
vs VDD, HSI RC osc, f
= 16 MHz
CPU
Figure 14. Typ. I
DD(WFI)
vs. VDD HSE user external clock, f
= 16MHz
CPU
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Figure 15. Typ. I
Figure 16. Typ. I
DD(WFI)
DD(WFI)
vs. f
, HSE user external clock, VDD = 5 V
CPU
vs VDD, HSI RC osc, f
CPU
= 16 MHz
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V
HSEH
V
HSEL
External clock source
OSCIN
f
HSE
STM8
MS36489V2

9.3.3 External clock sources and timing characteristics

HSE user external clock
Subject to general operating conditions for VDD and TA.
Symbol Parameter Conditions Min Typ Max Unit
Table 32. HSE user external clock characteristics
f
HSE_ext
V
HSEH
V
HSEL
I
LEAK_HSE
1. Data based on characterization results.
User external clock source frequency
OSCIN input pin high level
(1)
voltage
OSCIN input pin low level
(1)
voltage
OSCIN input leakage current
Figure 17. HSE external clock source
0-16MHz
-
0.7 x V
DD
-V
DD
+ 0.3 V
V
V
SS
< V
V
SS
IN
< V
DD
-1 - +1 µA
- 0.3 x V
DD
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).
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OSCOUT
OSCIN
f
HSE
to core
C
L1
R
F
STM8
Resonator
Consumption
control
g
m
R
m
C
m
L
m
Resonator
C
L2
C
O
MS36490V3
Table 33. HSE oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE
R
C
I
DD(HSE)
g
t
SU(HSE)
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R Refer to crystal manufacturer for more details
3. Data based on characterization results.
4. t
SU(HSE)
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
External high speed oscillator frequency
Feedback resistor - - 220 - kΩ
F
(1)
Recommended load capacitance
(2)
HSE oscillator power consumption
Oscillator transconductance - 5 - - mA/V
m
(4)
Startup time VDD is stabilized - 1 - ms
is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
-1-16MHz
---20pF
C = 20 pF,
f
= 16 MHz
OSC
C = 10 pF,
= 16 MHz
f
OSC
--
--
6 (startup)
1.6 (stabilized)
6 (startup)
1.2 (stabilized)
value.
m
(3)
(3)
Figure 18. HSE oscillator circuit diagram
mA
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g
mcrit
2 Π× f
HSE
×()
2
Rm× 2Co C+()
2
=
HSE oscillator critical gm formula
Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1=CL2=C: Grounded external capacitance gm >> g
mcrit

9.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Symbol Parameter Conditions Min Typ Max Unit
Table 34. HSI oscillator characteristics
f
Frequency - - 16 - MHz
HSI
Accuracy of HSI oscillator
ACC
HSI
Accuracy of HSI oscillator (factory calibrated)
t
su(HSI)
I
DD(HSI)
1. See the application note.
2. Guaranteed by design.
3. Data based on characterization results.
HSI oscillator wakeup time including calibration
HSI oscillator power consumption
User-trimmed with the CLK_HSITRIMR register for given V conditions
= 5 V,
V
DD
(1)
DD
and TA
-40 °C ≤ TA ≤ 85 °C
- - - 1.0
- - 170 250
--1.0
(2)
-5 - 5
(2)
(3)
%
µs
µA
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Figure 19. Typical HSI frequency variation vs VDD at 4 temperatures
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35. LSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
Frequency - - 128 - kHz
LSI
t
su(LSI)
I
DD(LSI)
1. Guaranteed by design.
LSI oscillator wakeup time - - - 7
LSI oscillator power consumption - - 5 - µA
(1)
Figure 20. Typical LSI frequency variation vs VDD @ 4 temperatures
µs
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9.3.5 Memory characteristics

RAM and hardware registers
Symbol Parameter Conditions Min Unit
V
RM
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design.
2. Refer to Table 20 on page 50 for the value of V
Flash program memory and data EEPROM
General conditions: TA = -40 to 85 °C.
Symbol Parameter Conditions Min
Table 37. Flash program memory and data EEPROM
Table 36. RAM and hardware registers
Data retention mode
(1)
IT-max
Halt mode (or reset) V
.
(2)
IT-max
(1)
Typ Max Unit
V
V
t
prog
t
erase
N
t
RET
I
DD
Operating voltage
DD
(all modes, execution/write/erase)
f
≤ 16 MHz 2.95 - 5.5 V
CPU
Standard programming time (including erase) for byte/word/block
--6.06.6ms
(1 byte/4 bytes/64 bytes)
Fast programming time for 1 block (64 bytes)
--3.03.3ms
Erase time for 1 block (64 bytes) - - 3.0 3.3 ms
Erase/write cycles (program memory)
RW
Erase/write cycles (data memory)
(2)
(2)
100 - -
TA = 85 °C
100 k - -
Data retention (program memory) after 100 erase/write cycles at T
= 85 °C
A
10 k erase/write cycles at TA = 85 °C
Data retention (data memory) after 100 k erase/write cycles at T
= 85 °C
A
Supply current (Flash programming or erasing for 1 to 128 bytes)
T
= 55° C
RET
= 85° C 1.0 - -
T
RET
--2.0-mA
20 - -
20 - -
cycles
yearsData retention (data memory) after
1. Data based on characterization results.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
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9.3.6 I/O port pin characteristics

General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
Symbol Parameter Conditions Min Typ Max Unit
Input low level
V
IL
voltage
V
V
R
tR, t
Input high level
IH
voltage
Hysteresis
hys
Pull-up resistor VDD = 5 V, V
pu
Rise and fall time
F
(10% - 90%)
(1)
Input leakage
I
current,
lkg
analog and digital
I
lkg ana
I
lkg(inj)
Analog input leakage current
Leakage current in adjacent I/O
Table 38. I/O static characteristics
-0.3 - 0.3 x V
= 5 V
V
DD
0.7 x V
DD
-700- mV
= V
IN
SS
Fast I/Os Load = 50 pF
Standard and high sink I/Os Load = 50 pF
V
V
IN
IN
V
V
DD
DD
V
SS
V
SS
30 55 80 kΩ
--20
- - 125
--±A
--±250
Injection current ±4 mA - - ±1
-VDD + 0.3 V V
DD
(2)
(2)
ns
(3)
(3)
V
ns
nA
µA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results.
2. Data guaranteed by design.
3. Data based on characterization results.
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Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures
Figure 22. Typical pull-up resistance vs V
@ 4 temperatures
DD
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Figure 23. Typical pull-up current vs VDD @ 4 temperatures
1. The pull-up is a pure resistor (slope goes through 0).
Table 39. Output driving current (standard ports)
Symbol Parameter Conditions Min Max Unit
V
OL
Output low level with 4 pins sunk I
Output high level with 8 pins sourced IIO = 10 mA, V
V
OH
Output high level with 4 pins sourced I
1. Data based on characterization results.
Output low level with 8 pins sunk I
Table 40. Output driving current (true open drain ports)
= 10 mA, V
IO
= 4 mA, V
IO
= 4 mA, V
IO
= 5 V - 2
DD
= 3.3 V - 1
DD
= 5 V 2.8 -
DD
= 3.3 V 2.1
DD
(1)
(1)
-
Symbol Parameter Conditions Max Unit
I
V
1. Data based on characterization results.
Output low level with 2 pins sunk
OL
= 10 mA, V
IO
= 10 mA, V
IO
IIO = 20 mA, V
= 5 V 1
DD
= 3.3 V 1.5
DD
= 5 V 2
DD
(1)
(1)
V
V
VI
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Table 41. Output driving current (high sink ports)
Symbol Parameter Conditions Min Max Unit
Output low level with 8 pins sunk IIO = 10 mA, V
V
Output low level with 4 pins sunk I
OL
Output low level with 4 pins sunk IIO = 20 mA, V
Output high level with 8 pins sourced IIO = 10 mA, V
V
Output high level with 4 pins sourced I
OH
Output high level with 4 pins sourced I
1. Data based on characterization results.
= 10 mA, V
IO
= 10 mA, V
IO
= 20 mA, V
IO
= 5 V - 0.8
DD
= 3.3 V - 1.0
DD
= 5 V - 1.5
DD
= 5 V 4.0 -
DD
= 3.3 V 2.1
DD
= 5 V 3.3
DD
(1)
(1)
(1)
(1)
-
-
Typical output level curves
Figure 25 to Figure 32 show typical output level curves measured with output on a single
pin.
Figure 24. Typ. VOL @ VDD = 5 V (standard ports)
V
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Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports)
Figure 26. Typ. V
@ VDD = 5 V (true open drain ports)
OL
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Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports)
Figure 28. Typ. V
@ VDD = 5 V (high sink ports)
OL
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Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports)
Figure 30. Typ. V
DD - VOH
@ VDD = 5 V (standard ports)
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Figure 31. Typ. V
Figure 32. Typ. V
DD - VOH
DD - VOH
@ VDD = 3.3 V (standard ports)
@ VDD = 5 V (high sink ports)
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Figure 33. Typ. V
DD - VOH
@ VDD = 3.3 V (high sink ports)
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9.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ
V
IL(NRST)
IH(NRST)
V
OL(NRST)
R
PU(NRST)
t
IFP(NRST)
t
INFP(NRST)
t
OP(NRST)
1. Data based on characterization results.
2. The R
3. Data guaranteed by design.
NRST input low level voltage
NRST input high level voltage
NRST output low level voltage
NRST pull-up resistor
NRST input filtered pulse
NRST Input not filtered pulse
NRST output pulse
pull-up equivalent resistor is based on a resistive transistor.
PU
Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures
Table 42. NRST pin characteristics
(1)
(1)
(1)
(2)
(3)
(3)
(1)
- -0.3 V - 0.3 x V
- 0.7 x V
IOL= 2 mA - - 0.5
-305580kΩ
---75ns
-500--ns
-20--µs
DD
1)
Max Unit
DD
-VDD + 0.3
VV
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Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures
Figure 36. Typical NRST pull-up current vs V
@ 4 temperatures
DD
The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in
Tabl e 38. Otherwise the reset is not taken into account internally. For power consumption
sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRST signal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF.
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MSv36491V1
External
reset
circuit
0.1 μF
NRST
Filter
STM8
(Optional)
V
DD
R
PU
Figure 37. Recommended reset pin protection
9.3.8

SPI serial peripheral interface

Unless otherwise specified, the parameters given in Tab le 43 are derived from tests performed under ambient temperature, f conditions. t
MASTER
= 1/f
MASTER
.
MASTER
frequency and VDD supply voltage
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
t
su(NSS)
t
h(NSS)
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
t
a(SO)
t
dis(SO)
t
v(SO)
t
v(MO)
t
h(SO)
t
h(MO)
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
SPI clock frequency
SPI clock rise and fall time Capacitive load: C = 30 pF - 25
(1)
NSS setup time Slave mode 4 x t
(1)
NSS hold time Slave mode 70 -
(1)
SCK high and low time Master mode t
(1)
(1)
Data input setup time
(1)
(1)
Data input hold time
(1)
(1)(2)
Data output access time Slave mode - 3 x t
(1)(3)
Data output disable time Slave mode 25 -
(1)
Data output valid time Slave mode (after enable edge) - 65
(1)
Data output valid time Master mode (after enable edge) - 30
(1)
Data output hold time
(1)
Table 43. SPI characteristics
Master mode 0 8
Slave mode 0 7
MASTER
/2 - 15 t
SCK
Master mode 5 -
Slave mode 5 -
Master mode 7 -
Slave mode 10 -
Slave mode (after enable edge) 27 -
Master mode (after enable edge) 11 -
SCK
-
/2 + 15
MASTER
MHz
ns
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Electrical characteristics STM8S003F3 STM8S003K3
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 38. SPI timing diagram - slave mode and CPHA = 0
Figure 39. SPI timing diagram - slave mode and CPHA = 1
NSS input
SU(NSS)
t
CPHA=1 CPOL=0
CPHA=1
SCK input
CPOL=1
MISO
OUTPUT
MOSI
INPUT
1. Measurement points are done at CMOS levels: 0.3 V
t
w(SCKH)
tw(SCKL)
ta(SO)
t
su(SI)
tv(SO)
MSB OUT
th(SI)
MSB IN
tc(SCK)
and 0.7 V
DD
DD.
BIT6 OUT
BIT 1 IN
th(SO)
th(NSS)
tr(SCK) tf(SCK)
LSB IN
(1)
tdis(SO)
LSB OUT
ai14135b
78/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Electrical characteristics
ai14136c
SCK Output
CPHA=0
MOSI
OUTPUT
MISO
INP UT
CPHA=0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
MSB IN
BIT6 IN
MSB OUT
Figure 40. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3 V
and 0.7 V
DD
DD.
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Electrical characteristics STM8S003F3 STM8S003K3

9.3.9 I2C interface characteristics

Symbol Parameter
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
t
su(STO)
t
w(STO:STA)
C
1. f
MASTER
Data based on standard I
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
3. time
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
4. undefined region of the falling edge of SCL
SCL clock low time 4.7 - 1.3 -
SCL clock high time 4.0 - 0.6 -
SDA setup time 250 - 100 -
SDA data hold time 0
SDA and SCL rise time - 1000 - 300
SDA and SCL fall time - 300 - 300
START condition hold time 4.0 - 0.6 -
Repeated START condition setup time 4.7 - 0.6 -
STOP condition setup time 4.0 - 0.6 - µs
STOP to START condition time (bus free)
Capacitive load for each bus line - 400 - 400 pF
b
, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
Table 44. I2C characteristics
Standard mode I
(2)
Min
(3)
4.7 - 1.3 - µs
2
C protocol requirement, not tested in production
2
CFast mode I2C
(2)
Max
-0
Min
(4)
(2)
Max
900
(3)
(1)
(2)
Unit
µs
ns
µs
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STM8S003F3 STM8S003K3 Electrical characteristics
2
Figure 41.
Typical application with I
C bus and timing diagram
V
DD
V
DD
4.7 kΩ 4.7 kΩ 100 Ω
SDA
I²C bus
SCL
100 Ω
START
SD A
t
f(SDA)
SCL
t
w(SCLH)
t
h(STA)
t
r(SDA)
t
r(SCL)
t
w(SCLL)
t
su(SDA)
t
h(SDA)
t
f(SCL)
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x V
t
su(STA)
DD
STM8
S TAR T REPEATED
STOP
t
su(STO)
START
t
su(STA:STO)
ai17490V2
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Electrical characteristics STM8S003F3 STM8S003K3

9.3.10 10-bit ADC characteristics

Subject to general operating conditions for V
DDA
, f
MASTER
, and TA unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
f
V
C
t
t
STAB
t
CONV
1. During the sample time the input capacitance C
ADC clock frequency
ADC
Conversion voltage range
AIN
Internal sample and hold
ADC
capacitor
(1)
Sampling time
S
Wakeup time from standby - - 7 - µs
Total conversion time (including sampling time, 10-bit resolution)
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t
Table 45. ADC characteristics
V
V
(1)
AIN
3 to 5.5 V 1 - 4
DDA =
4.5 to 5.5 V 1 - 6
DDA =
-V
--3-pF
f
= 4 MHz - 0.75 -
ADC
= 6 MHz - 0.5 -
f
ADC
= 4 MHz 3.5 µs
f
ADC
= 6 MHz 2.33 µs
f
ADC
-141/f
(3 pF max) can be charged/discharged by the external
depend on programming.
S
SS
MHz
-VDDV
µs
ADC
Table 46. ADC accuracy with R
< 10 kΩ , V
AIN
DD
= 5 V
Symbol Parameter Conditions Typ Max
f
= 2 MHz 1.6 3.5
ADC
|ET| Total unadjusted error
|E
| Offset error
O
|E
| Gain error
G
|E
| Differential linearity error
D
(2)
(2)
|EL| Integral linearity error
(2)
(2)
(2)
= 4 MHz 2.2 4
f
ADC
f
= 6 MHz 2.4 4.5
ADC
f
= 2 MHz 1.1 2.5
ADC
= 4 MHz 1.5 3
f
ADC
f
= 6 MHz 1.8 3
ADC
f
= 2 MHz 1.5 3
ADC
f
= 4 MHz 2.1 3
ADC
= 6 MHz 2.2 4
f
ADC
f
= 2 MHz 0.7 1.5
ADC
f
= 4 MHz 0.7 1.5
ADC
= 6 MHz 0.7 1.5
f
ADC
f
= 2 MHz 0.6 1.5
ADC
f
= 4 MHz 0.8 2
ADC
= 6 MHz 0.8 2
f
ADC
(1)
Unit
LSB
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STM8S003F3 STM8S003K3 Electrical characteristics
1. Data based on characterization results.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I ΣI
in Section 9.3.6 does not affect the ADC accuracy.
INJ(PIN)
INJ(PIN)
and
Symbol Parameter Conditions Typ Max
|ET| Total unadjusted error
|E
| Offset error
O
|E
| Gain error
G
|E
| Differential linearity error
D
|EL| Integral linearity error
1. Data based on characterization results.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I ΣI
INJ(PIN)
Table 47. ADC accuracy with R
(2)
(2)
(2)
(2)
(2)
in Section 9.3.6 does not affect the ADC accuracy.
AIN
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
f
ADC
< 10 kΩ R
AIN
, V
= 3.3 V
DD
= 2 MHz 1.6 3.5
= 4 MHz 1.9 4
= 2 MHz 1 2.5
= 4 MHz 1.5 2.5
= 2 MHz 1.3 3
= 4 MHz 2 3
= 2 MHz 0.7 1.0
= 4 MHz 0.7 1.5
= 2 MHz 0.6 1.5
= 4 MHz 0.8 2
(1)
INJ(PIN)
and
Unit
LSB
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Electrical characteristics STM8S003F3 STM8S003K3
E
O
E
G
1LSB
IDEAL
1LSB
IDEAL
V
DDAVSSA
1024
----------------------------- ------------=
1023
1022 1021
5
4
3
2
1
0
7
6
1234567
1021102210231024
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
V
SSA
AINx
STM8
V
DD
I
L
±1µA
V
T
0.6V
V
T
0.6V
C
ADC
V
AIN
R
AIN
10-bit A/D conversion
C
AIN
Figure 42. ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
E
T
E
= Offset error: deviation between the first actual transition and the first ideal one.
O
EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. E
= Integral linearity error: maximum deviation between any actual transition and the end point correlation
L
line.
Figure 43. Typical application with ADC
84/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Electrical characteristics

9.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
and VSS
DD
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Symbol Parameter Conditions Level/class
V
V
Voltage limits to be applied on any I/O pin to
FESD
induce a functional disturbance
Fast transient voltage burst limits to be applied through 100pF on VDD and V
EFTB
to induce a functional disturbance
Table 48. EMS data
V
DD
f
MASTER
conforming to IEC 61000-4-2
V
DD
f
MASTER
conforming to IEC 61000-4-4
SS
pins
= 3.3 V, TA = 25 °C,
= 16 MHz,
= 3.3 V, TA = 25 °C,
= 16 MHz,
2B
4A
(1)
(1)
1. Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 ­EMC guidelines for STM8Smicrocontrollers.
DS7147 Rev 10 85/103
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Electrical characteristics STM8S003F3 STM8S003K3
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading.
Table 49. EMI data
Conditions
Symbol Parameter
General conditions
V
= 5 V
DD
= 25 °C
T
S
Peak level
EMI
A
LQFP32 package conforming to IEC
EMI level - 2.5 2.5 -
1. Data based on characterization results.
61967-2
Max f
HSE/fCPU
Monitored
frequency band
16 MHz/
8 MHz
0.1 MHz to 30 MHz 5 5
130 MHz to 1 GHz 5 5
(1)
Unit
16 MHz/
16 MHz
dBµV30 MHz to 130 MHz 4 5
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (one positive then one negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: the Human Body Model (HBM). This test conforms to the JESD22­A114A/A115A standard. For more details, refer to the application note AN1181.
Table 50. ESD absolute maximum ratings
Symbol Ratings Conditions Class
V
ESD(HBM)
V
ESD(CDM)
1. Data based on characterization results.
Electrostatic discharge voltage (Human body model)
Electrostatic discharge voltage (Charge device model)
TA = 25°C, conforming to JESD22-A114
TA= 25°C, conforming to JESD22-C101
86/103 DS7147 Rev 10
Maximum
value
(1)
Unit
A 4000 V
IV 1000 V
Page 87
STM8S003F3 STM8S003K3 Electrical characteristics
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
A current injection (applied to each input, output and configurable I/O pin) is performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Symbol Parameter Conditions Class
Table 51. Electrical sensitivities
(1)
LU Static latch-up class
TA = 25 °C A
= 85 °C A
T
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).
DS7147 Rev 10 87/103
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Package information STM8S003F3 STM8S003K3
D
D1
D3
E3
E1
E
1
8
9
16
17
24
25
32
A1
L1
L
K
A1
A2
A
c
b
GAUGE PLANE
0.25 mm
SEATING
PLANE
C
PIN 1 IDENTIFICATION
ccc
C
5V_ME_V2
e

10 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark.

10.1 LQFP32 package information

Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

1. Drawing is not to scale.
88/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Package information
5V_FP_V2
1
8
9
16
17
24
25
32
9.70
7.30
7.30
1.20
0.30
0.50
1.20
6.10
9.70
0.80
6.10

Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data

millimeters inches
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
(1)
k 0°3.5°7° 0°3.5°7°
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint

1. Dimensions are expressed in millimeters.
DS7147 Rev 10 89/103
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Package information STM8S003F3 STM8S003K3
MS37767V1
Product identification
(1)
Pin 1 identifier
Revision code
Date code
YWW
R
Standard ST logo
STM8S003
K6T6C
Device marking for LQFP32
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 46. LQFP32 marking example (package top view)

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity.
90/103 DS7147 Rev 10
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STM8S003F3 STM8S003K3 Package information
YA_ME_V3
1
20
C
c
L
EE1
D
A2
A
k
eb
10
11
A1
L1
aaa
SEATING
PLANE
C
GAUGE PLANE
0.25 mm
PIN 1 IDENTIFICATION

10.2 TSSOP20 package information

Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
1. Drawing is not to scale.
Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters inches
Symbol
Min. Typ. Max. Min. Typ. Max.
(1)
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
(2)
D
6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
(3)
E1
4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k - -
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
3. Dimension "E1" does not include interlead Flash or protrusions. Interlead Flash or protrusions shall not
shall not exceed 0.15mm per side.
exceed 0.25mm per side.
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Package information STM8S003F3 STM8S003K3
YA_FP_V1
7.10 4.40
0.25
0.25
6.25
1.35
0.40
0.65
1.35
1
20 11
10
MS37768V1
Product identification
(1)
Pin 1 identifier
Revision code
Date code
YWW
R
Standard ST logo
8S003F3P6
Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
1. Dimensions are expressed in millimeters.
Device marking for TSSOP20
The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 49. TSSOP20 marking example (package top view)

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
92/103 DS7147 Rev 10
qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity.
Page 93
STM8S003F3 STM8S003K3 Package information
A0A5_ME_V4
15
16
20
1
5
D
e
b
e
E
A1
A
ddd
L2
10
L1
A3
L5
D
E
TOP VIEW
SIDE VIEWBOTTOM VIEW
Pin 1
L3
E1
D1

10.3 UFQFPN20 package information

Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
1. Drawing is not to scale.
Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters inches
Symbol
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.060 -
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
D1 - 2.000 - - 0.0790 -
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E1 - 2.000 - - 0.07905 -
L1 0.500 0.550 0.600 0.0197 0.0217 0.0236
L2 0.300 0.350 0.400 0.0118 0.0138 0.0157
L3 - 0.200 - - 0.0079 -
L5 - 0.150 - - 0.0059 -
DS7147 Rev 10 93/103
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Package information STM8S003F3 STM8S003K3
Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters inches
Symbol
Min Typ Max Min Typ Max
b 0.180 0.250 0.300 0.0071 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
(1)
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
1. Dimensions are expressed in millimeters.
94/103 DS7147 Rev 10
A0A5_FP_V2
Page 95
STM8S003F3 STM8S003K3 Package information
MS37769V1
Product identification
(1)
Dot (pin 1)
Revision code
Date code
YWW
R
S033
Device marking for UFQFPN20
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 52. UFQFPN20 marking example (package top view)

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity.
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Package information STM8S003F3 STM8S003K3

10.4 Thermal characteristics

The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Tabl e 19: General operating conditions.
The maximum chip-junction temperature, T
, in degrees Celsius, may be calculated
Jmax
using the following equation:
T
Jmax
= T
Amax
+ (P
Dmax
x ΘJA)
Where:
T
•Θ
P
P
is the maximum ambient temperature in ° C
Amax
is the package junction-to-ambient thermal resistance in ° C/W
JA
is the sum of P
Dmax
is the product of I
INTmax
INTmax
DD
and P
I/Omax (PDmax
= P
INTmax
+ P
and VDD, expressed in Watts. This is the maximum chip
I/Omax
)
internal power.
P
P VOH/I
Symbol Parameter Value Unit
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
represents the maximum power dissipation on output pins, where:
I/Omax
I/Omax =
Θ
JA
Σ (VOL*IOL) + Σ((VDD-V
of the I/Os at low and high level in the application.
OH
OH)*IOH
), and taking account of the actual VOL/I

Table 55. Thermal characteristics

Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm
Thermal resistance junction-ambient TSSOP20 - 4.4 mm
Thermal resistance junction-ambient UFQFPN20 -3 x 3 mm
(1)
60
84
90
OL
°C/W
and

10.4.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.
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STM8S003F3 STM8S003K3 Package information

10.4.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 53: STM8S003F3/K3 value line ordering information scheme
(1)
).
The following example shows how to calculate the temperature range needed for a given application.
Assuming the following application conditions:
Maximum ambient temperature T
I
= 8 mA, VDD = 5.0 V
DDmax
= 75 °C (measured according to JESD51-2)
Amax
Maximum 20 I/Os used at the same time in output at low level with
I
= 8 mA, VOL= 0.4 V
OL
P
INTmax =
P
Dmax
Thus: P
Using the values obtained in Section Table 55.: Thermal characteristics T
8 mA x 5.0 V = 400 mW
= 400 mW + 64 mW
= 464 mW
Dmax
is calculated
Jmax
as follows for LQFP32 7 x 7 mm = 60 °C/W:
T
= 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C
Jmax
This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
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Ordering information STM8S003F3 STM8S003K3
STM8 S 003 K 3 T 6 TR
Product class
STM8 microcontroller
Pin count
F = 20 pins K = 32 pins
Package type
T = LQFP P = TSSOP U = UFQFPN
Example:
Sub-family type
(2)
00x = Value line sub-family 003 = low density
Family type
S = standard
Temperature range
6 = -40 °C to 85 °C
Program memory size
3 = 8 Kbyte
Package pitch
No character = 0.5 mm or 0.65 mm
(3)
C = 0.8 mm
(4)
Packing
No character = Tray or tube
TR = Tape and reel

11 Ordering information

Figure 53. STM8S003F3/K3 value line ordering information scheme
(1)
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you.
2. Refer to Table 1: STM8S003F3/K3 value line features for detailed description.
3. TSSOP and UFQFPN packages.
4. LQFP package.
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12 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.
STice key features
Occurrence and time profiling and code coverage (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows users to specify the components users need to meet their
development requirements and adapt to future requirements
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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12.2 Software tools

STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 16 is available.

12.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.
Kbytes of code

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface.
Available toolchains include:
Cosmic C compiler for STM8 – One free version that outputs up to 16 Kbytes of code
is available. For more information, see www.cosmic-software.com.
Raisonance C compiler for STM8 – One free version that outputs up to 16 Kbytes of
code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows users to assemble and link the user application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8.
For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
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