Page 1
STM6510
Dual push-button Smart ResetTM with capacitor-adjustable delays
Features
■ Dual Smart Reset™ push-button inputs with
capacitor-adjustable extended reset setup
delay (t
■ Capacitor-adjustable reset pulse duration
(t
REC
■ Power-on reset
–RST
■ Factory-programmable thresholds to monitor
V
CC
■ Operating voltage 1.0 V (active-low output
valid) to 5.5 V
■ Low supply current (1.4 µA)
■ Operating temperature: industrial grade –40 °C
to +85 °C
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
)
SRC
)
active-low, open-drain
in the range of 1.575 to 4.625 V typ.
TDFN8 (DG)
2 mm x 2 mm
Applications
■ Mobile phones, smartphones
■ e-books
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability
February 2010 Doc ID 16788 Rev 2 1/26
www.st.com
1
Page 2
Contents STM6510
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Smart Reset™ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 STM6510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.2 Ground (V
1.3.3 Smart Reset™ push-button inputs (SR0
1.3.4 Adjustable delay of Smart Reset™ input (SRC pin) . . . . . . . . . . . . . . . . 9
1.3.5 Reset output (RST
1.3.6 Adjustable reset timeout (TREC
2 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
, SR1) . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
pin) . . . . . . . . . . . . . . . . . . . . . . . . 10
ADJ
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26 Doc ID 16788 Rev 2
Page 3
STM6510 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. tSRC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. tREC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Possible VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 18
Table 9. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 19
Table 10. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 16788 Rev 2 3/26
Page 4
List of figures STM6510
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Supply current (I
Figure 8. Smart Reset™ delay (t
Figure 9. Reset timeout period (t
Figure 10. Reset threshold (V
Figure 11. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
RST
) vs. temperature, C
SRC
) vs. temperature, C
REC
= 0.56 µF . . . . . . . . . . . . . . . . . . . . . . 11
SRC
= 0.01 µF . . . . . . . . . . . . . . . . . . . . . 12
tREC
) vs. temperature, “S” threshold option, VCC falling. . . . . . . . . . . . . 12
4/26 Doc ID 16788 Rev 2
Page 5
STM6510 Description
1 Description
1.1 Smart Reset™ devices
The Smart Reset™ device family STM65xx provides a useful feature that ensures
inadvertent short reset push-button closures do not cause system resets. This is done by
implementing an extended Smart Reset™ input delay (t
input levels and setup delay are met, the device generates an output reset pulse with userprogrammable timeout period (t
REC
).
The typical application hookup shows that the dual Smart Reset™ inputs can be also
connected to the applications interrupt to allow the control of both the interrupt pin and the
hard reset functions. If the push-buttons are closed for a short time, the processor is only
interrupted. If the system still does not respond properly, holding the push-buttons for the
extended setup time (t
) causes a hard reset of the processor through the reset output.
SRC
The Smart Reset™ feature helps significantly increase system stability.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset
circuits targeted at applications such as MP3 players, portable navigation devices or mobile
phones, generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset™
inputs (SRx). The delayed Smart Reset™ setup time (t
adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed
setup period ignores switch closures shorter than t
SRC
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST
output(s) with or without an internal pull-up resistor or push-pull as output options, with or
without the power-on reset function.
). Once the valid Smart Reset™
SRC
) options are adjustable by
SRC
, thus preventing undesired resets.
)
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V
reset output remains asserted for the reset timeout period (t
voltage goes above the specified threshold.
1.2 STM6510
The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™
setup delay (t
STM6510 feature is adjustable output reset pulse time t
(C
).
tREC
Additionally, the V
reset output goes active and remains active while V
defined duration of the reset pulse t
drops below the specified threshold. The
CC
) programmed by an external capacitor on the SRC pin. An additional
SRC
REC
is monitored and if it drops below the selected V
CC
REC
.
is below the V
CC
) after the monitored supply
REC
by adding an external capacitor
threshold, the
RST
threshold, plus the
RST
Doc ID 16788 Rev 2 5/26
Page 6
Description STM6510
Figure 1. Logic diagram
V
CC
SR0
SR1
SRC
STM6510
V
SS
RST
TREC
ADJ
AM00389a
Figure 2. Pin connections
STM
6510
8
V
CC
7
SR0
6
TREC
ADJ
5
SRC
Table 1. Signal names
RST
V
SS
SR1
NC
1
2
3
4
Symbol Input/output Description
RST
SR0 Input
SR1 Input
SRC Input
TREC
ADJ
Output Reset output, active-low (open-drain).
Primary push-button Smart Reset™ input. Active-low, internal 65 kΩ
pull-up resistor to V
CC
.
Secondary push-button Smart Reset™ input. Active-low, internal 65 kΩ
pull-up resistor to V
CC
.
Smart Reset™ input delay setup control. Connect an external capacitor
to this pin to adjust the delay setup time (t
Input
Input pin for t
capacitor (C
reset pulse duration adjustment. Connect an external
REC
) to this pin to determine t
tREC
Supply voltage input. Power supply for the device and an input for the
V
CC
Supply
monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between V
V
SS
Supply Ground
NC No connect (not bonded); should be connected to V
).
SRC
.
REC
and VSS pins.
CC
AM00390
SS.
6/26 Doc ID 16788 Rev 2
Page 7
STM6510 Description
Figure 3. Block diagram
V
CC
65 kΩ 65 kΩ
V
RST
COMPARE
t
REC
generator
RST
SR0
SR1
SRC
Logic
TREC
C
ADJ
tREC
AM00391a
Doc ID 16788 Rev 2 7/26
Page 8
Description STM6510
Figure 4. Single-button Smart Reset™ typical hookup
V
CC
100 kΩ
C
RESET
SRC
INT/
NMI
PUSH-BUTTON
SWITCH
C
tREC
TREC
ADJ
STM6510
V
CC
RST
SRC
SR1
V
SR0
SS
Note: When only one Smart Reset™ input push-button is used, tie both the SR
Figure 5. Dual-button Smart Reset™ typical hookup
V
CC
V
CC
MCU
V
SS
AM04870v1
inputs together.
V
CC
RST
SS
SRC
SR1
SR0
C
SRC
PUSH-BUTTON
SWITCH
C
tREC
TREC
ADJ
STM6510
V
8/26 Doc ID 16788 Rev 2
100 kΩ
RESET
INT/
NMI
PUSH-BUTTON
SWITCH
V
CC
MCU
V
SS
AM004871v1
Page 9
STM6510 Description
1.3 Pin descriptions
1.3.1 Power supply (VCC)
This pin is used to provide the power to the Smart Reset™ device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
the V
1.3.2 Ground (VSS)
This is the supply ground for the device.
1.3.3 Smart Reset™ push-button inputs (SR0, SR1)
and VSS pins.
CC
Both SR0 and SR1 need to be held active at the same time for at least t
reset output pulse. Include an internal 65 kΩ
pull-up resistor to V
Figure 6. Timing waveforms
SR0
SR1
RST
t
SRC
t
REC
1.3.4 Adjustable delay of Smart Reset™ input (SRC pin)
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (C
desired value of setup time (t
Calculated t
Table 2. t
Calculated C
value [µF]
and C
SRC
SRC
SRC
SRC
programmed by an ideal external capacitor
Min. Typ. Max.
).
SRC
examples are given in Table 2. Refer also to Table 6.
Setup delay t
), which is tied to ground to provide the
SRC
(1)(2)
[s]
SRC
SRC
for each input.
CC
to activate the
AM00393
Closest common
C
value [µF]
SRC
0.2 2 3 4 0.22
0.3 3 4.5 6 0.33
0.6 6 9 12 0.56
11015201
1. Example calculations based on an ideal capacitor. During application design and component selection it
should be considered that the current flowing into the external t
the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB
environment should be used to prevent t
value of C
2. In case of repeated activations of the t
activations to fully discharge C
is 0.01 µF.
SRC
, so that the next t
SRC
accuracy from being affected. A recommended minimum
SRC
counter, an interval of 10 ms min. is needed between the
SRC
is as specified.
SRC
programming capacitor (C
SRC
SRC
) is on
Doc ID 16788 Rev 2 9/26
Page 10
Description STM6510
1.3.5 Reset output (RST)
RST is active-low, open-drain.
1.3.6 Adjustable reset timeout (TREC
The reset timeout (t
Calculated t
Table 3. t
Calculated C
value [µF]
0.001 10 15 20 0.001
0.002 20 30 40 0.0022
0.01 100 150 200 0.01
0.014 140 210 280 0.015
0.028 280 420 560 0.027
0.056 560 840 1120 0.056
0.112 1120 1680 2240 0.1
1. Example calculations based on an ideal capacitor. During application design and component selection it
should be considered that the current flowing into the external t
the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB
environment should be used to prevent t
value of C
2. In case of repeated activations of the t
intervals to fully discharge C
and C
REC
REC
tREC
is 0.001 µF.
tREC
) is adjustable by connecting an external capacitor C
REC
examples are given in Table 3. Refer also to Table 6.
tREC
programmed by an ideal external capacitor
Min. Typ. Max.
, so that the next t
tREC
t
accuracy from being affected. A recommended minimum
REC
counter, an interval of 10 ms min. is needed between t
REC
ADJ
REC
pin)
(1)(2)
[ms]
is as specified.
REC
programming capacitor (C
REC
to this pin.
tREC
Closest common
C
value [µF]
tREC
) is on
tREC
REC
10/26 Doc ID 16788 Rev 2
Page 11
STM6510 Typical operating characteristics
2 Typical operating characteristics
Figure 7. Supply current (ICC) vs. temperature
2.4
2.2
2
1.8
1.6
1.4
[μA]
CC
I
-60 -40 -20 0 20 40 60 80 100 120 140
Figure 8. Smart Reset™ delay (t
1.2
0.8
0.6
0.4
0.2
1
0
Temperature [°C]
5.5 V 3.3 V 5 V 3 V
) vs. temperature, C
SRC
12
11
10
= 0.56 µF
SRC
AM04876v1
[s]
SRC
t
-60 -40 -20 0 20 40 60 80 100 120 140
9
8
7
6
Temperature [°C]
5.75 V 5.5 V 3.3 V
AM04877v1
Doc ID 16788 Rev 2 11/26
Page 12
Typical operating characteristics STM6510
Figure 9. Reset timeout period (t
200
190
180
170
160
[ms]
REC
t
-60 -40 -20 0 20 40 60 80 100 120 140
150
140
130
120
110
100
) vs. temperature, C
REC
Temperature [°C]
5.75 V 5.5 V 3.3 V
tREC
= 0.01 µF
AM04878v1
Figure 10. Reset threshold (V
[V]
RST
V
-60 -40 -20 0 20 40 60 80 100 120 140
) vs. temperature, “S” threshold option, VCC falling
RST
2.99
2.97
2.95
2.93
2.91
2.89
2.87
2.85
Temperature [°C]
AM04879v1
12/26 Doc ID 16788 Rev 2
Page 13
STM6510 Maximum ratings
3 Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
T
T
SLD
θ
V
V
STG
JA
IO
CC
Storage temperature (VCC off) –55 to +150 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Thermal resistance (junction to ambient) TDFN8 149.0 °C/W
Input or output voltage –0.3 to V
CC
Supply voltage –0.3 to 7 V
+0.3 V
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Doc ID 16788 Rev 2 13/26
Page 14
DC and AC parameters STM6510
4 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the Table 6: DC and AC characteristics that
follow, are derived from tests performed under the Measurement Conditions summarized in
T ab le 5: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 5. Operating and measurement conditions
Parameter Value Unit
V
supply voltage 1.0 to 5.5 V
CC
Ambient operating temperature (T
Input rise and fall times ≤
Input pulse voltages 0.2 to 0.8 V
Input and output timing ref. voltages 0.3 to 0.7 V
Figure 11. AC testing input/output waveforms
) –40 to +85 °C
A
5ns
CC
CC
V
V
0.8 V
0.2 V
CC
CC
0.7 V
0.3 V
CC
CC
AM00478
14/26 Doc ID 16788 Rev 2
Page 15
STM6510 DC and AC parameters
Table 6. DC and AC characteristics
Symbol Parameter Test conditions
V
V
Supply voltage range Reset output valid - active-low 1.0 5.5 V
CC
V
= 5.0 V 1.5 2.4 µA
I
Supply current (VCC)
CC
Reset output voltage low
OL
CC
V
V
V
V
= 3.0 V
CC
≥
CC
≥
CC
≥
CC
(3)
4.5 V, sinking 3.2 mA 0.3 V
3.3 V, sinking 2.5 mA 0.3 V
1.0 V, sinking 0.1 mA 0.3 V
–40 to +85 °C
V
VCC undervoltage reset
RST
threshold (refer to Table 7)
25 °C
L, M 0.5%
V
t
REC
Hysteresis of V
HYST
V
to reset delay
CC
User-adjustable reset timeout
(4)
period on RST. Refer to
RST
(4)
T, S, R, Z, Y, W, V 1%
VCC falling from (V
to (V
- 100 mV) at 10 mV/µs
RST
RST
Table 3.
(1)
+ 100 mV)
Min. Typ.
V
RST
–2.5%
V
RST
–2.0%
10 000 x
C
tREC
(µF)
(2)
Max. Units
1.4 µA
V
V
RST
V
RST
RST
+2.5%
V
RST
+2.0%
20 µs
15 000 x
C
(µF)
tREC
20 000 x
C
(µF)
tREC
V
V
ms
Smart Reset™ inputs
User-adjustable delayed Smart
(5)
t
SRC
Reset™ setup time. Refer to
Table 2.
V
SR0, SR1 input voltage low 0.3 V
IL
SR0, SR1 input voltage high 0.7 V
V
IH
R
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted).
2. Typical value is at 25 °C and V
3. For devices with V
4. Guaranteed by design.
5. Input glitch immunity is equal to t
Internal pull-up resistor, SR0,
PUI
SR1
inputs
RST
< 3.0 V.
= 3.3 V unless otherwise noted.
CC
(when both SR inputs are low, otherwise infinite).
SRC
10 x
C
SRC
(µF)
CC
15 x
C
SRC
(µF)
65 kΩ
20 x
C
SRC
s
(µF)
V
CC
V
Doc ID 16788 Rev 2 15/26
Page 16
DC and AC parameters STM6510
Table 7. Possible VCC voltage thresholds
VCC voltage
threshold V
RST
Typ .
±2.5% (–40 °C to +85 °C) ±2.0% (25 °C)
Unit
Min. Max. Min. Max.
L (falling) 4.625 4.509 4.741 4.533 4.718 V
M (falling) 4.375 4.266 4.484 4.288 4.463 V
T (falling) 3.075 2.998 3.152 3.014 3.137 V
S (falling) 2.925 2.852 2.998 2.867 2.984 V
R (falling) 2.625 2.559 2.691 2.573 2.678 V
Z (falling) 2.313 2.255 2.371 2.267 2.359 V
Y (falling) 2.188 2.133 2.243 2.144 2.232 V
W (falling) 1.665 1.623 1.707 1.632 1.698 V
V (falling) 1.575 1.536 1.614 1.544 1.607 V
16/26 Doc ID 16788 Rev 2
Page 17
STM6510 Package mechanical data
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Doc ID 16788 Rev 2 17/26
Page 18
Package mechanical data STM6510
Figure 12. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
PIN 1 INDEX AREA
0.10 C
0.10
C
A
0.08 C
PIN 1 INDEX AREA
Pin#1 I D
D
2x
0.10 C
2x
TOP VIEW
SIDE VIEW
e
1
A
B
E
C
A1
SEAT ING
PLANE
b
4
0.10 C A B
L
8
BOTTOM VIEW
5
8070540_A
Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm) Dimension (inches)
Symbol
Min. Nom. Max. Min. Nom. Max.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.15 0.20 0.25 0.006 0.008 0.010
D
BSC
E
BSC
e 0.50 0.020
L 0.45 0.55 0.65 0.018 0.022 0.026
2.00 0.079
2.00 0.079
18/26 Doc ID 16788 Rev 2
Page 19
STM6510 Package mechanical data
Figure 13. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E1E
L
b
Table 9. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Parameter Description
Min. Nom. Max.
L Contact length 1.05
b Contact width 0.25
E Max. land pattern Y-direction
E1 Contact gap spacing
D Max. land pattern X-direction
P Contact pitch
—
—
—
—
—
—
2.75
0.65
1.75
0.5
AM00441
1.15
0.30
—
—
—
—
Doc ID 16788 Rev 2 19/26
Page 20
Package mechanical data STM6510
Figure 14. Carrier tape
P
0
D
T
Top cover
tape
K
0
Center lines
of cavity
Table 10. Carrier tape dimensions
Package W D E P
TDFN8
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
1.75
±0.10
0
4.00
±0.10
P
2
User direction of feed
P
2.00
±0.10
FA0B
2
3.50
±0.05
±0.05
2.30
E
A
0
B
0
P
1
K
0
2.30
±0.05
1.00
±0.05
F
W
AM03073v2
P
0
4.00
±0.10
1
TUnit
0.250
±0.05
Bulk
qty.
mm 3000
20/26 Doc ID 16788 Rev 2
Page 21
STM6510 Package mechanical data
Figure 15. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
A
Full radius
C
N
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
AM00443
Table 11. Reel dimensions
Tape sizes A max. B min. C D min. N min. G T max.
8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.40
Doc ID 16788 Rev 2 21/26
Page 22
Package mechanical data STM6510
Figure 16. Tape trailer/leader
End
To p
cover
tape
No components No componentsComponents
TRAILER
160 mm min.
Figure 17. Pin 1 orientation
Sealed with cover tape
User direction of feed
10 0 mm mi n.
LEADE
400 mm min.
Start
R
AM00444
User direction of feed
Note: 1 Drawings are not to scale.
2 All dimensions are in mm, unless otherwise noted.
22/26 Doc ID 16788 Rev 2
AM00442
Page 23
STM6510 Part numbering
6 Part numbering
Table 12. Ordering information scheme
Example: STM6510 W C A C DG 6 F
Device type
STM6510
Reset (V
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset™ setup delay control (t
Smart Reset™ inputs (SR0
C = 1 to 15 s, user-programmable (external capacitor); 65 kΩ input pull-up
Output type
A = open-drain, active-low
Reset timeout period (t
C = user-programmable (external capacitor)
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
monitoring threshold) voltage V
CC
SRC
REC
, SR1)
)
RST
); presence of internal input pull-up on all
6 = –40 °C to +85 °C
Shipping method
®
F = ECOPACK
package, tape and reel
For device options currently available refer to Table 13. For other options, voltage threshold values etc. or
for more information on any aspect of this device, please contact the ST sales office nearest you.
Doc ID 16788 Rev 2 23/26
Page 24
Package marking STM6510
7 Package marking
Table 13. Package marking
t
Part name
SRC
delay
control
Smart
Reset™
inputs type
V
RST
Reset
output type
t
REC
programming
Top mark
STM6510WCACDG6F C
STM6510SCACDG6F C
STM6510RCACDG6F C
SRC
SRC
SRC
AL, PU W AL, OD C
AL, PU S AL, OD C
AL, PU R AL, OD C
tREC
tREC
tREC
8WK
8SK
8RK
Note: AL = Active-Low, AH = Active-High; PU = with internal pull-up resistor, OD = Open-Drain.
Figure 18. Package marking, top view
A
BC
E
D
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
24/26 Doc ID 16788 Rev 2
AM00479
Page 25
STM6510 Revision history
8 Revision history
Table 14. Document revision history
Date Revision Changes
12-Feb-2010 1 Initial release.
Updated title of datasheet, Features, Applications; updated footnote 1
26-Feb-2010 2
of Table 2; updated Table 6, 12, 13; Figure 3; Section 1.3.3; minor
textual and formatting changes.
Doc ID 16788 Rev 2 25/26
Page 26
STM6510
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26/26 Doc ID 16788 Rev 2
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