Datasheet STM32G031C4, STM32G031K4, STM32G031F4, STM32G031G4, STM32G031J4 Datasheet (STMicroelectronics)

STM32G031x4/x6/x8

Errata sheet

STM32G031x4/x6/x8 device errata

Applicability

This document applies to the part numbers of STM32G031x4/x6/x8 devices and the device variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0444.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term “errata” applies both to limitations and documentation errata.

Table 1. Device summary

Reference Part numbers

STM32G031x4 STM32G031C4, STM32G031K4, STM32G031F4, STM32G031G4, STM32G031J4

STM32G031x6 STM32G031C6, STM32G031K6, STM32G031F6, STM32G031G6, STM32G031J6

STM32G031x8 STM32G031C8, STM32G031K8, STM32G031F8, STM32G031G8, STM32G031Y8

Table 2. Device variants

Reference

STM32G031xx

1. Refer to the device datasheet for how to identify this code on different types of package.

2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.

Device marking

Z 0x1001

Silicon revision codes

(1)

REV_ID

(2)

ES0487 - Rev 3 - February 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

1 Summary of device errata

The following table gives a quick reference to the STM32G031x4/x6/x8 device limitations and their status:

A = workaround available

N = no workaround available

P = partial workaround available

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.

Table 3. Summary of device limitations

STM32G031x4/x6/x8

Summary of device errata

Function

System

DMA 2.2.1

DMAMUX

ADC

TIM

LPTIM

RTC and TAMP 2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry A

Section Limitation

2.1.1 Unstable LSI when it clocks RTC or CSS on LSE

2.1.2 WUFx wakeup flag wrongly set during configuration A

2.1.3

2.1.4 DMAMUX cannot be synchronized or triggered by EXTI N

2.1.5

2.1.6 Wakeup from Stop not effective under certain conditions N

2.1.7 Flash memory PCROP area weakness N

2.1.8 PC13 signal transitions disturb LSE N

2.3.1 SOFx not asserted when writing into DMAMUX_CFR register N

2.3.2 OFx not asserted for trigger event coinciding with last DMAMUX request N

2.3.3 OFx not asserted when writing into DMAMUX_RGCFR register N

2.3.4

2.4.1 Overrun flag is not set if EOC reset coincides with new conversion end P

2.4.2 Writing ADC_CFGR1 register while ADEN bit is set resets RES[1:0] bitfield A

2.4.3 Out-of-threshold value is not detected in AWD1 Single mode A

2.4.4 ADC sampling time might be one cycle longer N

2.5.1

2.5.2 Consecutive compare event missed in specific conditions N

2.5.3 Output compare clear not working with external counter reset P

2.5.4 TIM1 synchronization trigger might be missed N

2.5.5 TIM16 and TIM17 are unduly clocked by SYSCLK N

2.6.1 Device may remain stuck in LPTIM interrupt when entering Stop mode A

2.6.2 Device may remain stuck in LPTIM interrupt when clearing event flag P

Under Level 1 read protection, booting from Main Flash memory selected
through PA14‑BOOT0 pin is not functional

Overwriting with all zeros a Flash memory location previously programmed with
all ones fails

DMA disable failure and error flag omission upon simultaneous transfer error
and global flag clear

Wrong input DMA request routed upon specific DMAMUX_CxCR register write
coinciding with synchronization event

One-pulse mode trigger not detected in master-slave reset + trigger
configuration

Status

Rev. Z

P

N

N

A

A

P

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STM32G031x4/x6/x8

Summary of device errata

Function Section Limitation

2.8.1

I2C

USART 2.9.1 Data corruption due to noisy receive line N

SPI

2.8.2 Spurious bus error detection in master mode A

2.8.3 Spurious master transfer upon own slave address match P

2.10.1 BSY bit may stay high when SPI is disabled A

2.10.2 BSY bit may stay high at the end of data transfer in slave mode A

Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C
kernel clock period

The following table gives a quick reference to the documentation errata.

Table 4. Summary of device documentation errata

Function Section Documentation erratum

ADC 2.4.5 ADC trigger latency parameter

USART 2.9.2 USART prescaler feature missing in USART implementation section

Status

Rev. Z

P

ES0487 - Rev 3

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STM32G031x4/x6/x8

Description of device errata

2 Description of device errata

The following sections describe limitations of the applicable devices with Arm® core and provide workarounds if
available. They are grouped by device functions.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

2.1 System

2.1.1 Unstable LSI when it clocks RTC or CSS on LSE

Description

The LSI clock can become unstable (duty cycle different from 50 %) and its maximum frequency can become
significantly higher than 32 kHz, when:

• LSI clocks the RTC, or it clocks the clock security system (CSS) on LSE (which holds when the LSECSSON
bit set), and

• the VDD power domain is reset while the backup domain is not reset, which happens:

– upon exiting Shutdown mode

– if V

– if V

is separate from VDD and VDD goes off then on

BAT

is tied to VDD (internally in the package for products not featuring the VBAT pin, or externally)

BAT

and a short (< 1 ms) VDD drop under VDD(min) occurs

Workaround

Apply one of the following measures:

• Clock the RTC with LSE or HSE/32, without using the CSS on LSE

• If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each VDD power up
(when the BORRSTF flag is set). If V
registers and anti-tampering configuration.

is separate from VDD, also restore the RTC configuration, backup

BAT

2.1.2 WUFx wakeup flag wrongly set during configuration

Description

Upon configuring a wakeup pin (WKUPx), the corresponding wakeup flag (WUFx) might spuriously go high
depending on the state and configuration of the wakeup pin.

Workaround

After configuring a wakeup pin, clear its corresponding WUFx flag.

2.1.3 Under Level 1 read protection, booting from Main Flash memory selected through PA14‑BOOT0

pin is not functional

Description

With the Flash memory read protection set to Level 1 and the boot mode selected through the PA14-BOOT0 pin
(BOOT0 function of the pin), an attempt to boot from Main Flash memory can wrongly be interpreted by the read
protection mechanism as an unauthorized access, preventing the user code execution. Booting from Main Flash
memory operates correctly if selected through option bits (nBOOT_SEL and nBOOT0 both set).

ES0487 - Rev 3

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STM32G031x4/x6/x8

System

Workaround

None.

2.1.4 DMAMUX cannot be synchronized or triggered by EXTI

Description

The EXTI-related DMAMUX synchronization and trigger inputs are wrongly routed to the it_exti_per(y) output
instead of being routed to the exti[15:0] output lines.

The it_exti_per(y) signals are not usable for synchronizing and triggering DMAMUX.

Workaround

None.

2.1.5 Overwriting with all zeros a Flash memory location previously programmed with all ones fails

Description

Any attempt to re-program with all zeros (0x0000 0000 0000 0000) a Flash memory location previously
programmed with 0xFFFF FFFF FFFF FFFF fails and the PROGERR flag of the FLASH_SR register is set.

Workaround

None.

2.1.6 Wakeup from Stop not effective under certain conditions

Description

With the HSI clock divider bitfield HSIDIV[2:0] set to a value different from 000, the device fails to enter Stop mode
when SYSCLK is set to HSE clock.

With the HSI clock divider bitfield HSIDIV[2:0] set to a value different from 000, peripherals with clock request
capability fail to wake the device up from Stop modes.

Workaround

None.

2.1.7 Flash memory PCROP area weakness

Description

When the CPU accesses PCROP-protected Flash memory areas:

• Fetch requests are allowed and are responded to normally.

• Read access are properly discarded. However, the bus holds and returns the value read during previous

successful access.

Workaround

None.

Note: We recommend to use the PCROP protection in the following RDP and PCROP_RDP configurations:

• RDP = Level 1 and PCROP_RDP = 1

• RDP = Level 2

ES0487 - Rev 3

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2.1.8 PC13 signal transitions disturb LSE

Description

The PC13 port toggling disturbs the LSE clock.

Workaround

None.

STM32G031x4/x6/x8

DMA

2.2

DMA

2.2.1 DMA disable failure and error flag omission upon simultaneous transfer error and global flag

clear

Description

Upon a data transfer error in a DMA channel x, both the specific TEIFx and the global GIFx flags are raised and
the channel x is normally automatically disabled. However, if in the same clock cycle the software clears the GIFx
flag (by setting the CGIFx bit of the DMA_IFCR register), the automatic channel disable fails and the TEIFx flag is
not raised.

This issue does not occur with ST's HAL software that does not use and clear the GIFx flag when the channel is
active.

Workaround

Do not clear GIFx flags when the channel is active. Instead, use HTIFx, TCIFx, and TEIFx specific event flags and
their corresponding clear bits.

2.3 DMAMUX

2.3.1 SOFx not asserted when writing into DMAMUX_CFR register

Description

The SOFx flag of the DMAMUX_CSR status register is not asserted if overrun from another DMAMUX channel
occurs when the software writes into the DMAMUX_CFR register.

This can happen when multiple DMA channels operate in synchronization mode, and when overrun can occur
from more than one channel. As the SOFx flag clear requires a write into the DMAMUX_CFR register (to set
the corresponding CSOFx bit), overrun occurring from another DMAMUX channel operating during that write
operation fails to raise its corresponding SOFx flag.

Workaround

None. Avoid the use of synchronization mode for concurrent DMAMUX channels, if at least two of them potentially
generate synchronization overrun.

2.3.2 OFx not asserted for trigger event coinciding with last DMAMUX request

Description

In the DMAMUX request generator, a trigger event detected in a critical instant of the last-generated DMAMUX
request being served by the DMA controller does not assert the corresponding trigger overrun flag OFx. The
critical instant is the clock cycle at the very end of the trigger overrun condition.

Additionally, upon the following trigger event, one single DMA request is issued by the DMAMUX request
generator, regardless of the programmed number of DMA requests to generate.

The failure only occurs if the number of requests to generate is set to more than two (GNBREQ[4:0] > 00001).

ES0487 - Rev 3

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Workaround

Make the trigger period longer than the duration required for serving the programmed number of DMA requests,
so as to avoid the trigger overrun condition from occurring on the very last DMA data transfer.

2.3.3 OFx not asserted when writing into DMAMUX_RGCFR register

Description

The OFx flag of the DMAMUX_RGSR status register is not asserted if an overrun from another DMAMUX request
generator channel occurs when the software writes into the DMAMUX_RGCFR register. This can happen when
multiple DMA channels operate with the DMAMUX request generator, and when an overrun can occur from more
than one request generator channel. As the OFx flag clear requires a write into the DMAMUX_RGCFR register
(to set the corresponding COFx bit), an overrun occurring in another DMAMUX channel operating with another
request generator channel during that write operation fails to raise the corresponding OFx flag.

Workaround

None. Avoid the use of request generator mode for concurrent DMAMUX channels, if at least two channels are
potentially generating a request generator overrun.

STM32G031x4/x6/x8

ADC

2.3.4 Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with

synchronization event

Description

If a write access into the DMAMUX_CxCR register having the SE bit at zero and SPOL[1:0] bitfield at a value
other than 00:

• sets the SE bit (enables synchronization),

• modifies the values of the DMAREQ_ID[5:0] and SYNC_ID[4:0] bitfields, and

• does not modify the SPOL[1:0] bitfield,

and if a synchronization event occurs on the previously selected synchronization input exactly two AHB clock
cycles before this DMAMUX_CxCR write, then the input DMA request selected by the DMAREQ_ID[5:0] value
before that write is routed.

Workaround

Ensure that the SPOL[1:0] bitfield is at 00 whenever the SE bit is 0. When enabling synchronization by setting
the SE bit, always set the SPOL[1:0] bitfield to a value other than 00 with the same write operation into the
DMAMUX_CxCR register.

2.4 ADC

2.4.1 Overrun flag is not set if EOC reset coincides with new conversion end

Description

ES0487 - Rev 3

If the EOC flag is cleared by an ADC_DR register read operation or by software during the same APB cycle in
which the data from a new conversion are written in the ADC_DR register, the overrun event duly occurs (which
results in the loss of either current or new data) but the overrun flag (OVR) may stay low.

Workaround

Clear the EOC flag, by performing an ADC_DR read operation or by software within less than one ADC
conversion cycle period from the last conversion cycle end, in order to avoid the coincidence with the end of
the new conversion cycle.

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STM32G031x4/x6/x8

2.4.2 Writing ADC_CFGR1 register while ADEN bit is set resets RES[1:0] bitfield

Description

Modifying the ADC_CFGR1 register while ADC is enabled (ADEN set in ADC_CR) and no conversion is ongoing
(ADSTART cleared in ADC_CR) resets RES[1:0] to 00 whatever the bitfield previous value.

Workaround

Apply the following sequence:

1. Set ADDIS to disable the ADC, and wait until ADEN is cleared.

2. Program the ADC_CFGR1 register according to the application requirements.

3. Set ADEN bit.

2.4.3 Out-of-threshold value is not detected in AWD1 Single mode

Description

AWD1 analog watchdog does not detect that the result of a converted channel has reached the programmed
threshold when the ADC operates in Single mode, performs a sequence of conversions, and one of the converted
channels other than the first one is monitored by the AWD1 analog watchdog.

ADC

Workaround

Apply one of the following measures:

• Use a conversion sequence of one single channel.

• Configure the monitored channel as the first one of the sequence.

2.4.4 ADC sampling time might be one cycle longer

Description

For sampling time set to 1.5 or 3.5 cycles, the sampling in a single ADC conversion or in the first conversion of a
sequence takes one extra cycle.

Workaround

None.

2.4.5 ADC trigger latency parameter

Description

Some datasheet revisions state incorrectly ADC trigger latency values for CKMODE set to 01, 10, and 11, as

2.75, 2.63, and 3 ADC clock cycles at maximum, respectively.

The correct specification is 6.5, 12.5, and 3.5 PCLK cycles typical, respectively.

This is a documentation issue rather than a product limitation.

ES0487 - Rev 3

Workaround

No application workaround is applicable.

.

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STM32G031x4/x6/x8

2.5 TIM

2.5.1 One-pulse mode trigger not detected in master-slave reset + trigger configuration

Description

The failure occurs when several timers configured in one-pulse mode are cascaded, and the master timer is
configured in combined reset + trigger mode with the MSM bit set:

OPM = 1 in TIMx_CR1, SMS[3:0] = 1000 and MSM = 1 in TIMx_SMCR.

The MSM delays the reaction of the master timer to the trigger event, so as to have the slave timers cycle­accurately synchronized.

If the trigger arrives when the counter value is equal to the period value set in the TIMx_ARR register, the
one-pulse mode of the master timer does not work and no pulse is generated on the output.

Workaround

None. However, unless a cycle-level synchronization is mandatory, it is advised to keep the MSM bit reset, in
which case the problem is not present. The MSM = 0 configuration also allows decreasing the timer latency to
external trigger events.

2.5.2 Consecutive compare event missed in specific conditions

TIM

Description

Every match of the counter (CNT) value with the compare register (CCR) value is expected to trigger a compare
event. However, if such matches occur in two consecutive counter clock cycles (as consequence of the CCR
value change between the two cycles), the second compare event is missed for the following CCR value
changes:

in edge-aligned mode, from ARR to 0:

•

– first compare event: CNT = CCR = ARR

– second (missed) compare event: CNT = CCR = 0

•

in center-aligned mode while up-counting, from ARR-1 to ARR (possibly a new ARR value if the period is
also changed) at the crest (that is, when TIMx_RCR = 0):

– first compare event: CNT = CCR = (ARR-1)

– second (missed) compare event: CNT = CCR = ARR

•

in center-aligned mode while down-counting, from 1 to 0 at the valley (that is, when TIMx_RCR = 0):

– first compare event: CNT = CCR = 1

– second (missed) compare event: CNT = CCR = 0

This typically corresponds to an abrupt change of compare value aiming at creating a timer clock single-cycle­wide pulse in toggle mode.

As a consequence:

• In toggle mode, the output only toggles once per counter period (squared waveform), whereas it is expected

to toggle twice within two consecutive counter cycles (and so exhibit a short pulse per counter period).

• In center mode, the compare interrupt flag does note rise and the interrupt is not generated.

Note: The timer output operates as expected in modes other than the toggle mode.

Workaround

None.

2.5.3 Output compare clear not working with external counter reset

Description

The output compare clear event (ocref_clr) is not correctly generated when the timer is configured in the following
slave modes: Reset mode, Combined reset + trigger mode, and Combined gated + reset mode.

ES0487 - Rev 3

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The PWM output remains inactive during one extra PWM cycle if the following sequence occurs:

1. The output is cleared by the ocref_clr event.

2. The timer reset occurs before the programmed compare event.

Workaround

Apply one of the following measures:

• Use BKIN (or BKIN2 if available) input for clearing the output, selecting the Automatic output enable mode

(AOE = 1).

• Mask the timer reset during the PWM ON time to prevent it from occurring before the compare event (for

example with a spare timer compare channel open-drain output connected with the reset signal, pulling the
timer reset line down).

2.5.4 TIM1 synchronization trigger might be missed

Description

A slave timer may miss synchronization trigger signal generated by if the master timer clock is faster than the
slave timer clock.

Workaround

STM32G031x4/x6/x8

LPTIM

None.

2.5.5 TIM16 and TIM17 are unduly clocked by SYSCLK

Description

The timers TIM16 and TIM17 are unduly clocked by SYSCLK instead of being clocked by the timer clock
TIMPCLK. As a consequence, they do not reflect AHB and APB prescaler settings.

The TIM16 and TIM17 are fully functional as long as the SYSCLK-to-PCLK frequency ratio remains smaller than
or equal to four.

Workaround

None.

2.6 LPTIM

2.6.1 Device may remain stuck in LPTIM interrupt when entering Stop mode

Description

This limitation occurs when disabling the low-power timer (LPTIM).

When the user application clears the ENABLE bit in the LPTIM_CR register within a small time window around
one LPTIM interrupt occurrence, then the LPTIM interrupt signal used to wake up the device from Stop mode may
be frozen in active state. Consequently, when trying to enter Stop mode, this limitation prevents the device from
entering low-power mode and the firmware remains stuck in the LPTIM interrupt routine.

This limitation applies to all Stop modes and to all instances of the LPTIM. Note that the occurrence of this issue
is very low.

ES0487 - Rev 3

Workaround

In order to disable a low power timer (LPTIMx) peripheral, do not clear its ENABLE bit in its respective LPTIM_CR
register. Instead, reset the whole LPTIMx peripheral via the RCC controller by setting and resetting its respective
LPTIMxRST bit in RCC_APByRSTRz register.

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STM32G031x4/x6/x8

RTC and TAMP

2.6.2 Device may remain stuck in LPTIM interrupt when clearing event flag

Description

This limitation occurs when the LPTIM is configured in interrupt mode (at least one interrupt is enabled) and
the software clears any flag in LPTIM_ISR register by writing its corresponding bit in LPTIM_ICR register. If the
interrupt status flag corresponding to a disabled interrupt is cleared simultaneously with a new event detection,
the set and clear commands might reach the APB domain at the same time, leading to an asynchronous interrupt
signal permanently stuck high.

This issue can occur either during an interrupt subroutine execution (where the flag clearing is usually done), or
outside an interrupt subroutine.

Consequently, the firmware remains stuck in the LPTIM interrupt routine, and the device cannot enter Stop mode.

Workaround

To avoid this issue, it is strongly advised to follow the recommendations listed below:

• Clear the flag only when its corresponding interrupt is enabled in the interrupt enable register.

• If for specific reasons, it is required to clear some flags that have corresponding interrupt lines disabled in

the interrupt enable register, it is recommended to clear them during the current subroutine prior to those
which have corresponding interrupt line enabled in the interrupt enable register.

• Flags must not be cleared outside the interrupt subroutine.

Note: The proper clear sequence is already implemented in the HAL_LPTIM_IRQHandler in the STM32Cube.

2.7 RTC and TAMP

2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry

Description

If the INIT bit of the RTC_ICSR register is set between one and two RTCCLK cycles after being cleared, the
INITF flag is set immediately instead of waiting for synchronization delay (which should be between one and two
RTCCLK cycles), and the initialization of registers may fail. Depending on the INIT bit clearing and setting instants
versus the RTCCLK edges, it can happen that, after being immediately set, the INITF flag is cleared during one
RTCCLK period then set again. As writes to calendar registers are ignored when INITF is low, a write occurring
during this critical period might result in the corruption of one or more calendar registers.

Workaround

After existing the initialization mode, clear the BYPSHAD bit (if set) then wait for RSF to rise, before entering the
initialization mode again.

Note: It is recommended to write all registers in a single initialization session to avoid accumulating synchronization

delays.

2.8 I2C

2.8.1 Wrong data sampling when data setup time (t

Description

) is shorter than one I2C kernel clock period

SU;DAT

ES0487 - Rev 3

The I2C-bus specification and user manual specify a minimum data setup time (t

• 250 ns in Standard mode

• 100 ns in Fast mode

• 50 ns in Fast mode Plus

SU;DAT

) as:

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STM32G031x4/x6/x8

I2C

The device does not correctly sample the I2C-bus SDA line when t

(I2C-bus peripheral clock) period: the previous SDA value is sampled instead of the current one. This can result in
a wrong receipt of slave address, data byte, or acknowledge bit.

Workaround

Increase the I2C kernel clock frequency to get I2C kernel clock period within the transmitter minimum data setup
time. Alternatively, increase transmitter’s minimum data setup time. If the transmitter setup time minimum value

corresponds to the minimum value provided in the I2C-bus standard, the minimum I2CCLK frequencies are as
follows:

• In Standard mode, if the transmitter minimum setup time is 250 ns, the I2CCLK frequency must be at least

4 MHz.

• In Fast mode, if the transmitter minimum setup time is 100 ns, the I2CCLK frequency must be at least

10 MHz.

• In Fast-mode Plus, if the transmitter minimum setup time is 50 ns, the I2CCLK frequency must be at least

20 MHz.

2.8.2 Spurious bus error detection in master mode

Description

In master mode, a bus error can be detected spuriously, with the consequence of setting the BERR flag of the
I2C_SR register and generating bus error interrupt if such interrupt is enabled. Detection of bus error has no effect

on the I2C-bus transfer in master mode and any such transfer continues normally.

Workaround

is smaller than one I2C kernel clock

SU;DAT

If a bus error interrupt is generated in master mode, the BERR flag must be cleared by software. No other action
is required and the ongoing transfer can be handled normally.

2.8.3 Spurious master transfer upon own slave address match

Description

When the device is configured to operate at the same time as master and slave (in a multi- master I2C-bus
application), a spurious master transfer may occur under the following condition:

• Another master on the bus is in process of sending the slave address of the device (the bus is busy).

• The device initiates a master transfer by bit set before the slave address match event (the ADDR flag set in

the I2C_ISR register) occurs.

• After the ADDR flag is set:

– the device does not write I2C_CR2 before clearing the ADDR flag, or

– the device writes I2C_CR2 earlier than three I2C kernel clock cycles before clearing the ADDR flag

In these circumstances, even though the START bit is automatically cleared by the circuitry handling the ADDR
flag, the device spuriously proceeds to the master transfer as soon as the bus becomes free. The transfer
configuration depends on the content of the I2C_CR2 register when the master transfer starts. Moreover, if the
I2C_CR2 is written less than three kernel clocks before the ADDR flag is cleared, the I2C peripheral may fall into
an unpredictable state.

Workaround

Upon the address match event (ADDR flag set), apply the following sequence.

Normal mode (SBC = 0):

1. Set the ADDRCF bit.

2. Before Stop condition occurs on the bus, write I2C_CR2 with the START bit low.

ES0487 - Rev 3

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Slave byte control mode (SBC = 1):

1. Write I2C_CR2 with the slave transfer configuration and the START bit low.

2. Wait for longer than three I2C kernel clock cycles.

3. Set the ADDRCF bit.

4. Before Stop condition occurs on the bus, write I2C_CR2 again with its current value.

The time for the software application to write the I2C_CR2 register before the Stop condition is limited, as the
clock stretching (if enabled), is aborted when clearing the ADDR flag.

Polling the BUSY flag before requesting the master transfer is not a reliable workaround as the bus may become
busy between the BUSY flag check and the write into the I2C_CR2 register with the START bit set.

2.9 USART

2.9.1 Data corruption due to noisy receive line

Description

In UART mode with oversampling by 8 or 16 and with 1 or 2 stop bits, the received data may be corrupted if a
glitch to zero shorter than the half-bit occurs on the receive line within the second half of the stop bit.

Workaround

STM32G031x4/x6/x8

USART

None.

2.9.2 USART prescaler feature missing in USART implementation section

Description

Some reference manual revisions may omit the information that the USART prescaler is not present in all USART
instances. This information is provided in the USART implementation section of the corresponding reference
manual.

This is a documentation issue rather than a product limitation.

Workaround

No application workaround is required or applicable.

2.10 SPI

2.10.1 BSY bit may stay high when SPI is disabled

Description

The BSY flag may remain high upon disabling the SPI while operating in:

• master transmit mode and the TXE flag is low (data register full).

• master receive-only mode (simplex receive or half-duplex bidirectional receive phase) and an SCK strobing

edge has not occurred since the transition of the RXNE flag from low to high.

• slave mode and NSS signal is removed during the communication.

ES0487 - Rev 3

Workaround

When the SPI operates in:

• master transmit mode, disable the SPI when TXE = 1 and BSY = 0.

• master receive-only mode, ignore the BSY flag.

• slave mode, do not remove the NSS signal during the communication.

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STM32G031x4/x6/x8

2.10.2 BSY bit may stay high at the end of data transfer in slave mode

Description

BSY flag may sporadically remain high at the end of a data transfer in slave mode. This occurs upon coincidence
of internal CPU clock and external SCK clock provided by master.

In such an event, if the software only relies on BSY flag to detect the end of SPI slave data transaction (for
example to enter low-power mode or to change data line direction in half-duplex bidirectional mode), the detection
fails.

As a conclusion, the BSY flag is unreliable for detecting the end of data transactions.

Workaround

Depending on SPI operating mode, use the following means for detecting the end of transaction:

• When NSS hardware management is applied and NSS signal is provided by master, use NSS flag.

• In SPI receiving mode, use the corresponding RXNE event flag.

• In SPI transmit-only mode, use the BSY flag in conjunction with a timeout expiry event. Set the timeout such

as to exceed the expected duration of the last data frame and start it upon TXE event that occurs with the
second bit of the last data frame. The end of the transaction corresponds to either the BSY flag becoming
low or the timeout expiry, whichever happens first.

Prefer one of the first two measures to the third as they are simpler and less constraining.

Alternatively, apply the following sequence to ensure reliable operation of the BSY flag in SPI transmit mode:

1. Write last data to data register.

2. Poll the TXE flag until it becomes high, which occurs with the second bit of the data frame transfer.

3. Disable SPI by clearing the SPE bit mandatorily before the end of the frame transfer.

4. Poll the BSY bit until it becomes low, which signals the end of transfer.

Note: The alternative method can only be used with relatively fast CPU speeds versus relatively slow SPI clocks

or/and long last data frames. The faster is the software execution, the shorter can be the duration of the last data
frame.

SPI

ES0487 - Rev 3

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Revision history

Table 5. Document revision history

Date Version Changes

21-Jun-2019 1 Initial release.

Added:

• Section 2.1.4 DMAMUX cannot be synchronized or triggered by EXTI

• Section 2.4.1 Overrun flag is not set if EOC reset coincides with new

conversion end

• Section 2.4.2 Writing ADC_CFGR1 register while ADEN bit is set

resets RES[1:0] bitfield

• Section 2.4.3 Out-of-threshold value is not detected in AWD1 Single

mode

• Section 2.5.4 TIM1 synchronization trigger might be missed

16-Jan-2020 2

3-Fev-2021

3

• Section 2.5.5 TIM16 and TIM17 are unduly clocked by SYSCLK

• Section 2.6.1 Device may remain stuck in LPTIM interrupt when

entering Stop mode

• Section 2.6.2 Device may remain stuck in LPTIM interrupt when

clearing event flag

• Section 2.9.1 Data corruption due to noisy receive line

• Section 2.9.2 USART prescaler feature missing in USART

implementation section

• Table 4. Summary of device documentation errata

Updated Table 3. Summary of device limitations.

Added Table 3. Summary of device limitations :

• Wakeup from Stop not effective under certain conditions

• Flash memory PCROP area weakness

• PC13 signal transitions disturb LSE

• ADC sampling time might be one cycle longer

• Consecutive compare event missed in specific conditions

• Output compare clear not working with external counter reset

Added in Table 4. Summary of device documentation errata :

• ADC trigger latency parameter

STM32G031x4/x6/x8

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STM32G031x4/x6/x8

Contents

Contents

1 Summary of device errata..........................................................2

2 Description of device errata........................................................4

2.1 System .......................................................................4

2.1.1 Unstable LSI when it clocks RTC or CSS on LSE ................................4

2.1.2 WUFx wakeup flag wrongly set during configuration ..............................4

2.1.3 Under Level 1 read protection, booting from Main Flash memory selected through

PA14‑BOOT0 pin is not functional............................................4

2.1.4 DMAMUX cannot be synchronized or triggered by EXTI ...........................5

2.1.5 Overwriting with all zeros a Flash memory location previously programmed with all ones

fails ...................................................................5

2.1.6 Wakeup from Stop not effective under certain conditions ..........................5

2.1.7 Flash memory PCROP area weakness ........................................5

2.1.8 PC13 signal transitions disturb LSE ..........................................6

2.2 DMA .........................................................................6

2.2.1 DMA disable failure and error flag omission upon simultaneous transfer error and global

flag clear ...............................................................6

2.3 DMAMUX .....................................................................6

2.3.1 SOFx not asserted when writing into DMAMUX_CFR register ......................6

2.3.2 OFx not asserted for trigger event coinciding with last DMAMUX request ..............6

2.3.3 OFx not asserted when writing into DMAMUX_RGCFR register .....................7

2.3.4 Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding

with synchronization event .................................................7

2.4 ADC .........................................................................7

2.4.1 Overrun flag is not set if EOC reset coincides with new conversion end ...............7

2.4.2 Writing ADC_CFGR1 register while ADEN bit is set resets RES[1:0] bitfield............8

2.4.3 Out-of-threshold value is not detected in AWD1 Single mode .......................8

2.4.4 ADC sampling time might be one cycle longer ..................................8

2.4.5 ADC trigger latency parameter ..............................................8

2.5 TIM ..........................................................................9

2.5.1 One-pulse mode trigger not detected in master-slave reset + trigger configuration .......9

2.5.2 Consecutive compare event missed in specific conditions .........................9

2.5.3 Output compare clear not working with external counter reset ......................9

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STM32G031x4/x6/x8

Contents

2.5.4 TIM1 synchronization trigger might be missed .................................10

2.5.5 TIM16 and TIM17 are unduly clocked by SYSCLK ..............................10

2.6 LPTIM .......................................................................10

2.6.1 Device may remain stuck in LPTIM interrupt when entering Stop mode ..............10

2.6.2 Device may remain stuck in LPTIM interrupt when clearing event flag ............... 11

2.7 RTC and TAMP ...............................................................11

2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry ............... 11

2.8 I2C .........................................................................11

2.8.1 Wrong data sampling when data setup time (t

) is shorter than one I2C kernel clock

SU;DAT

period ................................................................ 11

2.8.2 Spurious bus error detection in master mode ..................................12

2.8.3 Spurious master transfer upon own slave address match .........................12

2.9 USART ......................................................................13

2.9.1 Data corruption due to noisy receive line......................................13

2.9.2 USART prescaler feature missing in USART implementation section ................13

2.10 SPI .........................................................................13

2.10.1 BSY bit may stay high when SPI is disabled ...................................13

2.10.2 BSY bit may stay high at the end of data transfer in slave mode....................14

Revision history .......................................................................15

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STM32G031x4/x6/x8

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