Datasheet STK14C88-3W55I, STK14C88-3W55, STK14C88-3W45I, STK14C88-3W45, STK14C88-3N55I Datasheet (SIMTEK)
...Page 1
STK14C88-3
32K x 8 AutoStore™ nvSRAM
3.3V QuantumTrap™ CMOS
Nonvolatile Static RAM
ADVANCE
FEATURES
•“Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to EEPROM Initiated by Software or
AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 45ns and 55ns Access Times
• 8mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• 3.0V-3.6V Operation
• Not Sensitive to Power On/Off Ramp Rates
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
BLOCK DIAGRAM
V
EEPROM ARRAY
512 x 512
A
5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
ROW DECODER
INPUT BUFFERS
STATIC RAM
ARRAY
512 x 512
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A
STORE
RECALL
10
CCXVCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
DESCRIPTION
The Simtek STK14C88-3 is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
PROM element
SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down. A 68µF capacitor
from V
to ground guarantees the STORE opera-
CAP
tion, regardless of power-down slew rate or loss of
power from “hot swapping”. Transfers from the
EEPROM to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initiation of
STORE and RECALL cycles can also be soft-
ware controlled by entering specific read
sequences.
PIN CONFIGUR ATIONS
V
32
CCX
NC
31
30
W
29
A
13
28
A
8
A
27
9
A
26
11
25
G
24
NC
A
23
10
E
22
DQ
21
7
DQ
20
6
19
DQ
5
18
17
Address Inputs
Chip Enable
Write Enable
Output Enable
Power (+ 3.3V)
Capacitor
Ground
32 - 300 SOIC
DQ
4
DQ
3
32 - 600 PDIP
SOFTWARE
DETECT
A0 - A
G
E
W
1
V
CAP
2
A
14
A
3
12
A
4
7
A
5
6
A
6
5
A
7
4
A
8
3
NC
9
A
10
2
A
11
1
A
12
0
DQ
13
0
DQ
14
1
DQ
15
2
V
16
SS
13
PIN NAMES
A0 - A
14
-DQ7Data In/Out
DQ
0
E
W
G
V
CCX
V
CAP
V
SS
July 1999 5-33
Page 2
STK14C88-3
ABSOLUTE MAXIMUM RATINGS
Volt age on Input Rel ative to VSS . . . . . . . . . .– 0.6V to (VCC + 0.5V)
Volt age on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sec tions of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 3.0V-3.6V)
SYMBOL PARAMETER
b
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
Note c: I
Note d: E
Note e: V
Average VCC Current 35
1
c
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
2
b
Average V
3
3.3V, 25°C, T yp ical
c
Average V
4
AutoStore™ Cycle
d
Average V
1
(Standby, Cycling TT L Input Levels)
d
V
2
CC
(Standby, Stable CMOS Input Levels)
Current at t
CC
Current during
CAP
Current
CC
Standby Current
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C
and I
CC
1
and I
CC
2
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
nected to ground.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
AVAV
= 200ns
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
37
30
32
88mA
22mA
9
8
10
9
11mA
±1 ±1 µA
±5 ±5 µA
if that is where the power supply connection is made, or V
CCX
UNITS NOTES
mA
mA
t
= 45ns
AVAV
t
= 55ns
AVAV
W
≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
All Inputs Don’t Care
mA
mA
STORE
t
= 45ns, E ≥ V
AVAV
t
= 55ns, E ≥ V
AVAV
E
≥ (VCC – 0.2V)
All Others V
V
= max
CC
V
= VSS to V
IN
V
= max
CC
V
= VSS to VCC, E or G ≥ VIH
IN
= – 1mA
OUT
= 2mA
OUT
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
).
CAP
if V
CCX
is con-
e
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.0V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
f
CAPACIT ANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
July 1999 5-34
OUTPUT
3.0V
1.55K Ohms
Figure 1: AC Output Loading
1.1K Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Page 3
STK14C88-3
SRAM READ CYCLES #1 & #2 (VCC = 3.0V-3.6V)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
h
h
i
i
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
f
t
PA
f
t
PS
Chip Enable Access Time 45 55 ns
Read Cycle Time 45 55 ns
Address Access Time 45 55 ns
Output Enable to Data Valid 20 25 ns
Output Hold after Address Change 5 3 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output I nactive 15 20 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inac ti ve 15 20 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 45 55 ns
PARAMETER
Note g: W must be high during SRAM READ cycles.
Note h: Device is continuously selected with E
and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg,
2
t
t
AVQV
AVAV
3
ADDRESS
DQ (DATA OUT)
t
AXQX
5
h
DATA VALI D
STK14C88-3-45 STK14C88-3-55
UNITS
e
SRAM READ CYCLE #2: E Controlled
ADDRESS
t
STANDBY
6
t
ELQX
8
t
GLQX
10
ELICCH
t
GLQV
4
DQ (DATA OUT)
I
CC
E
G
g
t
AVAV
t
ELQV
2
1
ACTIVE
DATA VALI D
t
GHQZ
11
t
EHICCL
7
t
EHQZ
9
July 1999 5-35
Page 4
STK14C88-3
SRAM WRITE CYCLES #1 & #2 (VCC = 3.0V-3.6V)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ V
SRAM WRITE CYCLE #1: W Controlled
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX
AVAV
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 45 55 ns
WC
t
Write Pulse Width 30 40 ns
WP
t
Chip Enable to End of Write 30 40 ns
CW
t
Data Set-up to End of Write 15 25 ns
DW
t
Data Hold after End of Write 0 0 ns
DH
t
Address Set-up to End o f Write 30 40 ns
AW
t
Address Set-up to Start of Write 0 0 ns
AS
t
Address Hold after En d of Write 0 0 n s
WR
t
Write Enable to Output D is able 15 20 ns
WZ
t
Output Active after En d of Write 5 5 ns
OW
during address transitions.
IH
PARAMETER
k
12
t
AVAV
ADDRESS
14
t
ELWH
E
STK14C88-3-45 STK14C88-3-55
19
t
WHAX
UNITS
e
17
t
18
t
AVWL
AVWH
W
DATA IN
DATA IN
DA TA OUT
PREVIOUS DATA
20
20
t
t
WLQZ
WLQZ
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
AVEL
E
17
t
AVEH
W
DATA IN
t
k
t
13
t
WLEH
13
WLWH
14
ELEH
t
AVAV
12
15
t
DVWH
DATA VALI D
HIGH IMPEDANCE
15
t
DVEH
DATA VALI D
16
t
WHDX
19
t
EHAX
16
t
EHDX
21
t
WHQX
DA TA OUT
HIGH IMPEDANCE
July 1999 5-36
Page 5
STK14C88-3
AutoStore™/POWER-UP RECALL (VCC = 3.0V-3.6V)
NO.
22 t
23 t
24 V
25 V
Note l: t
Note m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
RESTORE
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
SWITCH
RESET
t
HLHZ
starts from the time VCC rises above V
Power-up RECALL Duration 550 µsl
STORE Cycle Duration 10 ms m
Low Voltage Trigger Level 2.7 3.0 V
Low Voltage Reset Level 2.6 V
SWITCH
PARAMETER
.
STK14C88-3
UNITS NOTES
AutoStore™/POWER-UP RECALL
24
V
SWITCH
25
V
RESET
e
AutoStore™
POWER-UP RECALL
DQ (DATA OUT)
23
t
STORE
22
t
RESTORE
W
POWER-UP
RECALL
BROWN OUT
NO STORE
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
(NO SRAM WRITES)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
RECALL WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
July 1999 5-37
Page 6
STK14C88-3
SOFTWARE STORE/RECALL MODE SELECTION
E W A13 - A0 (hex) MODE I/O POWER NOTES
H X X Not Selected Output High Z Standby
L H X Read SRAM Output Data Active p
L L X Write SRAM Input Data Active
X X X Nonvolatile STORE Output High Z l
LH
LH
0E38
31C7
03E0
3C1F
303F
0FC0
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.
Note p: I/O state assumes G
SOFTWARE-CONTROLLED STORE/RECALL CYCLE
< VIL. Activation of nonvolatile cycles does not depend on state of G.
r
CC
2
Active
l
CC
Active
2
n, o, p
n, o, p
(VCC = 3.0V-3.6V)
e
NO.
26 t
27 t
28 t
29 t
30 t
SYMBOLS
Standard Alternate MIN MAX MIN MAX
AVAV
AVEL
ELEH
ELAX
RECALL
t
RC
t
AS
t
CW
STORE/RECALL Initiation Cycle Time 45 55 ns
Address Set-up Time 0 0 ns q
Clock Pulse Width 30 45 ns q
Address Hold Time 20 45 ns q
RECALL Duration 20 20 µs
PARAMETER
STK14C88-3-45 STK14C88-3-55
UNITS NOTES
Note q: The software sequence is clocked with E controlled READs.
Note r: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W
must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLED
ADDRESS
26
t
AVAV
27
t
AVEL
E
t
ELEH
28
t
ELAX
29
26
t
AVAV
ADDRESS #6ADDRESS #1
r
DQ (DATA
DATA VALID
July 1999 5-38
DATA VALI D
DATA VALI D
23 30
t
/ t
STORE
HIGH IMPEDANCE
RECALL
Page 7
DEVICE OPERATION
STK14C88-3
The STK14C88-3 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static
RAM. In nonvolatile mode, data is transferred
from
SRAM to EEPROM (the STORE operation) or
from
EEPROM to SRAM (the RECALL operation). In
this mode
SRAM functions are disabled.
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
V
, using leads and traces that are as short as pos-
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88-3 performs a READ cycle whenever
E
and G are low and W is high. The address specified on pins A
data bytes will be accessed. When the
ated by an address transition, the outputs will be
valid after a delay of t
READ is initiated by E or G, the outputs will be valid
at t
ELQV
or at t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high, or W is brought low.
determines which of the 32,768
0-14
READ is initi-
(READ cycle #1). If the
AVQV
, whichever is later (READ cycle #2 ) .
GLQV
access time without the need
AVQV
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CAP
latched. When V
voltage of V
be initiated and will take t
If the STK14C88-3 is in a
power-up
), an internal RECALL request will be
RESET
once again exceeds the sense
CAP
, a RECALL cycle will automatically
SWITCH
to complete.
RESTORE
WRITE state at the end of
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
V
or between E and system VCC.
CC
and system
SOFTWARE NONVOLATILE STORE
The STK14C88-3 software STORE cycle is initiated
by executing sequential
from six specific address locations. During the
STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. The program operation copies
the
SRAM data into nonvolatile memory. Once a
STORE cycle is initiated, further input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
tant that no other
READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no
STORE or RECALL will take place.
To initiate the software
READ sequence must be performed:
E controlled READ cycles
STORE initiation, it is impor-
STORE cycle, the following
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
until either E
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W
E
controlled WRITE or t
controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
common I/O lines. If G
will turn off the output buffers t
WRITE cycle and must remain stable
or W goes high at the end of the cycle.
will be writ-
0-7
before the end
DVWH
before the end of an
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
July 1999 5-39
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
SRAM will again be activated for
STORE
READ cycles
be low for the
cycle time has
Page 8
STK14C88-3
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
E controlled READ opera-
tions must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
the t
ready for
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The RECALL
SRAM cells. After
operation in no way alters the data in the EEPROM
cells. The nonvolatile data can be recalled an unlimited number of times.
AutoStore™ OPERATION
The STK14C88-3 can be powered in one of three
modes.
During normal AutoStore™ operation, the
STK14C88-3 will draw current from V
capacitor connected to the V
CAP
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the V
automatically disconnect the V
initiate a
pin drops below V
CAP
STORE operation.
SWITCH
pin from V
CAP
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
to charge a
CCX
pin. This stored
, the part will
and
CCX
capacitor having a capacity of between 68µF and
220µF (± 20%) should be provided.
In system power mode (Figure 3), both V
V
are connected to the system power supply with-
CAP
CCX
and
out the 68µF capacitor. In this mode the
AutoStore™ function of the STK14C88-3 will operate on the stored system charge as power goes
down. The user must, however, guarantee that V
CCX
does not drop below 2.4V during the 10ms STORE
cycle.
If an automatic
then V
CCX
applied to V
STORE on power loss is not required,
can be tied to ground and system power
(Figure 4). This is the AutoStore™
CAP
Inhibit mode, in which the AutoStore™ function is
disabled. If the STK14C88-3 is operated in this configuration, references to V
V
throughout this data sheet. In this mode,
CAP
STORE operations may be triggered through soft-
should be changed to
CCX
ware control. It is not permissable to change
between these three options “on the fly”.
In order to prevent unneeded
automatic
one
most recent
initiated
whether a
STOREs will be ignored unless at least
WRITE operation has taken place since the
STORE or RECALL cycle. Software-
STORE cycles are performed regardless of
WRITE operation has taken place.
STORE operations,
HARDWARE PROTECT
The STK14C88-3 offers hardware protection
against inadvertent
WRITE
V
SRAM WRITEs will be inhibited.
s during low-voltage conditions. When V
, all externally initiated STORE operations and
SWITCH
AutoStore™ can be completely disabled by tying
STORE operation and SRAM
<
CAP
1
+
0.1µF
68µF
6v, ±20%
Bypass
16
32
31
30
17
Figure 2: AutoStore™ Mode
10kΩ
0.1µF
Bypass
Figure 3: System Power Mode
1
16
July 1999 5-40
0.1µF
0.1µF
Bypass
32
31
30
17
10kΩ
Bypass
1
1
16
16
32
32
31
31
30
30
17
17
10kΩ
Figure 4: AutoStore™
Inhibit Mode
Page 9
V
to ground and applying system VCC to V
CCX
is the AutoStore™
STOREs are only initiated by explicit request using
Inhibit mode; in this mode
CAP
. This
the software sequence.
LOW AVERAGE ACTIVE POWER
The STK14C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 5
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
and READ cycle
CC
STK14C88-3
perature range, V
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK14C88-3 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
= 3.6V, 100% duty cycle on chip
CC
READs to WRITEs; 5) the operating
level; and 7) I/O loading.
cc
Average Active Current (mA)Average Active Current (mA)
50
40
30
20
10
50
40
30
20
TTL
10
Average Active Current (mA)
CMOS
0
50 100 150 200
Cycle Time (ns)
Figure 5: Icc (max) Reads
0
50 100 150 200
Cycle Time (ns)
Figure 6: Icc (max) Writes
TTL
CMOS
July 1999 5-41
Page 10
STK14C88-3
ORDERING INFOR M ATION
STK14C88-3 N 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
45 = 45ns
55 = 55ns
Package
N = Plastic 32-pin 300 mil SOIC
W = Plastic 32-pin 600 mil DIP
July 1999 5-42
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