The STiH223 uses the latest process technology
to provide a cost-effective, feature rich, highly
integrated SoC for set-top boxes (STBs). It is
targeted at the advanced decoding STB market
across American and Asian cable networks that
utilize the ITU-T J.83 annex B physical layer. It is
suitable both for operator (with advanced security)
and retail markets.
The STiH223 provides a solution for operators
and manufacturers to specify a range of costeffective, high performance STBs, including basic
zappers, interactive STBs, and DVR STBs with
content delivery possible using broadcast or
broadband networks or both (hybrid STBs).
The STiH223 integrates a high performance cable
receiver, supporting reception, channel
demodulation, and forward error correction (FEC)
and is fully compliant with the ITU-T J.83 annex B
standard.
JTAG
CPU/FPU
Transport
Security
Transport streams
Parallel/serial in/out
ResetsAnalog out
Clocks
Modes
Clock Gen
System
services
Dual FDMA
L2 cache
Video decoder
Low power
standby
controller
ITU-T J.83 annex B
demodulator
IF in
Transport
stream
PCM I/O
S/PDIF outexternal interrupts
Audio I/O
Audio decoder
DisplayVideo I/O
STBus
STB peripherals I/O
Peripherals
Analog video
HDMI
System
interfaces
DDR3 LMI
Connectivity
SLC NAND Flash
Serial Flash
CI-Plus cards
DDR2/DDR3
Dual USB
eSATA/PCI-e
Ethernet
SD-MMC/SDIO
March 2012Doc ID 22935 Rev 11/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4
Page 2
IntroductionSTiH223
1 Introduction
The STiH223 offers current users of ST’s growing family of advanced decoding ICs
enhancements in performance and features, enabling operators to offer consumers new
multimedia-rich services and viewing experiences, including new 3DTV features. Faster
DDR3 memory is also supported, and the applications CPU benefits from an L2 cache. The
STiH223 keeps pace with the latest advanced security requirements of the main CA
vendors, and an integrated standby controller enables the STiH223 to target stringent low
power regulations.
FeaturesBenefits
ST40 applications CPU, with 32KI and 32KD L1
caches and 256K L2 cache.
Integrated low power standby controller within its
own power island.
Latest generation of ST's Delta video decoder
coupled with a High Quality Video Display
Pipeline (HQVDP).
Dual USB 2.0 hosts, eSATA, Ethernet MAC with
MII/RMII/TMII interfaces, PCI-e, SD-MMC/SDIO
interface.
NOCS1.0/1.1/1.2/3.0, NSK2.0 and DVB-CSA3
ready.
High performance processing for applications and
middleware.
Secure hibernation to, and fast resume from, very
low power passive standby mode, targeting STB
standby power < 0.5 W.
Decoding of advanced high definition standards
(MPEG2, H264, VC-1, AVS) plus the performance
and flexibility for web-based content decoding such
as Flash
impacting applications CPU performance.
Extensive high speed connectivity for the widest
range of STB peripherals, such as Flash drives,
external HDDs, Ethernet, home network controllers
(such as MoCA
memory cards.
Fully compliant with the latest advanced security
requirements of CA vendors.
®
, DivX™, MJPEG and Real®, without
®
, Wi-Fi), DOCSIS® modem and
Integrated ITU-T J.83 annex B
demodulation/FEC.
Ball compatible with other STiH2xx family
variants.
2/4Doc ID 22935 Rev 1
Highly integrated STB solution, reducing
component count and manufacturing BOM.
Single platform versatility across all networks
(satellite, cable, terrestrial, IP).
Page 3
STiH223Revision history
2 Revision history
Table 1.Document revision history
DateRevisionChanges
14-Mar-20121Initial release
Doc ID 22935 Rev 13/4
Page 4
STiH223
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