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查询STF8NK85Z供应商
N-CHANNEL 850V -1.1Ω - 6.7A TO-220/TO -2 20F P
STP8NK85Z
STF8NK85Z
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE V
STP8NK85Z
STF8NK85Z
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSS
850 V
850 V
(on) = 1.1Ω
DS
R
DS(on)ID
<1.4 Ω
<1.4 Ω
6.7A
6.7A
Pw
150 W
35 W
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFET s including revolutionary MDmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES
■ SMPS
Figure 1: Package
TO-220 TO-220FP
Figure 2: Internal Schematic Diagram
3
2
1
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STP8NK85Z P8NK85Z TO-220 TUBE
STF8NK85Z F8NK85Z TO-220FP TUBE
Rev. 5
1/12September 2005
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STP8NK85Z - STF8NK85Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
TO-220 TO-220FP
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
j
T
stg
() Pulse wi dt h l i m i ted by safe operating area
≤6.7A, di/dt ≤200A/µs, VDD = 80% V
(1) I
SD
(*) Limited only by maximum temperature allowed
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
850 V
850 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed) 26.7 26.7 (*) A
Total Dissipation at TC = 25°C
6.7 6.7 (*) A
4.3 4.3 (*) A
150 35 W
Derating Factor 1.20 0.28 W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 KV
Insulation Withstand Voltage (DC) - 2500 V
Operating Junction Temperature
Storage Temperature
(BR)DSS
-55 to 150
-55 to 150
°C
°C
Table 4: Thermal Data
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 0.83 3.6 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering
300 °C
Purpose
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
6.7 A
350 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source
Igs=± 1mA (Open Drain) 30 V
Breakdown Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity . These integrated Zener diodes thus avoid the
usage of external components.
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STP8NK85Z - STF8NK85Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On/Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID = 1 mA, VGS = 0 850 V
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ± 20V ±10 µA
GS
V
= VGS, ID = 100µA
DS
33.754.5V
1
50
VGS = 10V, ID = 3.35 A 1.1 1.4 Ω
Resistance
Table 8: DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS = 15 V, ID= 3.35 A 6 S
g
fs
C
oss eq.
C
C
C
t
d(on)
t
d(off)
iss
oss
rss
t
r
t
f
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3) Equivalent Outpu t
Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
= 25V, f = 1 MHz, VGS = 0 1870
V
DS
190
44
VGS = 0V, VDS = 0V to 680V 75 pF
= 425 V, ID = 3.35 A
V
DD
R
=4.7Ω VGS = 10 V
G
(see Figure 19)
26
19
58
18
µA
µA
pF
pF
pF
ns
ns
ns
ns
= 680 V, ID = 6.7 A,
t
r(Voff)
t
Q
Q
Q
t
f
c
g
gs
gd
Fall Time
Cross-over Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Off-voltage Rise Time
V
DD
RG=4.7Ω, V
(see Figure 20)
= 680V, ID = 6.7 A,
V
DD
VGS = 10V
(see Figure 22)
GS
= 10V
12
10
24
60
12
35
84
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
(2)
SDM
(1)
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: P ul se duration = 300 µs, duty cycle 1.5 % .
2. Pulse wi dt h l i m ited by safe op erating area.
3. C
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
.
V
DSS
ISD = 6.7 A, VGS = 0
I
SD
VDD = 35V, Tj = 25°C
(see Figure 20)
I
SD
V
DD
(see Figure 20)
= 6.7 A, di/dt = 100A/µs
= 6.7 A, di/dt = 100A/µs
= 35V, Tj = 150°C
530
4.5
17
690
6.4
17
when VDS increases from 0 to 80%
oss
6.7
26.7
1.6 V
ns
ns
ns
nC
nC
nC
A
A
ns
µC
A
ns
µC
A
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STP8NK85Z - STF8NK85Z
Figure 3: Safe Operating Area for TO-220
Figure 4: Safe Operating Area for TO-220FP
Figure 6: Thermal Impedan ce for TO -2 20
Figure 7: Thermal Impedan ce for TO -2 20FP
Figure 5: Output Characteristics
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Figure 8: Transfer Characteristics
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STP8NK85Z - STF8NK85Z
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 12: Static Drain-source On Resistance
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Thereshold Voltage vs Temperature
Figure 14: Normalized BVDSS vs Temperature
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Figure 15: Norm alized O n Resis tance vs T emperatureS
Figure 16: Avalanche Energy vs Temp eratur e
Figure 17: S ource-Drain Diode Forw ard Characteristics
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STP8NK85Z - STF8NK85Z
Figure 18: Unclamped Inductive Load Test Circuit
Figure 19: Switching Times Test Circuit For
Resistive Load
Figure 21: Unclamped Inductive Wafeform
Figure 22: Gate Charge Test Circuit
Figure 20: Test Circuit For Inductive Load
Switching and Diode Recovery Times
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STP8NK85Z - STF8NK85Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, i n compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
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TO-220 MECHANICAL DATA
STP8NK85Z - STF8NK85Z
DIM.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
9/12
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STP8NK85Z - STF8NK85Z
TO-220FP MECHANICAL DATA
DIM.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
E
A
D
B
L3
L6
L7
F1
F
G1
H
F2
123
L2
L5
L4
G
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Table 10: Revision History
Date R evisio n Descrip tion of Change s
02-Mar-2005 1 First Release.
03-Mar-2005 2 Modified value in table 7
26-Apr-2005 3 Modified values in table 8 and inserted curves. Final datasheet.
09-May-2005 4 Modified note1 and Application Scope
06-Sep-2005 5 Inserted Ecopack indication
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STP8NK85Z - STF8NK85Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is gra nted
by implic ati o n or ot h er wis e und er an y pat ent or pa te nt r igh ts of STMi cr oe l ect ro ni cs . Sp ec if i cat i on s ment i o ned i n th is p ub li c ati on ar e s ubj ec t
to change without not ice. This publication supersedes and replaces all information previously sup plied. STMicroelectr onics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
12/12
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