The SuperMESH™ se ries is obtained through an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down , special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS FET s including revolutionary MDmesh™ products.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage± 30V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed)1414 (*)A
Total Dissipation at TC = 25°C
3.53.5 (*)A
2.22.2 (*)A
12530W
Derating Factor10.24W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ)4000V
dv/dt (1)Peak Diode Recovery voltage slope4.5V/ns
V
ISO
T
j
T
stg
() Pulse width limited by saf e operating area
≤3.5A, di/dt ≤200A/µs, VDD ≤ V
(1) I
SD
(*) Limited only by maximum temperature allowed
Insulation Withstand Voltage (DC)-2500V
Operating Junction Temperature
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
3.5A
250mJ
Table 6: Gate-Source Zener Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/12
Page 3
STP5NK100Z - STF5NK100Z - ST W5NK100Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 01000V
Voltage
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
= Max Rating
DS
V
= Max Rating,
DS
1
50
TC = 125°C
I
GSS
V
GS(th)
R
DS(on)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= ± 20 V± 10µA
GS
V
= VGS, ID = 100 µA3
DS
3.75
4.5V
VGS = 10 V, ID = 1.75 A2.73.7Ω
Resistance
Table 8: Dynamic
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(1)Forward TransconductanceVDS = 15 V , ID = 1.75 A4S
fs
C
oss eq
C
C
C
t
d(on)
t
d(off)
Q
Q
Q
iss
oss
rss
t
r
t
gs
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
= 25 V, f = 1 MHz,
V
DS
VGS = 0
1154
106
21.3
(3).Equivalent Outpu t Capacitance VGS = 0 V, VDS = 0 to 800 V46.8pF
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 500 V, ID = 1.75 A,
V
DD
R
= 4.7 Ω, V
G
GS
(see Figure 21)
= 800 V, ID = 3.5 A,
V
DD
V
= 10 V
GS
(see Figure 24)
= 10 V
22.5
7.7
51.5
19
42
7.3
21.7
59nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse durat ion = 300 µs, duty cycle 1.5 %.
(2) Pulse width limite d by safe operatin g area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 3.5 A, VGS = 0
= 3.5 A, di/dt = 100 A/µs
I
SD
V
= 35V
DD
(see Figure 22)
= 3.5 A, di/dt = 100 A/µs
I
SD
VDD = 35V, Tj = 150°C
(see Figure 22)
605
3.09
10.5
742
4.2
11.2
when VDS increase s from 0 to 80% V
oss
3.5
14
1.6V
A
A
ns
µC
A
ns
µC
A
DSS
3/12
.
Page 4
STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 3: Safe Operating Area For TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance TO-220
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Safe Operating Area For TO-247
4/12
Figure 8: Thermal Impedance For TO-247
Page 5
STP5NK100Z - STF5NK100Z - ST W5NK100Z
Figure 9: Output Characteristics
Figure 10: Transconductance
Figure 12: Transfer Characteristics
Figure 13: Static Drain-Source On Resis tance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 14: Capacitance Variations
5/12
Page 6
STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 15: Normalized Gate Threshold Voltage
vs Tem pera tur e
Figure 16: S ource-Drain Forward Char acteristics
Figure 18: Normal ized On R esistance vs Temperature
Figure 19: Normalized BV
vs Temperature
DSS
Figure 17: Maximum Avalanche Energy vs
Temperature
6/12
Page 7
STP5NK100Z - STF5NK100Z - ST W5NK100Z
Figure 20: Unclamped Inductive Load Test Circuit
Figure 21: Switching Times Test Circuit For
Resistive Load
Figure 23: Unclamped Inductive Wafeform
Figure 24: Gate Charge Test Circuit
Figure 22: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third par ties wh ich m ay res ul t from i ts us e. No licens e is gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners