
This is information on a product in full production.
STB24N65M2, STF24N65M2,
STP24N65M2
N-channel 650 V, 0.185 Ω typ., 16 A MDmesh M2
Power MOSFET in D2PAK, TO-220FP and TO-220 packages
Datasheet - production data
Features
Extremely low gate charge
Figure 1: Internal schematic diagram
Excellent output capacitance (C
100% avalanche tested
Zener-protected
Applications
Switching applications
) profile
oss
Description
These devices are N-channel Power MOSFETs
developed using MDmesh™ M2 technology.
Thanks to their strip layout and improved vertical
structure, the devices exhibit low on-resistance
and optimized switching characteristics,
rendering them suitable for the most demanding
high efficiency converters.
Table 1: Device summary

STB24N65M2, STF24N65M2, STP24N65M2
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package mechanical data ................................ ............................. 10
4.1 D2PAK package information ........................................................... 10
4.2 TO-220FP package information ...................................................... 13
4.3 TO-220 type A package information ................................................ 15
5 Packaging mechanical data .......................................................... 17
6 Revision history ............................................................................ 19

STB24N65M2, STF24N65M2, STP24N65M2
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Total dissipation at TC = 25 °C
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all three
leads to external heat sink (t = 1 s; TC = 25 °C)
Max. operating junction temperature
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area.
(3)
ISD ≤ 16 A, di/dt ≤ 400 A/µs; V
DS(peak)
< V
(BR)DSS
, VDD = 80% V
(BR)DSS
.
(4)
VDS ≤ 520 V
Thermal resistance junction-case max
Thermal resistance junction-pcb max
(1)
Thermal resistance junction-ambient max
(1)
When mounted on 1 inch² FR-4, 2 Oz copper board.
Avalanche current, repetitive or not repetitive (pulse width limited by T
jmax
)
Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50V)
1 Electrical ratings
Table 2: Absolute maximum ratings
Table 3: Thermal data
Table 4: Avalanche characteristics

Electrical characteristics
STB24N65M2, STF24N65M2, STP24N65M2
Drain-source breakdown voltage
Zero gate voltage
drain current (VGS = 0)
Gate-body leakage
current (VDS = 0)
Static drain-source
on-resistance
VDS = 100 V, f = 1 MHz,
VGS = 0
Reverse transfer capacitance
Equivalent output capacitance
VDS = 0 to 520 V, VGS = 0
Intrinsic gate resistance
VDD = 520 V, ID = 16 A,
VGS = 10 V
(1)
C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when VDS
increases from 0 to 80% V
DSS
VDD = 325 V, ID = 8 A,
RG = 4.7 Ω, VGS = 10 V
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5: On /off states
Table 6: Dynamic
Table 7: Switching times

STB24N65M2, STF24N65M2, STP24N65M2
Electrical characteristics
Source-drain current (pulsed)
ISD = 16 A, di/dt = 100 A/µs
VDD = 60 V
ISD = 16 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8: Source drain diode

Electrical characteristics
STB24N65M2, STF24N65M2, STP24N65M2
Figure 2: Safe operating area for D2PAK and
TO-220
Figure 3: Thermal impedance for D2PAK and
TO-220
Figure 4: Safe operating area for TO-220FP
Figure 5: Thermal impedance for TO-220FP
Figure 6: Output characteristics
Figure 7: Transfer characteristics
ID
10
5
0
VDS(V)
4
(A)
0
VGS= 7, 8, 9, 10 V
6V
5V
4V
8
15
20
25
12 16 20 24 28
30
35
GIPD180920141533FSR
ID
10
5
0
VGS(V)
2
(A)
0
VDS= 20 V
4
15
20
25
6 8
30
35
GIPD180920141600FSR
2.1 Electrical characteristics (curves)

STB24N65M2, STF24N65M2, STP24N65M2
Electrical characteristics
Figure 8: Gate charge vs gate-source voltage
Figure 9: Static drain-source on-resistance
Figure 10: Capacitance variations
Figure 11: Normalized gate threshold voltage
vs temperature
Figure 12: Normalized on-resistance
Figure 13: Normalized V(BR)DSS vs
temperature
VGS
4
2
0 5 15
Qg(nC)
10
(V)
0
20
6
8
10
12
25
VDS
(V)
0
100
200
300
400
500
600
VDD = 520 V
ID = 16 A
30
VDS
GIPD041020141607FSR
RDS(on)
0.178
0
ID(A)
4
(Ω)
0.175
8
0.181
0.184
VGS= 10V
0.187
12 16
0.190
0.193
0.196
GIPD180920141613FSR
C
10
1
0.1 1 100 VDS(V)10
(pF)
0.1
100
1000
Ciss
Coss
Crss
f= 1 MHz
GIPD041020141619FSR
RDS(on)
1
-75 -25 75
Tj(°C)
25
(norm)
0.2
125
0.6
1.4
1.8
2.2
VGS= 10V
GIPD180920141459FSR

Electrical characteristics
STB24N65M2, STF24N65M2, STP24N65M2
Figure 14: Source-drain diode forward
characteristics
Figure 15: Output capacitance stored energy
VSD
0.7
0 4 12
ISD(A)
8
(V)
0.5
0.6
0.8
0.9
Tj= 150°C
Tj= -50°C
Tj= 25°C
16
1
1.1
GIPD041020141624FSR
E
2
0 100 300
VDS(V)
200
(µJ)
0
400 500 600
4
6
8
GIPD041020141629FSR

STB24N65M2, STF24N65M2, STP24N65M2
Figure 16: Switching times test circuit for
resistive load
Figure 17: Gate charge test circuit
Figure 18: Test circuit for inductive load
switching and diode recovery times
Figure 19: Unclamped inductive load test
circuit
Figure 20: Unclamped inductive waveform
Figure 21: Switching time waveform
3 Test circuits

STB24N65M2, STF24N65M2, STP24N65M2
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1 D2PAK package information
Figure 22: D²PAK (TO-263) drawing

STB24N65M2, STF24N65M2, STP24N65M2
Table 9: D²PAK (TO-263) mechanical data

STB24N65M2, STF24N65M2, STP24N65M2
All the dimensions are in millimeters.
Figure 23: D²PAK footprint

STB24N65M2, STF24N65M2, STP24N65M2
4.2 TO-220FP package information
Figure 24: TO-220FP package outline

STB24N65M2, STF24N65M2, STP24N65M2
Table 10: TO-220FP mechanical data

STB24N65M2, STF24N65M2, STP24N65M2
4.3 TO-220 type A package information
Figure 25: TO-220 type A package outline

STB24N65M2, STF24N65M2, STP24N65M2
Table 11: TO-220 type A mechanical data

STB24N65M2, STF24N65M2, STP24N65M2
Packaging mechanical data
5 Packaging mechanical data
Figure 26: Tape

Packaging mechanical data
STB24N65M2, STF24N65M2, STP24N65M2
A
D
B
Full radius
Tape slot
In core for
Tape start
2.5mm min.width
G measured
At hub
C
N
40mm min.
Access hole
At slot location
T
AM06038v1
Figure 27: Reel
Table 12: D²PAK (TO-263) tape and reel mechanical data

STB24N65M2, STF24N65M2, STP24N65M2
Document status promoted from preliminary to production data.
6 Revision history
Table 13: Document revision history

STB24N65M2, STF24N65M2, STP24N65M2
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications , and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved