Datasheet STE70NM50 Datasheet (SGS Thomson Microelectronics)

STE70NM50

N-CHANNEL 500V - 0.045Ω - 70A ISOTOP

Zener-Protected MDmesh™Power MOSFET

TYPE V

DSS

R

DS(on)

I

D

STE70NM50 500V < 0.05Ω 70 A

n

TYPICAL RDS(on) = 0.045Ω

n

HIGH dv/dt AND AVALANCHE CAPABILITIES

n

IMPROVED ESD CAPABILITY

n

LOW INPUT CAPACITANCE AND GATE
CHARGE

n

LOW GATE INPUT RESIST ANC E

n

TIGHT PROCESS CONTRO L

n

INDUSTRY’S LOWEST ON-RESISTANCE

DESCRIPTION

The MDmesh™

is a new revolutionary MOSFET

technology that associates the Multiple Drain pro­cess with the Company’s PowerMESH™ horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar competition’s products.

APPLICATIONS

The MDmesh™ family is very suitable for increasing
power density of high voltage converters allowing
system miniaturization and higher efficiencies.

ISOTOP

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

TOT

V

ESD(G-S)

dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns

T

stg

T

j

(•)Pu l se width limited by safe operating area

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)

500 V
500 V

Gate- source Voltage ±30 V

Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C

(l)

Drain Current (pulsed) 280 A
Total Dissipation at TC = 25°C

70 A
44 A

600 W
Gate source ESD(HBM-C=100pF, R=15KΩ) 6KV
Derating Factor 5 W/°C

Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C

(1)ISD ≤60A, di/dt ≤400A/µs, VDD ≤ V

(BR)DSS

, Tj ≤ T

JMAX

1/8September 2002

STE70NM50

THERMA L D ATA

Rthj-case Thermal Resistance Junction-case Max 0.2 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W

T

l

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

I

AR

E

AS

Maximum Lead Temperature For Soldering Purpose 300 °C

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

= 25 °C, ID = IAR, VDD = 35 V)

j

30 A

1.4 J

ELECTRICAL CHARACTERISTICS (T

= 25 °C UNLESS OTHERWISE SPECIFIED)

CASE

OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

Drain-source

ID = 250 µA, VGS = 0 500 V

Breakdown Voltage

ON

I

I

GSS

(1)

DSS

Zero Gate Voltage
Drain Current (V

GS

Gate-body Leakage
Current (V

DS

= 0)

= 0)

V

= Max Rating

DS

VDS = Max Rating, TC = 125 °C
V

= ± 20V ± 10 µA

GS

10 µA

100 µA

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

GS(th)

R

DS(on)

Gate Threshold Voltage
Static Drain-source On

V

= VGS, ID = 250µA

DS

VGS = 10V, ID = 30A

345V

0.045 0.05 Ω

Resistance

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(1) Forward Transconductance VDS > I

g

fs

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 980 pF
Reverse Transfer

I

D

V

Capacitance

R

G

Gate Input Resistance f=1 MHz Gate DC Bias = 0

Test Signal Level = 20mV
Open Drain

Note: 1. Pulsed: Pu l se duration = 300 µs, duty c ycle 1.5 %.

= 30A

DS

D(on)

x R

DS(on)max,

= 25V, f = 1 MHz, VGS = 0

35 S

7500 pF

200 pF

1.5 Ω

2/8

STE70NM50

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

t

d(on)

Q

Q

Q

t

r

g

gs

gd

Turn-on Delay Time
Rise Time 58 ns
Total Gate Charge

Gate-Source Charge 53 nC
Gate-Drain Charge 97 nC

SWITCHING OFF

Symbol Param eter Test Conditions Min. Typ. Max. Unit

t

r(Voff)

t

t

f

c

Off-voltage Rise Time
Fall Time 46 ns
Cross-over Time 108 ns

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD (1)

t

rr

Q

rr

I

rrm

t

rr

Q

rr

I

rrm

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2. Pulse width limi ted by safe operating area.

(2)

Source-drain Current 60 A
Source-drain Current (pulsed) 240 A
Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charg e
Reverse Recovery Curren t

Reverse Recovery Time
Reverse Recovery Charg e
Reverse Recovery Curren t

= 250V, ID = 30A

DD

RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)

V

= 400V, ID = 60A,

DD

V

= 10V

GS

V

= 400V, ID = 60A,

DD

RG= 4.7Ω, V

GS

= 10V

(see test circuit, Figure 5)

ISD = 60A, VGS = 0

= 60A, di/dt = 100A/µs,

I

SD

V

= 100 V, Tj = 25°C

DD

(see test circuit, Figure 5)

= 60A, di/dt = 100A/µs,

I

SD

VDD = 100 V, Tj = 150°C
(see test circuit, Figure 5)

51 ns

190 266 nC

51 ns

1.5 V

532

9.9
37

636

13.4
42

ns

µC

A

ns

µC

A

GATE-SOURCE ZENER DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BV

GSO

Gate-Source Breakdown

Igs=± 1mA (Open Drain) 30 V

Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specificall y been des igned to enhan ce not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the 25V Zener voltage is appropriate to achieve an efficient
and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid
the usage of external components.

3/8

STE70NM50

Safe Operating Area Thermal Impedance

Output Characteristics

Transconductance

Transfer Characteristics

Static Drain-source On Resistance

4/8

Gate Charge vs Gate-source Voltage Capacitance Variation s

STE70NM50

Normalized Gate Threshold Volta ge vs Temp.

Source-drain Diode Forward Characteristics

Normalized On Resistance vs Temperatur e

5/8

STE70NM50

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit For

Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

6/8

ISOTOP MECHANICAL DATA

STE70NM50

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 11.8 12.2 0.466 0.480
B 8.9 9.1 0.350 0.358
C 1.95 2.05 0.076 0.080
D 0.75 0.85 0.029 0.033
E 12.6 12.8 0.496 0.503

F 25.15 25.5 0.990 1.003
G 31.5 31.7 1.240 1.248
H4 0.157

J 4.1 4.3 0.161 0.169
K 14.9 15.1 0.586 0.594

L 30.1 30.3 1.185 1.193
M 37.8 38.2 1.488 1.503
N4 0.157
O 7.8 8.2 0.307 0.322

mm inch

G

A

N

O

B

D

E

F

H

J

C

K
L

M

7/8

STE70NM50

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco

© The ST logo is a registered trademark of STMicroelectronics

© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved

Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

STMicroelectronics GROUP OF COMPANIES

© http://www.st.com

8/8