Using the latest high voltage MESH OVERLAY
process, STMicroelectronicshas designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and
dv/dt capabilities and unrivalled gate charge and
switchingcharacteristics.
R
DS(on)
I
D
Ω
- 38A - ISOTOP
PowerMESH MOSFET
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGHCURRENT, HIGH SPEED SWITCHING
■ SWITCHMODE POWER SUPPLY (SMPS)
■ DC-AC CONVERTERFOR WELDING
EQUIPMENTANDUNINTERRUPTABLE
POWERSUPPLY AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symb o lParameterValueUnit
V
V
V
I
DM
P
dv/dt
T
(•) Pulse width limited by safe operating area(1)ISD≤38 A, di/dt ≤ 200 A/µs, VDD≤ V
December 1999
Drain-source Volt age (VGS= 0)500V
DS
Drain- g at e Voltag e (RGS=20kΩ)500V
DGR
Gate-s ource Voltage
GS
I
Drain C urrent (continu ous ) at Tc=25oC38A
D
I
Drain C urrent (continu ous ) at Tc=100oC24A
D
30V
±
(•)Drain C urrent (pulsed)152A
Tot al Diss i pat ion at Tc=25oC400W
tot
Derat ing Fact or3.2W/
(1) Peak Diode R ecov e ry volt ag e slope4.5V/ns
Sto rage Temper at ur e-65 to 150
stg
T
Max. Oper a t ing Junction Temperature150
j
(BR)DSS,Tj≤TJMAX
o
C
o
C
o
C
1/8
Page 2
STE38NB50F
THERMAL DATA
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
SymbolParameterMax ValueUnit
I
AR
E
Ther mal Resistance J unction- ca seMax
Ther mal Resistance J unction- am bie ntMax
Ther mal Resistance C ase-sinkTy p
Maximum Lead T e m perature For So lder ing Purpose
l
Avalanche Current, Repetitive or Not-Repetiti ve
(pulse width limited by T
Single Pul s e Avalanc he E ner gy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max)
j
0.31
30
0.1
300
38A
1200mJ
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
V
(BR)DSS
Drain-source
ID=250µAVGS= 0500V
Break dow n Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gat e- bod y Leak ag e
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRatingTc= 125oC
V
DS
V
=± 30 V
GS
10
100
100nA
±
ON(∗)
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage VDS=VGSID= 250 µA345V
Sta t ic Drain-s ource On
VGS=10VID= 1 9 A0.110.14
Resistance
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
38A
VGS=10V
DYNAMIC
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
g
(∗)Forward
fs
Tr ansc on duc tance
C
C
C
Input Capaci t anc e
iss
Out put Capac it ance
oss
Reverse Transfer
rss
Capacit a nc e
VDS>I
D(on)xRDS(on)maxID
=19A27S
VDS=25V f=1MHz VGS= 05900
880
80
µ
µA
Ω
pF
pF
pF
A
2/8
Page 3
STE38NB50F
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
t
d(on)
t
r
Turn-on Time
Rise Tim e
VDD=250VID=19A
R
=4.7
G
Ω
VGS=10V
45
35
(see test circuit, figure 3)
Q
Q
Q
Tot al Gate Charge
g
Gat e- Source Charg e
gs
Gate-Drain Charge
gd
VDD= 400 V ID=38A VGS= 10 V140
38
61
196nC
SWITCHING OFF
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
t
r(Voff)
t
t
Off-voltage Rise Time
Fall T ime
f
Cross-over Time
c
VDD=400VID=38A
=4.7 ΩVGS=10V
R
G
(see test circuit, figure 5)
28
30
60
SOURCEDRAINDIODE
SymbolParameterTest Condit ionsMin.Typ.M ax.Unit
I
V
I
SDM
SD
Q
I
RRM
SD
t
Source-drain Current
(•)
Source-drain Current
38
152
(pulsed)
(∗)ForwardOnVoltage ISD=38A VGS=01.6V
Reverse Recovery
rr
Time
Reverse Recovery
rr
ISD= 38 Adi/dt = 100 A/µs
= 100 VTj=150oC
V
DD
(see test circuit, figure 5)
715
11.8
Charge
Reverse Recovery
33
Current
ns
ns
nC
nC
ns
ns
ns
A
A
ns
µ
A
C
(∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
SafeOperating AreaThermalImpedance
3/8
Page 4
STE38NB50F
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/8
CapacitanceVariations
Page 5
STE38NB50F
NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
5/8
Page 6
STE38NB50F
Fig. 1:
UnclampedInductiveLoad Test Circuit
Fig. 3: Switching Times Test CircuitsFor
ResistiveLoad
Information furnished is believed tobeaccurateand reliable.However, STMicroelectronics assumesno responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subjecttochange without notice. This publication supersedes and replaces all information previouslysupplied.STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China- Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
8/8
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
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