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PRELIMINARY DATA
July 2001
STD8NS25
N-CH A NNEL 250V - 0.38Ω - 8A DPAK
MESH OVERLAY™ MOSFET
■ TYPICAL R
DS
(on) = 0.38 Ω
■ EXTREMELY HIGH dv /d t C APABILITY
■ 100% AVALANCHE TESTED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for
lighting applications.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLI ES ( SMPS)
■ DC-DC CONVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
(•)Pu l se width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STD8NS25 250 V < 0.45 Ω 8 A
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
250 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
250 V
V
GS
Gate- source Voltage ± 20 V
I
D
Drain Current (continuos) at TC = 25°C
8A
I
D
Drain Current (continuos) at TC = 100°C
5A
I
DM
(●)
Drain Current (pulsed) 32 A
P
TOT
Total Dissipation at TC = 25°C
80 W
Derating Factor 0.64 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns
E
AS
(2)
Single Pulse Avalanche Energy 209 mJ
T
stg
Storage Temperature –65 to 150 °C
T
j
Max. Operating Junction Temperature 150 °C
(1) ISD≤ 8A, di/dt≤300 A/µs, VDD≤ V
(BR)DSS
, Tj≤ T
jMAX
(2) Start i ng Tj = 25°C, I
AR
= 50A, VDD=20 V
INTERNAL SCHEMATIC DIAGRAM
DPAK
1
3
STD8NS25
2/6
THERMA L D ATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
Rthj-case Thermal Resistance Junction-case Max 1.56 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose 300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
8A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, ID = IAR, VDD = 50 V)
300 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0 250 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1µA
V
DS
= Max Rating, TC = 125 °C
10 µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ±20V ±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 250µA
234V
R
DS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 4 A
0.38 0.45 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance VDS > I
D(on)
x R
DS(on)max,
I
D
=4A
78 S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, VGS = 0
770 pF
C
oss
Output Capacitance 118 pF
C
rss
Reverse Transfer
Capacitance
48 pF
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STD8NS25
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c yc l e 1.5 %.
2. Pulse width li mited by safe operating area.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Turn-on Delay Time
V
DD
= 125 V, ID = 4 A
RG= 4.7Ω VGS = 10 V
(see test circuit, Figure 3)
13 ns
t
r
Rise Time 18 ns
Q
g
Total Gate Charge
V
DD
= 200V, ID = 8 A,
VGS = 10V
37 50 nC
Q
gs
Gate-Source Charge 5.2 nC
Q
gd
Gate-Drain Charge 14.8 nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(Voff)
t
f
Turn-off- Delay Time
Fall Time
VDD = 125V, ID = 4 A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 3)
51
16
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
clamp
= 200V, ID = 8 A,
R
G
=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
12.5
12.5
28
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
Source-drain Current 8 A
I
SDM
(2)
Source-drain Current (pulsed) 32 A
VSD (1)
Forward On Voltage
ISD = 8 A, VGS = 0
1.7 V
t
rr
Reverse Recovery Time
I
SD
= 8 A, di/dt = 100A/µs
VDD = 30V, Tj = 150°C
(see test circuit, Figure 5)
198 ns
Q
rr
Reverse Recovery Charge 1.1 µC
I
RRM
Reverse Recovery Current 11.3 A
STD8NS25
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
5/6
STD8NS25
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.20 2.40 0.087 0.094
A1 0.90 1.10 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.90 0.025 0.035
B2 5.20 5.40 0.204 0.213
C 0.45 0.60 0.018 0.024
C2 0.48 0.60 0.019 0.024
D 6.00 6.20 0.236 0.244
E 6.40 6.60 0.252 0.260
G 4.40 4.60 0.173 0.181
H 9.35 10.10 0.368 0.398
L2 0.8 0.031
L4 0.60 1.00 0.024 0.039
V2 0
o
8
o
0
o
0
o
P032P_B
TO-252 (DPAK) MECHANICAL DATA
STD8NS25
6/6
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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