Datasheet STD60NF3LL Datasheet (SGS Thomson Microelectronics)

STD60NF3LL

N-CHANNEL 30V - 0.0075Ω - 60A DPAK

STripFET™ II POWER MOSFET

TYPE V

STD60NF3LL 30V <0.0095Ω 60A

■ TYPICAL R

■ OPTIMAL RDS(O N) x Qg TRA D E-OFF @ 4.5V

■ CONDUCTION LOSSES REDUCED

■ SWITCHING LOSSES REDUCED

■ ADD SUFFIX “T4” FOR ORDERING IN TAPE &

DS

DSS

(on) = 0.0075Ω

R

DS(on)

I

D

REEL

DESCRIPTION

This application specific Powe r M osfet i s the t hird
genaration of STMicroelectronics unique “Single
Feature Size

™” strip-based process. The resul t-

ing transistor shows the best trade-off between on­resistance ang gate charge. When used as high
and low side in buck regulators, it gives the best
performance in terms of both conduction and
switching losses. This is e xtremely important for
motherboards where fast switching and high e ffi­ciency are of paramount importance.

APPLICATIONS

■ SPECIFICALLY D ESIGNED AND OP TIMISED

FOR HIGH EFFICIENCY DC/DC
CONVERTERS

3

1

DPAK

TO-252

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

TOT

E

AS

T

stg

T

j

(●) Pulse width limited by safe operating area

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ± 16 V

Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C

(l)

Drain Current (pulsed) 240 A
Total Dissipation at TC = 25°C
Derating Factor 0.67 W/°C

(1)

Single Pulse Avalanche Energy 700 mJ
Storage Temperature
Operating Junction Temperature

(1) Starting Tj=25°C, ID=30A, VDD=27.5V

30 V
30 V

60 A
43 A

100 W

– 55 to 175 °C

1/9April 2002

STD60NF3LL

THERMA L D ATA

Rthj-case Thermal Resistance Junction-case Max 1.5 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W

T

l

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

ON

(1)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

GS(th)

R

DS(on)

Maximum Lead Temperature For Soldering Purpose 300 °C

Drain-source

ID = 250 µA, VGS = 0 30 V

Breakdown Voltage
Zero Gate Voltage

Drain Current (V

GS

= 0)

Gate-body Leakage
Current (V

DS

= 0)

Gate Threshold Voltage
Static Drain-source On

Resistance

V

= Max Rating

DS

V

= Max Rating, TC = 125 °C

DS

V

= ± 16V ±100 nA

GS

V

= VGS, ID = 250µA

DS

= 10 V, ID = 30 A

V

GS

VGS = 4.5 V , ID = 30 A

1V

0.0075

0.0085

1µA

10 µA

0.0095

0.0105

Ω
Ω

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(1) Forward Transconductance VDS =15 V, ID=30 A 30 S

g

fs

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 635 pF
Reverse Transfer

Capacitance

V

= 25V, f = 1 MHz, VGS = 0

DS

2210 pF

138 pF

2/9

STD60NF3LL

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

t

d(on)

Q
Q
Q

t

r

g
gs
gd

Turn-on Delay Time
Rise Time 130 ns
Total Gate Charge

Gate-Source Charge
Gate-Drain Charge

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(off)

t

d(off)

t

f

t

f

t

c

Turn-off-Delay Time
Fall Time

Off-voltage Rise Time
Fall Time
Cross-over Time

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD (2)

t

rr

Q

rr

I

RRM

Note: 1. Pulsed: Pu l se duration = 300 µs, duty cyc l e 1.5 %.

2. Pulse width li mited by safe operating ar ea.

Source-drain Current 60 A

(1)

Source-drain Current (pulsed) 240 A
Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

= 15V, ID = 30A

DD

R

= 4.7Ω VGS = 4.5V

G

(see test circuit, Figure 3)

= 24V, ID = 60A,

V

DD

VGS = 4.5V

= 15V, ID = 30A,

V

DD

RG=4.7Ω, V

GS

= 4.5V

(see test circuit, Figure 3)

GS

=30A

D

= 4.5V

Vclamp =24V, I
R

=4.7Ω, V

G

(see test circuit, Figure 5)

ISD = 60A, VGS = 0

= 60A, di/dt = 100A/µs,

I

SD

VDD = 15V, Tj = 150°C
(see test circuit, Figure 5)

22 ns

30

40 nC

9

12.5

36.5

36.5

32
23
40

1.2 V

65

105

3.4

nC
nC

ns
ns

ns
ns
ns

ns

nC

A

Thermal ImpedenceSafe Operating Area

3/9

STD60NF3LL

Output Characteristics

Transconductance Static Drain-source On Resistance

Transfer Characteristics

Gate Charge vs Gate-source Voltage Capacitance Variations

4/9

Source-drain Diode Forward Characteristics

STD60NF3LL

Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.

5/9

STD60NF3LL

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit For

Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

6/9

TO-252 (DPAK) MECHANICAL DATA

STD60NF3LL

DIM.

A 2.20 2.40 0.087 0.094
A1 0.90 1.10 0.035 0.043
A2 0.03 0.23 0.001 0.009

B 0.64 0.90 0.025 0.035
B2 5.20 5.40 0.204 0.213

C 0.45 0.60 0.018 0.024
C2 0.48 0.60 0.019 0.024

D 6.00 6.20 0.236 0.244

E 6.40 6.60 0.252 0.260

G 4.40 4.60 0.173 0.181

H 9.35 10.10 0.368 0.398
L2 0.8 0.031
L4 0.60 1.00 0.024 0.039
V2 0

MIN. TYP. MAX. MIN. TYP. MAX.

o

mm inch

o

8

o

0

o

0

P032P_B

7/9

STD60NF3LL

DPAK FOOTPRINT

All dimensions are in millimeters

TAPE AND REEL SHIPMENT (suffix ”T4”)*

TUBE SHIPMENT (no suffix)*

All dimensions

are in millimeters

REEL MECHANICAL DATA

DIM.

A 330 12.992

B 1.5 0 .059
C 12 .8 13.2 0.504 0.520
D 20 .2 0.795
G 16 .4 18. 4 0.645 0.724
N 50 1.968

T 22.4 0.881

mm inch

MIN. MAX. MIN. MAX.

TAPE MECHANICAL DATA

DIM.

A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476

D 1.5 1.6 0.059 0.063

D1 1.5 0.059

E 1.65 1.85 0.065 0.073

F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082

R 40 1.574

W 15.7 16.3 0.618 0.641

* on sales type

8/9

mm inch

MIN. MAX. MIN. MAX.

BASE QTY BULK QTY

2500 2500

STD60NF3LL

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibilit y for the
consequences of use of su ch in formation nor for any in fringement of paten ts or o ther rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as c ritical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco

© The ST logo is a registered trademark of STMicroelectronics

© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved

Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

STMicroelectronics GROUP OF COMPANIES

© http://www.st.com

9/9