The SuperMESH ™ series is obtained through an
extreme optimi za tio n of ST’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the
most demanding applications. Such series complements ST full range of high voltage MOSFETs i ncluding revolutionary MDmesh™ products.
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
E
AS
Single Pulse Avalanche Energy
(starting T
max)
j
= 25 °C, ID=IAR,VDD=50V)
j
3A
120mJ
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIOD ES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possibl e voltage transients that may occasionally be
applied from gate to source. In this r es pect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/13
Page 3
STP4NK50Z - STP4NK50ZFP - STD4NK50Z - STD4NK50Z-1
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
ON/OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
ID=1mA,VGS= 0500V
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage
Drain Current (V
GS
=0)
Gate-body Leakage
Current (V
DS
=0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
VDS= Max Rating, TC= 125 °C
V
= ± 20V±10µA
GS
V
DS=VGS,ID
= 50µA
33.754.5V
1
50
VGS=10V,ID= 1.5 A2.32.7Ω
Resistance
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(1)Forward TransconductanceVDS=15V,ID= 1.5 A1.5S
g
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3)Equivalent Output
=25V,f=1MHz,VGS= 0310
V
DS
49
10
VGS=0V,VDS= 0V to 400V33pF
Capacitance
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
Q
Q
Q
Turn-on Delay Time
t
r
g
gs
gd
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD=250V,ID= 1.5 A
RG= 4.7Ω VGS=10V
(Resistive Load see, Figure 3)
Information furnished is believed to be accurate and reliable. However , STMicroelectronics assum es no responsibility for the
consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication su persedes and replaces all in formation
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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