Datasheet STD40NF3LL Datasheet (SGS Thomson Microelectronics)



STD40NF3LL

N-CHANNEL 30V - 0.0095

LOW GATE CHARGE STripFET POWER MOSFET

TYPE V

ST D40N F 3LL 30 V < 0.0115 Ω 40 A

■ TYPICALR

■ OPTIMAL R

■ CONDUCTION LOSSESREDUCED

■ SWITCHINGLOSSESREDUCED

DS(on)

DSS

= 0.0115 Ω @ 4.5V

DS(on)xQg

DESCRIPTION

This applicationspecific Power Mosfet is thethird
generation of STMicroelectronics unique ”Single
Feature Size” strip-based process. The resul­ting transistor shows the best trade-off between
on-resistance and gate charge. When used as
high and low side in buck regulators, it gives the
best performancein termsof both conductionand
switching losses. This is extremely important for
motherboardswhere fast switching and high effi­ciencyare of paramount importance.

APPLICATIONS

■ SPECIFICALLYDESIGNED AND

OPTIMISEDFOR HIGH EFFICIENCYCPU
CORE DC/DC CONVERTERS

R

DS(on)

I

D

TRADE-OFF@ 4.5V

Ω

- 40A DPAK

PRELIMINARY DATA

3

1

DPAK

TO-252

(Suffix ”T4”)

ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

DM

P

T

(•) Pulse widthlimited by safe operating area

May 2000

Dra in- sour c e V ol t age (VGS=0) 30 V

DS

Dra in- gate Vol t age (RGS=20kΩ)30V

DGR

Gat e-sourc e Volt age

GS

I

Dra in Curr ent (c ont in uous ) at Tc=25oC40A

D

I

Dra in Curr ent (c ont in uous ) at Tc=100oC28A

D

(•) Dra in Curr ent (puls ed ) 160 A

Tot al Diss ipation at Tc=25oC55W

tot

Der ati ng F ac t or 0.37 W/
St orage T emperature -65 to 175

stg

T

Max. Oper at ing J unction Tem peratur e 175

j

15 V

±

o

C

o

C

o

C

1/6

STD40NF3LL

THERMAL DATA

R

thj-case

R

thj-amb

T

Ther mal Resistanc e Junct ion-case Max
Ther mal Resistanc e Junct ion-ambie nt Max
Maximum L ead Tempe rat ur e For Soldering Purp os e

l

2.73

62.5
300

o

C/W

o

C/W

o

C

ELECTRICAL CHARACTERISTICS

=25oC unless otherwisespecified)

(T

case

OFF

Symbol Parameter Test Conditions Min. Typ. Max. U nit

V

(BR)DSS

Drain-source

ID=250µAVGS=0 30 V

Break dow n Volt age

I

DSS

I

GSS

Zero Gate Voltage
Drain Current (V

GS

Gat e- bod y L eak ag e
Current (V

DS

=0)

=0)

V

=MaxRating

DS

=MaxRating Tc=125oC

V

DS

V

= ± 20 V ± 100 nA

GS

1

10

ON(∗)

Symbol Parameter Test Conditions Min. Typ. Max. U nit

V

GS(th)

R

DS(on)

I

D(on)

Gate Threshold Voltage VDS=VGSID= 250 µ A12.5V
Sta t ic Drain -s ource On

Resistance
On State Drain Current VDS>I

VGS=10V ID=20A
V

=4.5V ID=10A

GS

D(on)xRDS(on)max

0.0095

0.0115

0.0115

0.0135

40 A

VGS=10V

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. U nit

g

(∗)Forward

fs

Tr ansc on duc tance

C

C

C

Input C apaci t anc e

iss

Out put Capacit anc e

oss

Reverse Tr ansfer

rss

Capacit a nc e

VDS>I

D(on)xRDS(on)maxID

=20 A 40 S

VDS=25V f=1MHz VGS= 0 1700

500
115

µA
µ

Ω
Ω

pF
pF
pF

A

2/6

STD40NF3LL

ELECTRICAL CHARACTERISTICS

(continued)

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. U nit

t

d(on)

t

Tur n-on Delay T ime
Rise Ti m e

r

VDD=15V ID=20A
R

=4.7

G

Ω

VGS=4.5V

20

170

(Resis t iv e Loa d, see fig. 3)

Q
Q
Q

Tot al G ate Charge

g

Gat e- Source Charge

gs

Gate-Drain Charge

gd

VDD=24V ID=40A VGS=10V 43

10
10

56 nC

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. U nit

t

d(off)

Tur n-of f D ela y Tim e

t

Fall T ime

f

VDD=15V ID=20A

=4.7 Ω VGS=4.5V

R

G

40
60

(Resis t iv e Loa d, see fig. 3)

SOURCEDRAINDIODE

Symbol Parameter Test Conditions Min. Typ. Max. U nit

I

SD

I

SDM

V

SD

t

Q

I

RRM

(∗) Pulsed:Pulse duration= 300µs, duty cycle 1.5%
(•) Pulse width limited by safe operatingarea

Source-drain Current

(•)

Source-drain Current

40

160

(pulsed)

(∗)ForwardOnVoltage ISD=40 A VGS=0 1.5 V

Reverse Recover y

rr

Time
Reverse Recover y

rr

ISD= 40 A di/dt = 100 A/µ s

=15V Tj=150oC

V

DD

(see test circuit, fig. 5)

40

52
Charge
Reverse Recover y

2.4

Current

ns
ns

nC
nC

ns
ns

A
A

ns

nC

A

3/6

STD40NF3LL

Fig. 1:

UnclampedInductiveLoad Test Circuit

Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad

Fig. 2:

UnclampedInductive Waveform

Fig. 4: Gate Chargetest Circuit

Fig. 5:

Test CircuitFor InductiveLoad Switching

And Diode Recovery Times

4/6

TO-252 (DPAK) MECHANICAL DATA

STD40NF3LL

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009

B 0.64 0.9 0.025 0.035
B2 5.2 5.4 0.204 0.212

C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L2 0.8 0.031
L4 0.6 1 0.023 0.039

H

A

E

C2

L2

B2

==

==

DETAIL”A”

D

2

13

L4

A1

C

A2

DETAIL”A”

B

G

==

0068772-B

5/6

STD40NF3LL

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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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