Datasheet std40nf06lz Datasheet

Page 1
STD40NF06LZ
N-CHANNEL 60V - 0.020 Ω - 40A DPAK
Zener-Protected STripFET™ II POWER MOSFET
TYPE
V
DSS
STD40NF06LZ 60 V < 25 m
■ TYPICAL R
■ LOW GATE CHARGE
■ LOGIC LEVEL GATE DRIVE
■ SURFACE-MOUNTING DPAK (TO-252)
(on) = 0.020Ω
DS
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
■ BUILT-I N Z EN ER DIODES T O IMPROVE ESD
R
DS(on)
I
D
40 A
Ω
3
1
DPAK
TO-252
(Suffix “T4”)
PROTECTION UP TO 2kV
DESCRIPTION
This Power MOSFET is the latest dev elo pment of STMicroelectronis unique "Single Feature Size™"
INTERNAL SCHEMATIC DIAGRAM
strip-based process. The resulting transistor shows extremely high packing density for low on­resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ SINGLE-ENDED SMPS IN MONITOTS,
COMPUTER AND INDUSTRIAL APPLICATION
■ WELDING EQUIPMENT
■ AUTOMOTIVE
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
(
I
DM
P
tot
V
ESD(G-S)
dv/dt
E
AS
T
stg
T
j
(
Pulse widt h l i m i ted by safe o perating area.
•)
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ)
60 V 60 V
Gate- source Voltage ± 16 V
Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C
•)
Drain Current (pulsed) 160 A Total Dissipation at TC = 25°C
40 A 28 A
100 W Derating Factor 0.67 W/°C Gate-source ESD(HBM-C=100pF, R=15k
(1)
Peak Diode Recovery voltage slope 9 V/ns
(2)
Single Pulse Avalanche Energy 450 mJ
Ω)
Storage Temperature Max. Operating Junction Temperature
(1)
ISD ≤40A, di/dt ≤100A/µs , VDD ≤ V
(2)
Starting Tj = 25 oC ID = 20A VDD = 45V
± 2.5 kV
-55 to 175 °C
(BR)DSS
, Tj ≤ T
JMAX
.
1/8October 2002
.
Page 2
STD40NF06LZ
THERMA L D ATA
Rthj-case
Rthj-
PCB
T
l
(#) When M ounted on 1 inch
ELECTRICAL CHARACTERISTICS (T
Thermal Resistance Junction-case Thermal Resistance Junction-PCB (#) Maximum Lead Temperature For Soldering Purpose
2
FR-4 boar d, 2 oz Cu.
= 25 °C unless otherwise specified)
case
Max Max
1.5 50
300
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
Drain-source Breakdown Voltage
Zero Gate Voltage Drain Current (V
GS
Gate-body Leakage Current (V
DS
= 0)
= 0)
ON
V
(BR)DSS
I
DSS
I
GSS
(*)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage Static Drain-source On
Resistance
= 250 µA, VGS = 0
D
V
= Max Rating
DS
V
= Max Rating TC = 125°C
DS
= ± 16 V
V
GS
V
= VGS I
DS
= 5 V ID = 20 A
V
GS
V
= 10 V D = 20 A
GS
= 250 µA
D
60 V
1
50
±10 µA
1V
0.030
0.025
°C/W °C/W
°C
µA µA
Ω Ω
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance Input Capacitance
Output Capacitance Reverse Transfer Capacitance
V
= 15 V ID= 20 A
DS
= 25V, f = 1 MHz, VGS = 0
V
DS
25 S
1360
302
115
pF pF pF
2/8
Page 3
STD40NF06LZ
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 30 V ID = 20 A
t
d(on)
Turn-on Delay Time
t
r
Rise Time
V
DD
R
= 4.7 Ω VGS = 4.5 V
G
(Resistive Load, Figure 3)
Q
g
Q
gs
Q
gd
Total Gate Charge Gate-Source Charge Gate-Drain Charge
=48 V ID =40 A VGS=10V
V
DD
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 30V ID = 20 A
t
d(off)
Turn-off Delay Time
t
f
Fall Time
V
DD
R
= 4.7Ω, V
G
GS
= 4.5 V
(Resistive Load, Figure 3)
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %
(
•)Pulse width limited by s afe operating area.
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage Reverse Recovery Time
Reverse Recovery Charge Reverse Recovery Current
I
= 40A VGS = 0
SD
= 40 A di/dt = 100A/µs
I
SD
V
= 30 V Tj = 150°C
DD
(see test circuit, Figure 5)
17 75
54 11 12
38 23
40
160
1.6 V
66
142
4.3
ns ns
nC nC nC
ns ns
A A
ns
nC
A
Safe Operating Area Thermal Impedance
3/8
Page 4
STD40NF06LZ
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
4/8
Page 5
STD40NF06LZ
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature.
. .
. .
5/8
Page 6
STD40NF06LZ
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
Page 7
TO-252 (DPAK) MECHANICAL DATA
STD40NF06LZ
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397 L2 0.8 0.031 L4 0.6 1 0.023 0.039
A
C2
L2
E
B2
==
H
DETAIL "A"
D
==
C
B
2
1 3
L4
A1
G
==
A2
DETAIL "A"
0068772-B
7/8
Page 8
STD40NF06LZ
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise under any patent or patent ri ghts of STM i croelectr oni cs. Specifications mentioned in thi s publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as cri tical comp onents in life support dev i ces or systems wi thout exp res s written ap proval of STMi croelectr o nics.
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