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STD40NE03L
N - CHANNEL 30V - 0.012 Ω - 40A TO-252
STripFET POWER MOSFET
■ TYPICALR
DS(on)
= 0.012 Ω
■ EXCEPTIONALdv/dtCAPABILITY
■ 100%AVALANCHETESTED
■ LOW GATE CHARGE
■ APPLICATIONORIENTED
CHARACTERIZATION
■ ADDSUFFIX ”T4” FORORDERING INTAPE
& REEL
DESCRIPTION
This PowerMOSFET is the latest developmentof
STMicroelectronics unique ”Single Feature
Size” strip-based process. The resulting transi-
stor showsextremelyhigh packing densityfor low
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a remarkablemanufacturingreproducibility.
APPLICATIONS
■ HIGHCURRENT, HIGH SPEED SWITCHING
■ SOLENOIDAND RELAYDRIVERS
■ MOTORCONTROL, AUDIO AMPLIFIERS
■ DC-DC& DC-ACCONVERTERS
INTERNAL SCHEMATIC DIAGRAM
September 1999
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Uni t
V
DS
Dra in- sour c e Volta ge (VGS=0) 30 V
V
DGR
Drain- gate Voltage (RGS=20kΩ)30V
V
GS
Gate-s ource Volt age ± 20 V
I
D
Dra in Cu rr ent (continuous) at Tc=25oC20**A
I
D
Dra in Cu rr ent (continuous) at Tc= 100oC20**A
I
DM
(•) D ra in Cu rr ent (pulsed) 160 A
P
tot
Tot al Dissi pat io n at Tc=25oC55W
Der ati ng Fa c t or 0.37 W/
o
C
dv/dt (
1) P eak Diode Rec o ve ry volt a ge slope 7 V/ ns
T
stg
St orage Tem pe ra t ure -65 to 175
o
C
T
j
Max. Operating Junction Tem pe ra t ure 175
o
C
(•) Pulse width limitedby safe operatingarea (1)ISD≤20A, di/dt ≤ 300 A/µs, VDD≤ V
(BR)DSS
,Tj≤T
JMAX
(**) Valuelimitedonly by the package
TYPE V
DSS
R
DS(o n)
I
D
ST D40N E 03L 30 V < 0.016 Ω 40 A
1
3
DPAK
TO-252
(Suffix ”T4”)
1/8
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THERMAL DATA
R
thj-pcb
R
thj-amb
R
thj-sink
T
l
Ther mal Resistanc e Junct ion-PC Boa rd Max
Ther mal Resistanc e Junct ion-ambient Max
Ther mal Resistanc e Case-sink Ty p
Maximum Lead Temperatur e For Soldering Pu rpose
2.7
100
1.5
275
o
C/W
o
C/W
o
C/W
o
C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Valu e Unit
I
AR
Avalanche Current, Repe titive or Not-Repetitive
(pulse width limited by T
j
max)
40 A
E
AS
Single Pul se Avalanche Ener gy
(starting T
j
=25oC, ID=IAR,VDD=15V)
100 mJ
ELECTRICAL CHARACTERISTICS
(T
case
=25oC unless otherwisespecified)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. U nit
V
(BR)DSS
Drain-source
Break dow n Vo lt age
ID=250µAVGS=0 30 V
I
DSS
Zero Gate Voltage
Drain Curre nt (V
GS
=0)
V
DS
=MaxRating
V
DS
=MaxRating Tc= 125oC
1
10
µ
A
µA
I
GSS
Gat e- bod y Leakag e
Current (V
DS
=0)
V
GS
=± 20 V
±
100 nA
ON(∗)
Symbol Parameter Test Conditions Min. Typ. Max. U nit
V
GS(th)
Gate Threshold Volt age VDS=VGSID= 250 µ A11.72.5V
R
DS(on)
Sta t ic Drain-s our c e On
Resistance
VGS=10V ID=20A
V
GS
=5V ID=20A
0.012 0.016
0.022ΩΩ
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on )max
VGS=10V
40 A
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. U nit
g
fs
(∗)Forward
Tr ansc on duc tance
VDS>I
D(on)xRDS(on )maxID
= 2 0 A 15 28 S
C
iss
C
oss
C
rss
Input Capaci t ance
Out put Capac itance
Reverse Transfer
Capacit a nc e
VDS=25V f=1MHz VGS= 0 V 2200
570
200
pF
pF
pF
STD40NE03L
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ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. U nit
t
d(on)
t
r
Tur n-on Delay Time
Rise Time
VDD=15V ID=30A
R
G
=4.7
Ω
VGS=5V
(Resis t iv e Load, see fig. 3)
38
260
ns
ns
Q
g
Q
gs
Q
gd
Tot al Gate Charge
Gat e- Source Char g e
Gate-Drain Charge
VDD=24V ID=64A VGS=5V 35
18
13
45 nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. U nit
t
d(off)
t
f
Tur n-of f Dela y Tim e
Fall T ime
VDD=15V ID=30A
R
G
=4.7 Ω VGS=5V
(Resis t iv e Load, see fig. 3)
75
50
ns
ns
t
r(Voff)
t
f
t
c
Off-volt age Rise Time
Fall T ime
Cross-over Tim e
VDD=24V ID=64A
R
G
=4.7 Ω VGS=5V
(Indu ct iv e Load, see fig . 5)
35
120
175
ns
ns
ns
SOURCEDRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. U nit
I
SD
I
SDM
(•)
Source-drain Current
Source-drain Current
(pulsed)
40
160
A
A
V
SD
(∗)ForwardOnVoltage ISD=40A VGS=0 1.5 V
t
rr
Q
rr
I
RRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD= 64 A di/dt = 100 A/µs
V
DD
=15V Tj=150oC
(see test circuit, fig. 5)
55
0.1
3.5
ns
µC
A
(∗) Pulsed: Pulse duration= 300µs, dutycycle 1.5 %
(•) Pulse width limited by safeoperating area
SafeOperating Area ThermalImpedance
STD40NE03L
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OutputCharacteristics
Transconductance
Gate Charge vs Gate-sourceVoltage
TransferCharacteristics
Static Drain-sourceOn Resistance
CapacitanceVariations
STD40NE03L
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Page 5
NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
STD40NE03L
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Page 6
Fig. 1:
UnclampedInductiveLoad TestCircuit
Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad
Fig. 2:
UnclampedInductiveWaveform
Fig. 4: Gate Charge test Circuit
Fig. 5:
Test Circuit For InductiveLoad Switching
And Diode Recovery Times
STD40NE03L
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DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L2 0.8 0.031
L4 0.6 1 0.023 0.039
==
D
L2
L4
13
==
B
E
==
B2
G
2
A
C2
C
H
A1
DETAIL”A”
A2
DETAIL”A”
TO-252 (DPAK) MECHANICALDATA
0068772-B
STD40NE03L
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Information furnished is believed tobeaccurateand reliable. However, STMicroelectronics assumesno responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publicationare
subjecttochange without notice.Thispublication supersedesand replacesall information previouslysupplied.STMicroelectronics products
are not authorizedfor useas critical components in lifesupport devices or systems without express written approval of STMicroelectronics.
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1999STMicroelectronics – Printed in Italy – All Rights Reserved
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STD40NE03L
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