The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal
layout. Theresulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar completition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increase
the power density of high voltage converters allowing system miniaturization and higher efficiencies.
3
DPAK
TO-252
1
IP AK
TO-251
1
INTERNAL SCHEMATIC DIAGRAM
3
2
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
DS
V
DGR
V
GS
I
D
I
D
IDM(●)
P
TOT
V
ESD(G-S)
dv/dt(1)Peak Diode Recovery voltage slope15V/ns
T
stg
T
j
(•)Pulse width limited by safe operating area
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
Gate- source Voltage±30V
Drain Current (continuous) at TC= 25°C
Drain Current (continuous) at TC= 100°C
Drain Current (pulsed)12A
T ot al Dissipation at TC= 25°C
Gate source ESD(HBM-C=100pF , R=15KΩ)4KV
Derating Factor0.37W/°C
Storage Temperature–65 to 150°C
Max. Operating Junction Temperature150°C
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge790nC
Reverse Recovery Current7.5A
Reverse Recovery Time
Reverse Recovery Charge1.1µC
Reverse Recovery Current7.7A
=250V,ID= 1.5A
V
DD
RG= 4.7Ω VGS=10V
(see test circuit, Figure 3)
V
=400V,ID= 3A,
DD
V
=10V
GS
V
= 480V, ID=3A,
DD
RG=4.7Ω, VGS= 10V
(see test circuit, Figure 5)
ISD= 3A, VGS=0
I
= 3A, di/dt = 100A/µs,
SD
V
=100V,Tj=25°C
DD
(see test circuit, Figure 5)
I
= 3A, di/dt = 100A/µs,
SD
V
=100V,Tj=150°C
DD
(see test circuit, Figure 5)
7ns
10ns
5.5nC
8ns
1.5V
210ns
282ns
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back -to-back Zener diodes have spec ifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective interven tio n to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
3/10
Page 4
STD3NM50/STD3NM50-1
Safe Operating Area For DPAK / IPAKThermal Impedance For DPAK / IPAK
Output Characteristics
Transfer Characteristics
Static Drain-source On ResistanceTransconductance
4/10
Page 5
STD3NM50/STD3NM50-1
Capacitance VariationsGate Charge vs Gate-so urc e V oltage
Normalized Gate Threshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Normalized BVdss vs TemperatureSource-drain Diode Forward Characteristics
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of u se of such inf ormat ion nor for any in fring ement of p aten ts or othe r ri ghts of th ird p arties whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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