Page 1
STD25NF10L
N-CHANNEL 100V - 0.030 Ω - 25A DPAK
LOW GATE CHARGE STripFET™ II POWER MOSFET
TYPE
V
DSS
STD25NF10L 100 V < 0.035
■ TYPICAL R
■ EXCEPTIONA L dv/d t CAPABILITY
■ 100% AVALANCHE TESTED
■ LOW THRESHOLD DEVICE
■ LOGIC LEVEL DEVICE
■ SURFACE-MOUNTING DPAK (TO-252)
(on) = 0.030 Ω
DS
R
DS(on)
I
D
25 A
Ω
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
DESCRIPTION
This MOSFET series realized with STMicroelectronics
unique STripFET process has specifically been designed
to minimize input capacitance and gate charge. It is
therefore suitable as primary switch in advanced highefficiency, high-frequency isolate d DC-DC c onverters for
Telecom and Computer applica tions. It is also intended
for any applications with low gate drive requirements
APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
3
1
DPAK
TO-252
(Suffix “T4”)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
(*) Drain Current (continuous) at TC = 25°C
I
D
I
D
(
I
DM
P
tot
dv/dt
E
AS
T
stg
T
j
Pulse wi dth limited by safe operating area.
(•)
(*) Current Limited by Package
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
100 V
100 V
Gate- source Voltage ± 16 V
25 A
Drain Current (continuous) at TC = 100°C
•)
Drain Current (pulsed) 100 A
Total Dissipation at TC = 25°C
25 A
100 W
Derating Factor 0.67 W/°C
(1)
Peak Diode Recovery voltage slope 20 V/ns
(2)
Single Pulse Avalanche Energy 450 mJ
Storage Temperature
Max. Operating Junction Temperature
(1) ISD ≤25A, di/dt ≤300A/ µ s , VDD ≤ V
(2) Starting Tj = 25 oC, ID = 12.5A, VDD = 50V
-55 to 175 °C
(BR)DSS
, Tj ≤ T
JMAX
1/9February 2003
Page 2
STD25NF10L
THERMA L D ATA
Rthj-case
Rthj-pcb
T
(#)
When Mounted on 1 inch2 FR-4 board, 2 oz of Cu.
Thermal Resistance Junction-case
Thermal Resistance Junction-pcb
Maximum Lead Temperature For Soldering Purpose
l
(#)
Max
Max
1.5
50
275
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 250 µA, VGS = 0
V
(BR)DSS
Drain-source
I
D
100 V
Breakdown Voltage
= Max Rating
V
DS
V
= Max Rating TC = 125°C
DS
= ± 16 V
V
GS
1
10
±100 nA
ON
(*)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
= VGS I
DS
= 10 V ID = 12.5 A
V
GS
V
= 4.5 V ID = 12.5 A
GS
= 250 µA
D
1 2.5 V
0.030
0.035
0.035
0.040
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 15 V ID= 12.5 A
DS
= 25V f = 1 MHz VGS = 0
V
DS
24 S
1710
250
110
µA
µA
Ω
Ω
pF
pF
pF
2/9
Page 3
STD25NF10L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 50 V ID = 12.5 A
t
d(on)
Turn-on Delay Time
t
r
Rise Time
V
DD
R
= 4.7 Ω VGS = 5 V
G
(Resistive Load, Figure 3)
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 80 V ID= 25 A VGS= 5 V
V
DD
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 50 V ID = 12.5 A
t
d(off)
Turn-off Delay Time
t
f
Fall Time
V
DD
R
= 4.7Ω, V
G
GS
= 5 V
(Resistive Load, Figure 3)
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: P ul se duration = 300 µs, duty c yc l e 1.5 %.
(
Pulse widt h l i m i ted by safe operating area.
•)
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
= 25 A VGS = 0
SD
= 25 A di/dt = 100A/µs
I
SD
V
= 50 V Tj = 150°C
DD
(see test circuit, Figure 5)
20
40
38
8.5
21
58
20
88
317
7.2
52 nC
25
100
1.5 V
ns
ns
nC
nC
ns
ns
A
A
ns
nC
A
Safe Operating Area Thermal Impedance
3/9
Page 4
STD25NF10L
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
4/9
Page 5
STD25NF10L
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature
. .
5/9
Page 6
STD25NF10L
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/9
Page 7
STD25NF10L
TO-252 (DPAK) MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L2 0.8 0.031
L4 0.6 1 0.023 0.039
A
C2
L2
E
B2
==
H
DETAIL "A"
D
==
C
B
2
1 3
L4
A1
G
==
A2
DETAIL "A"
0068772-B
7/9
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STD25NF10L
8/9
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STD25NF10L
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9/9
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