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STB75NE75
N - CHANNEL 75V - 0.01 Ω - 75A - D2PAK
STripFET POWER MOSFET
■ TYPICALR
DS(on)
= 0.01 Ω
■ EXCEPTIONALdv/dtCAPABILITY
■ 100%AVALANCHETESTED
■ APPLICATIONORIENTED
CHARACTERIZATION
■ FORTHROUGH-HOLE VERSION CONTACT
SALESOFFICE
■ ADDSUFFIX ”T4” FORORDERING IN TAPE
& REEL
DESCRIPTION
This Power MOSFET is the latest developmentof
STMicroelectronics unique ”Single Feature
Size” strip-based process. The resulting transi-
stor shows extremely high packing density for low
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a remarkablemanufacturingreproducibility.
APPLICATIONS
■ SOLENOIDAND RELAY DRIVERS
■ DC MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DCCONVERTERS
■ AUTOMOTIVEENVIRONMENT
INTERNAL SCHEMATIC DIAGRAM
March 1999
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
Dra in- sour c e Vol t age (VGS=0) 75 V
V
DGR
Dra in- gate Vol t age (RGS=20kΩ)75V
V
GS
Gat e-sourc e Voltage ± 20 V
I
D
Dra in Current (contin uous ) at Tc=25oC75A
I
D
Dra in Current (contin uous ) at Tc=100oC53A
I
DM
(•) D rain Current (p ulsed) 300 A
P
tot
Tot al Dis sipation at Tc=25oC 160 W
Der ati ng Factor 1.06 W/
o
C
dv/dt (
1) Peak Diode Recov er y voltage slope 7 V / ns
T
stg
St orage T em pe rat ure -65 to 175
o
C
T
j
Max. Operat ing Junc t ion Temperature 175
o
C
(•) Pulsewidth limited by safe operating area (1)ISD≤ 75 A, di/dt ≤ 300 A/µs, VDD≤ V
(BR)DSS,Tj≤TJMAX
TYPE V
DSS
R
DS(on)
I
D
ST B75NE75 75 V <0. 013 Ω 75 A
1
3
D2PAK
TO-263
(suffix ”T4”)
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THERMAL DATA
R
thj-case
Rthj-a mb
R
thc-sink
T
l
Ther mal Resistanc e Junct ion-case Max
Ther mal Resistanc e Junct ion-ambie nt Max
Ther mal Resistanc e Case-sink Ty p
Maximum L ead T empe rat ur e For Soldering Purpos e
0.94
62.5
0.5
300
o
C/W
o
C/W
o
C/W
o
C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Un it
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
75 A
E
AS
Single Pulse Avalanche Energy
(starting T
j
=25oC, ID=IAR,VDD=30V)
500 mJ
ELECTRICAL CHARACTERISTICS
(T
case
=25oC unless otherwisespecified)
OFF
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Break dow n Voltage
ID=250µAVGS=0 75 V
I
DSS
Zero Gate Voltage
Drain Current ( V
GS
=0)
V
DS
=MaxRating
V
DS
=MaxRating Tc= 125oC
1
10
µ
A
µA
I
GSS
Gat e- bod y Leakage
Current (V
DS
=0)
V
GS
=± 20 V
±
100 nA
ON(∗)
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
V
GS(th)
Gate Threshold Voltage VDS=VGSID= 250 µA 234V
R
DS(on)
Sta t ic Dr ain -s ource On
Resistance
VGS=5V ID= 37.5 A 10 13 m
Ω
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
VGS=10V
75 A
DYNAMIC
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
g
fs
(∗)Forward
Tr ansc on duc tance
VDS>I
D(on)xRDS(on)maxID
=37. 5 A 40 S
C
iss
C
oss
C
rss
Input C apac i t ance
Out put Capacitance
Reverse T r ansfer
Capacit a nc e
VDS=25V f=1MHz VGS= 0 5300
850
310
pF
pF
pF
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ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
t
d(on)
t
r
Tur n-on Delay T im e
Rise T i me
VDD=40V ID=40A
R
G
=4.7
Ω
VGS=10V
(Resis t iv e Load, s ee f ig. 3)
32
130
ns
ns
Q
g
Q
gs
Q
gd
Tot al G at e Char ge
Gat e- Source Charge
Gate-Drain Charge
VDD=60V ID=75A VGS= 10 V 150
30
62
200 nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
t
d(off)
t
f
Tur n-of f Delay Time
Fall T ime
VDD=40V ID=40A
R
G
=4.7 Ω VGS=10V
(Resis t iv e Load, s ee f ig. 3)
150
45
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall T ime
Cross-over Time
V
clamp
=60V ID=75A
R
G
=4.7 Ω VGS=4.5V
(Indu ct iv e L oad , see fig. 5)
35
60
100
ns
ns
ns
SOURCEDRAINDIODE
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
I
SD
I
SDM
(•)
Source-drain Current
Source-drain Current
(pulsed)
75
300
A
A
V
SD
(∗)ForwardOnVoltage ISD=75A VGS=0 1.5 V
t
rr
Q
rr
I
RRM
Reverse Re covery
Time
Reverse Re covery
Charge
Reverse Re covery
Current
ISD= 75 A di/dt = 100 A/µs
V
DD
=30V Tj=150oC
(see test circuit, fig. 5)
130
0.6
9
ns
µC
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
SafeOperating Area ThermalImpedance
STB75NE75
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OutputCharacteristics
Transconductance
Gate Charge vs Gate-sourceVoltage
TransferCharacteristics
Static Drain-sourceOn Resistance
CapacitanceVariations
STB75NE75
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NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
STB75NE75
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Fig. 1:
UnclampedInductiveLoad Test Circuit
Fig. 3: Switching Times Test CircuitsFor
ResistiveLoad
Fig. 2:
UnclampedInductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5:
Test CircuitFor InductiveLoad Switching
And Diode Recovery Times
STB75NE75
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DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098 0.106
B 0.7 0.93 0.027 0.036
B2 1.14 1.7 0.044 0.067
C 0.45 0.6 0.017 0.023
C2 1.21 1.36 0.047 0.053
D 8.95 9.35 0.352 0.368
E 10 10.4 0.393 0.409
G 4.88 5.28 0.192 0.208
L 15 15.85 0.590 0.624
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.068
L2
L3
L
B2
B
G
E
A
C2
D
C
A1
DETAIL”A”
DETAIL”A”
A2
P011P6/E
TO-263 (D2PAK) MECHANICAL DATA
STB75NE75
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subjecttochange without notice. This publication supersedes and replaces all information previouslysupplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systemswithout express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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STB75NE75
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