Datasheet STB70NF03L-1 Datasheet (SGS Thomson Microelectronics)

STP70NF03L

STB70NF03L-1

N-CHANNEL 30V - 0.008Ω - 70A TO -220/I2PAK

LOW GATE CHARGE STripFET™ POWER MOSFET

TYPE V

STP70NF03L
STB70NF03L-1

■ TYPICAL R

■ TYPICAL Q

■ OPTIMAL R

■ CONDUCTION LOSSES REDUCED

■ SWITCHING LOSSES REDUCED

DS
g

DS

DSS

30 V
30 V

(on) = 0.008 Ω

= 35 nC @ 10 V

(on) x Qg TRADE-OFF

R

DS(on)

< 0.01
< 0.01

I

D

Ω

70 A

Ω

70 A

DESCRIPTION

This application specific Powe r M osfet i s the t hird

generation of STMicroelectronics unique “Single
Feature Size

™” strip-based process. The resul t-

ing transistor shows the best trade-off between on­resistance and gate charge. When used as high
and low side in buck regulators, it gives the best
performance in terms of both conduction and
switching losses. This is e xtremely important for
motherboards where fast switching and high e ffi­ciency are of paramount importance.

APPLICATIONS

■ SPECIFICALL Y D ESIGNED AND OP TIMISED

FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS

3

TO-220

2

1

I2PAK

1

INTERNAL SCHEMATIC DIAGRAM

3

2

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

TOT

dv/dt (1) Peak Diode Recovery voltage slope 4 V/ns

T

stg

T

j

(●) Pulse width limited by safe operating area

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ± 15 V

Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C

(●)

Drain Current (pulsed) 280 A
Total Dissipation at TC = 25°C
Derating Factor 0.67 W/°C

Storage Temperature –65 to 175 °C
Max. Operating Junction Temperature 175 °C

(1) ISD ≤70A, di/dt ≤290A/µs, VDD =24 V ; Tj ≤ T

30 V
30 V

70 A
50 A

100 W

JMAX.

1/9March 2001

STP70NF03L/STB70NF03L-1

THERMA L D ATA

Rthj-case Thermal Resistance Junction-case Max 1.5 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W

T

l

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

I

AR

E

AS

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

Maximum Lead Temperature For Soldering Purpose 300 °C

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

Drain-source

= 25 °C, ID = IAR, VDD = 50 V)

j

ID = 250 µA, VGS = 0 30 V

35 A

450 mJ

Breakdown Voltage
Zero Gate Voltage

Drain Current (V

GS

Gate-body Leakage
Current (V

DS

= 0)

= 0)

V

= Max Rating

DS

V

= Max Rating, TC = 125 °C

DS

V

= ± 15V ±100 nA

GS

1µA

10 µA

ON

(1)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

V

GS(th)

R

DS(on)

I

D(on)

Gate Threshold Voltage
Static Drain-source On

Resistance
On State Drain Current VDS > I

= VGS, ID = 250µA

DS

VGS = 10 V, ID = 35 A
VGS = 5 V, ID = 18 A

x R

D(on)

DS(on)max,

12 V

0.008 0.01

0.015 0.018

70 A

VGS=10V

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(1) Forward Transconductance VDS > I

g

fs

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 490 pF
Reverse Transfer

Capacitance

ID= 35 A

V

DS

x R

D(on)

DS(on)max,

= 25V, f = 1 MHz, VGS = 0

40 S

1470 pF

110 pF

Ω
Ω

2/9

STP70NF03L/STB70NF03L-1

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

t

d(on)

Q

Q
Q

t

r

g

gs
gd

Turn-on Delay Time
Rise Time 350 ns
Total Gate Charge VDD = 24 V, ID = 46A,

Gate-Source Charge
Gate-Drain Charge 10 nC

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(off)

t

f

Turn-off-Delay Time VDD = 15 V, ID = 35 A,

Fall Time 65 ns

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD (2)

t

rr

Q

rr

I

RRM

Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.

2. Pulse width li mited by safe operating area .

Source-drain Current 70 A

(1)

Source-drain Current (pulsed) 280 A
Forward On Voltage
Reverse Recovery Time ISD = 70 A, di/dt = 100A/µs,

Reverse Recovery Charge 110 nC
Reverse Recovery Current 2.9 A

= 15 V, ID = 35 A

DD

R

= 4.7Ω VGS = 4.5 V

G

(see test circuit, Figure 3)

VGS = 10V

RG=4.7Ω, V

GS

= 4.5V

(see test circuit, Figure 3)

ISD = 70 A, VGS = 0

V

= 20 V, Tj = 150°C

DD

(see test circuit, Figure 5)

20 ns

35 45 nC

5

35 ns

1.5 V

75 ns

nC

Ther m al Imp e denceSafe Operating Area

3/9

STP70NF03L/STB70NF03L-1

Output Characteristics

Transconductance Static Drain-source On Resistance

Transfer Characteristics

Gate Charge vs Gate-source Voltage

4/9

Capacitance Variations

STP70NF03L/STB70NF03L-1

Normalized Gate Threshold Volta ge vs
Temperature

Source-drain Diode Forward Characteristics

Normalized On Resistance vs Temperature

5/9

STP70NF03L/STB70NF03L-1

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit For

Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

6/9

E

TO-220 MECHANICAL DATA

STP70NF03L/STB70NF03L-1

DIM.

A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107

D1 1.27 0.050

E 0.49 0.70 0.019 0.027

F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067

G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154

DIA. 3.75 3.85 0.147 0.151

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A

C

D

L5

Dia.

L7

D1

L6

L2

L9

F1

G1

F

H2

G

F2

L4

P011C

7/9

STP70NF03L/STB70NF03L-1

TO-262 (I2PAK) MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098 0.106

B 0.7 0.93 0.027 0.036
B2 1.14 1.7 0.044 0.067

C 0.45 0.6 0.017 0.023
C2 1.23 1.36 0.048 0.053

D 8.95 9.35 0.352 0.368

e 2.4 2.7 0.094 0.106

E 10 10.4 0.393 0.409

L 13.1 13.6 0.515 0.531
L1 3.48 3.78 0.137 0.149
L2 1.27 1.4 0.050 0.055

mm inch

C

8/9

A

A1

C2

B2

B

e

E

L1

L2

D

L

P011P5/E

STP70NF03L/STB70NF03L-1

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.

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