Using the latest high voltageMESH OVERLAY
process, STMicroelectronics has designed an
advanced familyofpower MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
■ HIGHCURRENT, HIGHSPEEDSWITCHING
■ DC-AC CONVERTERS FOR WELDING
■ EQUIPMENTAND UNINTERRUPTIBLE
POWERSUPPLIESAND MOTORDRIVE
3
1
D2PAK
TO-263
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
DM
P
dv/ dt(
T
(*) Limited only by maximum temperature allowed(1)ISD≤ 5A, di/dt ≤ 200 A/µs,VDD≤ V
March 1999
Drain-source Voltage (VGS=0)800V
DS
Dra in- gat e Voltage (RGS=20kΩ)
DGR
Gate -source Voltage
GS
I
Dra in Cur ren t (continuous ) a t Tc=25oC5A
D
I
Dra in Cur ren t (continuous ) a t Tc= 100oC3.2A
D
800V
30V
±
(•)Dra in Curr en t (puls ed)20A
Tot al Dissipati on at Tc=25oC110W
tot
Der at ing Factor0.88W/
1) Peak Diode Recovery voltag e slope4V / ns
St orage Tem pe ra t ure-65 to 150
stg
T
Max. Op erat i ng J unction Temperature150
j
,Tj≤T
(BR)DSS
JMAX
o
C
o
C
o
C
1/8
Page 2
STB5NB80
THERMAL DATA
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
Ther mal Resis t an ce Junc ti on-cas eMax1.13
Ther mal Resis t an ce Junc ti on-ambien tMax
Thermal Resistance Case-sinkTyp
Maximum Lead Tem per at ure For S old er ing Pur p ose
l
62.5
0.5
300
o
C/W
o
C/W
o
C/W
o
C
SymbolPara meterMi n .
I
AR
E
ELECTRICAL CHARACTERISTICS
Avalanche Curr ent, Repet itiv e or Not-Repetitive
(pulse width limited by T
Single Pu lse Avalanche En ergy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max)
j
(T
case
=25oC unless otherwisespecified)
Value
Max.
Value
5A
300mJ
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-sourc e
=250µAVGS=0
I
D
800V
Break d own Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Cu rr ent (V
GS
Gat e- b ody Leak a ge
Current (V
DS
=0)
=0)
V
=MaxRating
DS
= Max RatingTc=125oC
V
DS
=± 30 V
V
GS
1
50
100nA
±
ON(∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
R
DS(on)
I
D(on)
Gate Threshold
V
DS=VGSID
Voltage
Static Drain-source O n
VGS=10V ID= 2.5 A1.82.2Ω
Resistanc e
On Stat e Dra in Curr ent VDS>I
VGS=10V
= 250µA
D(on)xRDS(on)max
345V
5A
Unit
A
µ
µA
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(∗)Forward
fs
C
iss
C
oss
C
rss
2/8
Tr ansconduc tance
Input Cap acitan ce
Out put Capac it ance
Reverse Transfer
Capacitance
Information furnishedis believedto beaccurate and reliable.However, STMicroelectronics assumesno responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subjecttochange without notice. This publicationsupersedesandreplaces all information previouslysupplied. STMicroelectronicsproducts
are not authorized for use as critical components in life support devicesor systemswithout express written approval of STMicroelectronics.
The STlogo is atrademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada -China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
8/8
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
.
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