Datasheet STB50NH02L Datasheet (SGS Thomson Microelectronics)

STB50NH02L

N-CHANNEL 24V - 0.011 Ω - 50A D²PAK

STripFET™ III POWER MOSFET

TYPE

V

DSS

STB50NH02L 24 V < 0.0135

■ TYPICAL R

■ TYPICAL R

■ R

DS(ON)

■ CONDUCTION LOSSES REDUCED

■ SWITCHING LOSSES REDUCED

■ LOW THRESHOLD DEVICE

■ SURFACE-MOUNTING D

(on) = 0.011 Ω @ 10 V

DS

(on) = 0.015 Ω @ 5 V

DS

* Qg INDUSTRY’s BENCHMARK

R

DS(on)

Ω

2

PAK (TO-263)

I

D

50 A

POWER PACKAG E IN TU BE (NO SU FFIX) OR
IN TAPE & REEL (SUFFIX “T4”)

DESCRIPTION

The STB50NH02L utilizes the latest advanced design

rules of ST’s proprieta ry STripFET™ technology. This is
suitable fot the most demanding DC-DC converter
applications where high efficiency is to be achieved.

APPLICATIONS

■ SPECIFICALL Y D ESIGNED AND OPTIMISED

FOR HIGH EFFICIENCY DC/DC
CONVERTERS

3

1

D²PAK

TO-263

(Suffix “T4”)

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

spike(1)

V

V

V

I

DM

P

E

AS

T

DS

DGR

GS

I

D

I

D

(2)

tot

stg

T

j

Drain-source Voltage Rating 30 V
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)

24 V

24 V
Gate- source Voltage ± 20 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C

50 A

36 A
Drain Current (pulsed) 200 A
Total Dissipation at TC = 25°C

60 W
Derating Factor 0.4 W/°C

(3)

Single Pulse Avalanche Energy 200 mJ
Storage Temperature
Max. Operating Junction Temperature

-55 to 175 °C

1/11September 2003

STB50NH02L

THERMA L D ATA

Rthj-case

Rthj-amb

T

Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose

l

Max
Max

2.5

62.5
300

°C/W
°C/W

°C

ELECTRICAL CHARACTERISTICS (T

= 25 °C UNLESS OTHERWISE SPECIFIED)

CASE

OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

= 25 mA, VGS = 0

V

(BR)DSS

Drain-source

I

D

24 V

Breakdown Voltage

= 20 V

V

DS

V

= 20 V TC = 125°C

DS

V

= ± 20 V

GS

1

10

±100 nA

ON

(4)

I

DSS

I

GSS

Zero Gate Voltage
Drain Current (V

GS

Gate-body Leakage
Current (V

DS

= 0)

= 0)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

V

GS(th)

R

DS(on)

Gate Threshold Voltage
Static Drain-source On

Resistance

= VGS I

DS

= 10 V ID = 25 A

V

GS

V

= 5 V ID = 12.5 A

GS

= 250 µA

D

1 1.8 V

0.011

0.015

0.0135

0.025

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(4)

g

fs

C

iss

C

oss

C

rss

Forward Transconductance
Input Capacitance

Output Capacitance
Reverse Transfer
Capacitance

V

= 10 V ID= 19 A

DS

= 15V f = 1 MHz VGS = 0

V

DS

19 S

1070

305

45

µA
µA

Ω
Ω

pF
pF
pF

2/11

R

G

Gate Input Resistance

f=1 MHz Gate DC Bias=0
Test Signal Level =20 mV

1

Ω

Open Drain

STB50NH02L

ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

= 10 V ID =25 A

t

d(on)

t

Turn-on Delay Time

r

Rise Time

V

DD

R

= 4.7 Ω VGS = 4.5 V

G

(Resistive Load, Figure 3)

Q

Q

gs

Q

gd

Q

oss

Total Gate Charge

g

Gate-Source Charge
Gate-Drain Charge

(5)

Output Charge

≤ V

0.44
I

=50 A VGS=10 V

D

V

DS

≤10 V

DD

= 16 V VGS= 0 V

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

= 10 V ID = 25 A

t

d(off)

t

Turn-off Delay Time

f

Fall Time

V

DD

R

= 4.7Ω, V

G

GS

= 10 V

(Resistive Load, Figure 3)

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

7

62

18

24 nC

4

2.5

6.5 nC

25
12 16

ns
ns

nC
nC

ns
ns

I

SD

I

SDM

V

SD

t

rr

Q

rr

I

RRM

(1)

Garanted wh en external Rg=4.7 Ω and tf < t

(2)

Pulse width limited by safe operating area

3

(

) Starting Tj = 25 oC, ID = 25A, VDD = 18V

Source-drain Current
Source-drain Current (pulsed)

(4)

Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

fmax

I

= 25 A VGS = 0

SD

= 50 A di/dt = 100A/µs

I

SD

V

= 18 V Tj = 150°C

DD

(see test circuit, Figure 5)

.

(4)
(5)

Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %.

Q

oss = Coss

*∆ V

in , Coss = Cgd + Cds .

Safe Operating Area Thermal Impedance

200

1.3 V

27
22

1.6

See Appendix A

50

A
A

ns

nC

A

3/11

STB50NH02L

Output Characteristics Transfer Characteristics

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

4/11

STB50NH02L

Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature

Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature

. .

5/11

STB50NH02L

Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Resistive

Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

6/11

STB50NH02L

D2PAK MECHANICAL DATA

DIM.

A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098
A2 0.03 0.23 0.001 0.009

B 0.7 0.93 0.028 0.037
B2 1.14 1.7 0.045 0.067

C 0.45 0.6 0.018 0.024
C2 1.21 1.36 0.048 0.054

D 8.95 9.35 0.352 0.368
D1 8 0.315

E 10 10.4 0.394 0.409
E1 8.5 0.334

G 4.88 5.28 0.192 0.208

L 15 15.85 0.591 0.624
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.069

M 2.4 3.2 0.094 0.126

R 0.4 0.015

V2 0° 4° 0° 4°

MIN. TYP. MAX. MIN. TYP. TYP.

mm. inch.

0.106

7/11

STB50NH02L

D2PAK FOOTPRINT

TAPE AND REEL SHIPMENT (suffix ”T4”)*

TUBE SHIPMENT (no suffix)*

REEL MECHANICAL DATA

DIM.

A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0.795
G 24.4 26.4 0.960 1.039
N 100 3.937

T 30.4 1.197

mm inch

MIN. MAX. MIN. MAX.

TAPE MECHANICAL DATA

DIM.

A0 10.5 10.7 0.413 0.421
B0 15.7 15.9 0.618 0.626

D 1.5 1.6 0.059 0.063

D1 1.59 1.61 0.062 0.063

E 1.65 1.85 0.065 0.073

F 11.4 11.6 0.449 0.456
K0 4.8 5.0 0.189 0.197
P0 3.9 4.1 0.153 0.161
P1 11.9 12.1 0.468 0.476
P2 1.9 2.1 0075 0.082

R50 1.574

T0.25 0.35 .0.0098 0.0137

W 23.7 24.3 0.933 0.956

mm inch

MIN. MAX. MIN. MAX.

* on sales type

8/11

BASE QTY BULK QTY

1000 1000

STB50NH02L

APPENDIX A

Buck Converter: Power Losses Estimation

SW1

SW2

The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.

SW2

The low side (

• Very low R

• Small Q

• Small C

• Small Q

• The C

voltage to avoid the cross conduction phenomenon;

The high side (

• Small R

feedback on the gate

• Small Q

• Low R

) device requires:

to reduce conduction losses

DS(on)

to reduce the gate charge losses

gls

to reduce losses due to output capacitance

oss

to reduce losses on SW1 during its turn-on

rr

ratio lower than Vth/Vgg ratio especially with low drain to source

gd/Cgs

SW1)

device requires:

and Ls to allow higher gate current peak and to limit the voltage

g

to have a faster commutation and to reduce gate charge losses

g

to reduce the conduction losses.

DS(on)

9/11

STB50NH02L

High Side Switch (SW1) Low Side Switch (SW2)

conduction

P

P

P

P

P

switching

Recovery Not Applicable

diode

Conduction Not Applicable

)gate(Q

G

Qoss

Parameter Meaning

d Duty-cycle

Q

gsth

Q

gls

Pconduction
Pswitching
Pdiode

Pgate

Qoss

P

Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses

Gate drive losses
Output capacitance losses

2

d*I *R

LDS(on)SW1

I

+

gd(SW1)gsth(SW1)in

f*V*Q

ggg(SW1)

f*Q*V

oss(SW1)in

2

L

*f*)Q(Q*V

I

g

Zero Voltage Switching

1

2

d−

f*Q*V

deadtimeLf(SW2)

f*V*Q

gggls(SW2)

f*Q*V

)1(*I *R

f*t*I*V

LDS(on)SW2

rr(SW2)in

oss(SW2)in

2

10/11

1

Dissipated by SW1 during turn - on

STB50NH02L

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11/11