STB4NC50
N-CH A NNEL 500V - 2.2Ω - 4A D2PAK
PowerMesh™II MOSFET
TYPE V
DSS
STB4NC50 500V < 2.7
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ 100% AVALANCHE TESTED
■ NEW HIGH VOLTAGE BENCHMARK
■ GATE CHARGE MINIMIZED
(on) = 2.2 Ω
DS
R
DS(on)
I
D
Ω
4 A
DESCRIPTION
The PowerMESH
generation of MESH OVERLAY
™II is the evolution of the first
™. The layout re-
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lea ding edge for what concerns swithing speed, gate
charge and ruggedness.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLI ES ( SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVERS
3
1
D²PAK
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt(1) Peak Diode Recovery voltage slope 3.5 V/ns
T
stg
T
(•)Pu l se width limited by safe operati ng area
≤4A, di/dt ≤300A/µs, VDD ≤ V
(1)I
SD
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
500 V
500 V
Gate- source Voltage ±30 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(●)
Drain Current (pulsed) 12 A
Total Dissipation at TC = 25°C
4A
2.5 A
80 W
Derating Factor 0.64 W/°C
Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C
j
, Tj ≤ T
(BR)DSS
JMAX.
1/8July 2000
STB4NC50
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 1.56 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
Gate-body Leakage
Current (V
= 25 °C, ID = IAR, VDD = 50 V)
j
= 250 µA, VGS = 0
I
D
= Max Rating
V
DS
= 0)
DS
GS
= 0)
V
= Max Rating, TC = 125 °C
DS
= ±30V
V
GS
500 V
10 A
110 mJ
1µA
50 µA
±100 nA
ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
I
D(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
On State Drain Current
= VGS, ID = 250µA
DS
= 10V, ID = 1.5 A
V
GS
V
> I
D(on)
x R
DS
VGS=10V
DS(on)max,
234V
2.2 2.7
4A
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
> I
(1)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance 52 pF
Reverse Transfer
Capacitance
D(on)
x R
DS(on)max,
V
DS
ID=2A
VDS = 25V, f = 1 MHz, VGS = 0
3S
315 pF
7.7 pF
Ω
2/8
STB4NC50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
gs
gd
Turn-on Delay Time
Rise Time 13 ns
Total Gate Charge
g
Gate-Source Charge 2.7 nC
Gate-Drain Charge 6.1 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
f
c
Off-voltage Rise Time
Fall Time 13 ns
Cross-over Time 20 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area .
Source-drain Current 4 A
(2)
Source-drain Current (pulsed) 16 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 1.64 µC
Reverse Recovery Current 8.2 A
= 300V, ID = 2 A
DD
RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)
V
= 400V, ID = 4.2A,
DD
VGS = 10V
VDD = 400V, ID = 4 A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
ISD = 4 A, VGS = 0
ISD = 4 A, di/dt = 100A/µs, VDD
= 100V, Tj = 150°C
(see test circuit, Figure 5)
10 ns
12.5 17 nC
15 ns
1.6 V
400 ns
Safe Operating Area
Ther m al Impe d ance
3/8
STB4NC50
Tranfer CharacteristicsOutput Characteristics
Tranconductance
Gate Charge vs Gate-source Voltage
Static Drain-Source On Resistance
Capacitance Variations
4/8
Source-drain Diode Forward Characteristics
STB4NC50
Normalized On Resistance vs Temperatur eNormalized Gate Thereshold Voltage vs Temp.
5/8
STB4NC50
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
TO-263 (D2PAK) MECHANICAL DATA
STB4NC50
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098 0.106
B 0.7 0.93 0.027 0.036
B2 1.14 1.7 0.044 0.067
C 0.45 0.6 0.017 0.023
C2 1.21 1.36 0.047 0.053
D 8.95 9.35 0.352 0.368
E 10 10.4 0.393 0.409
G 4.88 5.28 0.192 0.208
L 15 15.85 0.590 0.624
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.068
mm inch
D
A
C2
DETAIL "A"
C
A2
DETAIL "A"
A1
B2
E
L2
L
L3
B
G
P011P6/E
7/8
STB4NC50
8/8
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