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STB160NF02L
N-CHANNEL 20V - 0.0018Ω - 160A D2P AK
STripFET™ POWER MOSFET
PRELIMINARY DATA
TYPE V
DSS
STB160NF02L 20 V < 0.0027
■ TYPICAL R
■ LOW THRESHOLD DRIVE
■ ULTRA LOW ON-RESISTANCE
■ VERY LOW GATE CHARGE
■ 100% AVALANCHE TESTED
(on) = 0.0018Ω
DS
R
DS(on)
I
D
Ω
160 A
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronics unique “Single Feature
™” strip-based process. The re sulting tran-
Size
sistor shows extremely high packing density with
ultra low on-resistance, superior switching characteristics and less critical alignment steps therefore
a remarkable manufacturing reproducibility. This
device is particularly suitable for high current, low
voltage switching application where efficiency is
crucial.
APPLICATIONS
■ BUCK CONVERTERS IN HIGH
PERFORMANCE TELECOM AND VRMs
■ DC-DC CONVERTERS
3
1
D2PAK
(TO-263)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
(1) Drain Current (continuos) at TC = 25°C
D
I
D
I
DM
P
TOT
E
AS
T
stg
T
j
(●) Pulse width limited by safe operating area
February 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
20 V
20 V
Gate- source Voltage ±15 V
160 A
Drain Current (continuos) at TC = 100°C
(●)
Drain Current (pulsed) 640 A
Total Dissipation at TC = 25°C
113 A
300 W
Derating Factor 2 W/°C
(2)
Single Pulse Avalanche Energy 2.65 mJ
Storage Temperature –65 to 175 °C
Max. Operating Junction Temperature 175 °C
(1) Limited by Package
≤100A, di/dt ≤300A/µs, VDD ≤ V
(2) I
SD
(BR)DSS
, Tj ≤ T
JMAX.
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STB160NF02L
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.5 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
I
D(on)
Maximum Lead Temperature For Soldering Purpose 300 °C
Drain-source
ID = 250 µA, VGS = 0 20 V
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
Resistance
On State Drain Current VDS > I
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±15V ±100 nA
GS
V
= VGS, ID = 250µA
DS
VGS = 10 V, ID = 80 A
VGS = 5 V, ID = 80 A
x R
D(on)
DS(on)max,
1V
0.0018 0.0027
0.0038 0.0064
160 A
1µA
10 µA
VGS=10V
Ω
Ω
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 3250 pF
Reverse Transfer
Capacitance
ID=80 A
V
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
210 S
5600 pF
750 pF
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STB160NF02L
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 390 ns
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
d(off)
t
f
t
f
t
c
Turn-off-Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (2)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c yc l e 1.5 %.
2. Pulse width li mited by safe operating area.
Source-drain Current 160 A
(1)
Source-drain Current (pulsed) 640 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
= 10V, ID = 80A
DD
RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)
= 16V, ID = 160A,
V
DD
VGS = 10V
VDD = 10V, ID = 80A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
GS
=40A
D
= 10V
Vclamp =16V, I
RG=4.7Ω, V
ISD = 160A, VGS = 0
= 80A, di/dt = 100A/µs,
I
SD
VDD = 15V, Tj = 25°C
(see test circuit, Figure 5)
30 ns
130
20
54
100
90
105
50
100
1.3 V
90
225
5
nC
nC
nC
ns
ns
ns
ns
ns
ns
nC
A
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STB160NF02L
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
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2
D
PAK MECHANICAL DATA
STB160NF02L
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098 0.106
A2 0.03 0.23 0.001 0.009
B 0.7 0.93 0.027 0.036
B2 1.14 1.7 0.044 0.067
C 0.45 0.6 0.017 0.023
C2 1.23 1.36 0.048 0.053
D 8.95 9.35 0.352 0.368
D1 8 0.315
E 10 10.4 0.393
E1 8.5 0.334
G 4.88 5.28 0.192 0.208
L 15 15.85 0.590 0.625
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.068
mm. inch
M 2.4 3.2 0.094 0.126
R 0.4 0.015
V2 0º8º
3
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1
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STB160NF02L
D2PAK FOOTPRINT
TAPE AND REEL SHIPMENT (suffix ”T4”)*
TUBE SHIPMENT (no suffix)*
REEL MECHANICAL DATA
DIM.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0795
G 24.4 26.4 0.960 1.039
N 100 3.937
T 30.4 1.197
mm inch
MIN. MAX. MIN. MAX.
TAPE MECHANICAL DATA
DIM.
A0 10.5 10.7 0.413 0.421
B0 15.7 15.9 0.618 0.626
D 1.5 1.6 0.059 0.063
D1 1.59 1.61 0.062 0.063
E 1.65 1.85 0.065 0.073
F 11.4 11.6 0.449 0.456
K0 4.8 5.0 0.189 0.197
P0 3.9 4.1 0.153 0.161
P1 11.9 12.1 0.468 0.476
P2 1.9 2.1 0.075 0.082
R 50 1.574
T 0.25 0.35 0.0098 0.0137
W 23.7 24.3 0.933 0.956
* on sales type
6/7
mm inch
MIN. MAX. MIN. MAX.
BASE QTY BULK QTY
1000 1000
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STB160NF02L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.
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STMicroelectronics GROUP OF COMPANIES
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