Datasheet ST93C67, ST93C66 Datasheet (SGS Thomson Microelectronics)

4K (256 x 16 or 512 x 8)SERIALMICROWIREEEPROM

1 MILLIONERASE/WRITE CYCLES, with
40 YEARS DATARETENTION

DUALORGANIZATION:256 x 16 or 512 x 8
BYTE/WORDand ENTIRE MEMORY

PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMINGCYCLEwith

AUTO-ERASE
READY/BUSY SIGNAL DURING

PROGRAMMING
SINGLESUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C66version
– 3V to 5.5V for ST93C67 version
SEQUENTIAL READ OPERATION
5ms TYPICALPROGRAMMING TIME

ST93C66and ST93C67are replaced by the
M93C66

8

1

PSDIP8 (B)

0.4mm Frame

Figure 1. Logic Diagram

ST93C66
ST93C67

NOT FOR NEW DESIGN

8

1

SO8 (CM)

150mil Width

DESCRIPTION

This specification covers a range of 4K bit serial
EEPROMproducts, the ST93C66specified at 5V
± 10%and theST93C67 specifiedat 3V to 5.5V.In
the text, products are referred to asST93C66.

The ST93C66 is a 4K bit Electrically Erasable
ProgrammableMemory(EEPROM)fabricatedwith
SGS-THOMSON’sHighEnduranceSinglePolysili­con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 4K
bit memory is divided into either 512 x 8 bit bytes
or 256 x 16 bit words. The organization may be
selectedby a signalappliedon the ORG input.

Table 1. Signal Names

S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG Organisation Select
V

CC

V

SS

Supply Voltage
Ground

ORG

V

CC

D

C
S

ST93C66
ST93C67

V

SS

Q

AI01252B

July 1997 1/13

This isinformation on a product still in production but not recommended for new designs.

ST93C66,ST93C67

Figure2A. DIPPin Connections

ST93C66
ST93C67

SV

1
2

D

3

Q

4

Warning: DU = Don’t Use Warning: DU = Don’t Use

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

STG

T

LEAD

V

V

CC

V

ESD

Notes: 1. Exceptfor the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

Ambient Operating Temperature –40 to 125 °C

A

Storage Temperature –65 to 150 °C
Lead Temperature,Soldering (SO8 package)

Input or Output Voltages(Q = VOHor Hi-Z) –0.3 to VCC+0.5 V

IO

Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

may cause permanent damage to the device. Theseare stress ratings only and operation of thedevice at these or any other
conditions abovethose indicated in the Operating sectionsof this specification is not implied. Exposure toAbsolute Maximum
Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Programand other
relevant quality documents.

2. MIL-STD-883C, 3015.7(100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

8
7
6
5

AI01253B

CC

DUC
ORG
V

SS

(1)

(PSDIP8 package)

Figure2B. SO Pin Connections

ST93C66
ST93C67

1

SV

2

D

3

Q

4

40 sec
10 sec

(2)

(3)

8
7
6
5

AI01254C

215
260

7000 V
1000 V

CC

DUC
ORG
V

SS

°C

DESCRIPTION (cont’d)
The memory is accessed by a set of instructions

which includes Read a byte/word, Write a
byte/word,Erasea byte/word,Erase All and Write
All. ARead instructionloads theaddressof the first
byte/word to be read into an internal address
pointer.The data containedat this addressis then
clocked out serially. The address pointer is auto­maticallyincrementedafterthe data is output and,
if the Chip Select input (S) is held High, the
ST93C66 can output a sequential stream of data
bytes/words.In this way,the memorycan be read
as a data stream from 8 to 4096 bits long, or
continuouslyas the address counterautomatically
rolls over to ’00’ when the highest address is
reached.Programming is internallyself-timed(the
external clock signal on C input may be discon-

2/13

nectedorleftrunningafterthestart ofa Writecycle)
and does not require an erase cycle prior to the
Write instruction. The Write instruction writes 8 or
16 bits at one timeinto oneof the512 bytesor256
words. After the startof the programming cycle, a
Busy/Readysignal is available on the Data output
(Q)when Chip Select (S) is driven High.

The design of the ST93C66 and the High Endur­anceCMOStechnologyusedforitsfabricationgive
an Erase/Write cycle Endurance of 1,000,000 cy­clesand a data retention of 40 years.

TheDU (Don’tUse) pindoesnotaffectthefunction
of the memory and it is reserved for use by SGS­THOMSON duringtestsequences.The pinmaybe
left unconnectedor may be connected to V
V

. Direct connection of DU to VSSis recom-

SS

CC

or

mended for the lowest standby power consump­tion.

ST93C66, ST93C67

AC MEASUREMENT CONDITIONS

Figure 3. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages 0.4V to 2.4V
Input TimingReference Voltages 1V to 2.0V
Output TimingReference Voltages 0.8V to 2.0V

Note that Output Hi-Z is defined as the point where data

2.4V

0.4V

2V
1V

INPUT OUTPUT

is no longer driven.

Table 3. Capacitance

(1)

(TA=25°C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampledonly, not 100% tested.

Input Capacitance VIN=0V 5 pF
Output Capacitance V

=0V 5 pF

OUT

Table 4. DC Characteristics

= 0 to70°C or –40 to 85°C; VCC= 4.5V to 5.5V or 3V to 5.5V)

(T

A

2.0V

0.8V

AI00815

Symbol Parameter TestCondition Min Max Unit

I

I

I

CC1

V

V

V

V

I

LI

LO

CC

IL

IH

OL

OH

Input Leakage Current 0V ≤ VIN≤ V

Output Leakage Current

0V ≤ V

≤ VCC,

OUT

Q inHi-Z

CC

±2.5 µA

±2.5 µA

Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA
Supply Current (CMOS Inputs) S = V

Supply Current (Standby)

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

Output Low Voltage

Output High Voltage

, f = 1 MHz 2 mA

IH

,C=VSS,

S=V

SS

ORG = V

V

CC

3V ≤ V
V

CC

3V ≤ V

I

OL

I

I

OH

I

OH

or V

SS

CC

=5V±10% –0.3 0.8 V

≤ 4.5V –0.3 0.2V

CC

=5V±10% 2 VCC+1 V

≤ 4.5V 0.8 V

CC

CC

= 2.1mA 0.4 V

=10µA 0.2 V

OL

= –400µA 2.4 V

= –10µAV

–0.2 V

CC

50 µA

VCC+1 V

CC

V

3/13

ST93C66,ST93C67

Table 5. AC Characteristics

(T

= 0 to70°C or –40 to 85°C; VCC= 4.5V to 5.5V or 3V to 5.5V)

A

Symbol Alt Parameter Test Condition Min Max Unit

t

SHCH

t

CLSH

t

DVCH

t

CHDX

t
t

t

t

Chip Select High to Clock High 50 ns

CSS

Clock Low to Chip SelectHigh 100 ns

SKS

Input Valid to Clock High 100 ns

DIS

Temp.Range: grade 1 100 ns

Clock High to Input Transition

DIH

Temp.Range:

grades3, 6

200 ns

t

CHQL

t

CHQV

t

CLSL

t

SLCH

t

SLSH

t

SHQV

t

SLQZ

t

CHCL

t

CLCH

t

W

f

C

Notes: 1. Chip Selectmust bebrought low for a minimumof 250 ns(t

2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings t

t
t
t

Clock High to Output Low 500 ns

PD0

Clock High to Output Valid 500 ns

PD1

Clock Low to Chip SelectLow 0 ns

CSH

Chip Select Low to Clock High 250 ns

t

Chip Select Low to Chip Select High Note 1 250 ns

CS

t

Chip Select High to Output Valid 500 ns

SV

t

Chip Select Low to Output Hi-Z 200 ns

DF

t
t

must be greater or equal to 1 µs. For example, ift

Clock High to Clock Low Note 2 250 ns

SKH

Clock Low to Clock High Note 2 250 ns

SKL

t

Erase/Write Cycle time 10 ms

WP

f

Clock Frequency 0 1 MHz

SK

is 250 ns, then t

CHCL

) between consecutive instruction cycles.

SLSH

must be at least 750 ns.

CLCH

Figure4. Synchronous Timing, Start and Op-CodeInput

CHCL+tCLCH

4/13

tCLSH tCHCL

C

tSHCH

S

tDVCH

D

OP CODE OP CODESTART

OP CODE INPUTSTART

tCLCH

tCHDX

AI01428

Figure5. SynchronousTiming,Read or Write

C

S

ST93C66, ST93C67

tCLSL

tDVCH

D

Q

C

S

D

Q

Hi-Z

An

tCHQL

ADDRESS INPUT

tDVCH

An

Hi-Z

A0

A0/D0

tCHQVtCHDX

tSLQZ

Q15/Q7 Q0

DATA OUTPUT

tSLCH

tCLSL

tSLSHtCHDX

BUSY

tSLQZ

READY

tSHQV

tSLSH

AI00820C

ADDRESS/DATA INPUT

MEMORY ORGANIZATION

The ST93C66isorganizedas512bytesx 8 bits or
256 words x 16 bits. If theORGinputis left uncon­nected(or connectedto V

) the x16 organization

CC

is selected, when ORG is connected to Ground

) the x8 organization is selected. When the

(V

SS

ST93C66 is in standby mode, the ORG input
should be unconnectedor set to either V

SS

or V

CC

in order to achieve the minimum power consump­tion. Any voltage between V

and VCCappliedto

SS

ORG may increase the standby currentvalue.

tW

WRITE CYCLE

AI01429

POWER-ON DATA PROTECTION

In orderto prevent datacorruptionand inadvertent
write operations during power up, a Power On
Reset(POR)circuitresetsall internalprogramming
circuitry and sets the device in the Write Disable
mode. When V

reaches its functionalvalue,the

CC

deviceisproperlyreset(inthe WriteDisable mode)
and is ready to decode and execute an incoming
instruction. A stable V

must be applied, before

CC

applyinganylogic signal.

5/13

ST93C66,ST93C67

INSTRUCTIONS

The ST93C66has seven instructions, as shownin
Table 6.Theop-codesofthe instructionsaremade
up of2 bits.The op-code is followed by an address
for thebyte/wordwhichiseightbitslong for the x16
organization or nine bits long for the x8 organiza­tion.Eachinstructionisprecededbytherising edge
of the signal applied on the Chip Select (S) input
(assumingthat tha Clock C is low). The data input
D is thensampledupon the followingrising edges
of the clock C untill a ’1’ is sampled and decoded
by the ST93C66as a Start bit.

The ST93C66 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
inputsignals)up to themaximumratings(specified
in Table5).

Read

The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de­codedandthe datafromthememory is transferred
intoanoutputshiftregister.Adummy’0’bitisoutput
first, followed by the 8 bit byte or the 16 bit word
with the MSB first. Output data changes are trig­geredby theLowtoHightransition oftheClock(C).
The ST93C66will automaticallyincrement the ad­dressand will clock out the next byte/wordas long
as the Chip Select input (S) is held High. In this
case the dummy ’0’ bit is NOT output between
bytes/wordsand a continuousstream of data can
be read.

Erase/WriteEnable and Disable

The Erase/Write Enable instruction (EWEN)
authorizesthe followingErase/Writeinstructions to
be executed, the Erase/Write Disable instruction

(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap­plied, the ST93C66 enters the Disable mode.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disableinstruction(EWDS)is executedorV

CC

falls
belowthe power-onreset threshold.To protect the
memory contents from accidental corruption, it is
advisabletoissuethe EWDSinstructionafterevery
writecycle.

TheREADinstructionisnot affectedbytheEWEN
or EWDS instructions.

Erase

The Erase instruction (ERASE) programs the ad­dressedmemorybyte or word bits to ’1’.Once the
addressiscorrectlydecoded,thefallingedgeofthe
Chip Select input (S) triggers a self-timed erase
cycle.

If the ST93C66is still performing the erase cycle,
theBusysignal(Q=0)willbe returnedif S isdriven
high, and the ST93C66will ignore any data on the
bus.Whentheerase cycleiscompleted,theReady
signal(Q = 1) will indicate (if S is driven high) that
the ST93C66is readyto receiveanewinstruction.

Write

The Write instruction (WRITE) is followed by the
addressandthe8or16 databits to bewritten. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start
the self-timed programming cycle. If the ST93C66
is still performing the write cycle, the Busy signal
(Q =0) will be returned if S is driven high, and the
ST93C66will ignore any data on the bus.

Table 6. InstructionSet

Instruc-

tion

READ Read Data from Memory 10 A8-A0 Q7-Q0 A7-A0 Q15-Q0

WRITE Write Data to Memory 01 A8-A0 D7-D0 A7-A0 D15-D0

EWEN Erase/Write Enable 00 11XXXXXXX 11XX XXXX
EWDS Erase/Write Disable 00 00XXX XXXX 00XX XXXX

ERASE Erase Byte or Word 11 A8-A0 A7-A0

ERAL Erase All Memory 00 10XXX XXXX 10XX XXXX

WRAL

Note: 1. X = don’t care bit.

6/13

Description Op-Code

Write All Memory
with same Data

00 01XXX XXXX D7-D0 01XX XXXX D15-D0

x8 Org

Address

(ORG = 0)

(1)

Data

x16 Org

Address

(ORG = 1)

(1)

Data

Figure 6. READ,WRITE, EWEN, EWDS Sequences

ST93C66, ST93C67

READ

ERASE
WRITE
ENABLE

S

D

Q

SWRITE

D

Q

S

1 1 0 An A0

ADDR

OP

CODE

1 0 An A0

ADDR

OP

CODE

Qn Q0

DATA OUT

Dn D01

DATA IN

ERASE
WRITE
DISABLE

S

CHECK

STATUS

BUSY READY

1 0 Xn X0D

101

OP

CODE

Notes: 1. An: n = 7 for x16 org. and 8 for x8 org.

2. Xn: n = 5 for x16 org. and 6 for x8 org.

When the write cycle is completed, the Ready
signal(Q = 1) will indicate (if S is driven high) that
the ST93C66is readyto receivea new instruction.
Programmingis internally self-timed (the external
clocksignalon C input may be disconnectedor left

1 0 Xn X0D

000

OP

CODE

AI00878C

runningafterthestartof a programmingcycle)and
does not require an Erase instruction prior to the
Writeinstruction(TheWrite instructionincludesan
automaticerase cycle before programing data).

7/13

ST93C66,ST93C67

Figure7. ERASE, ERAL Sequences

SERASE

Q

11D

An A0

1

CHECK

STATUS

ERASE
ALL

Notes: 1. An:n = 7 forx16 org. and 8 for x8 org.

2. Xn: n = 5 for x16 org. and 6 for x8 org.

S

Q

Figure8. WRAL Sequence

OP

CODE

10D

00

1

OP

CODE

ADDR

Xn X0

ADDR

BUSY READY

CHECK

STATUS

BUSY READY

AI00879B

ALL

Note: 2. Xn:n = 5 for x16 org. and 6 for x8 org.

SWRITE

D

Q

1000 1 Xn X0

OP

CODE

8/13

ADDR

Dn D0

DATA IN

CHECK

STATUS

BUSY READY

AI00880C

ST93C66, ST93C67

Erase All

The EraseAll instruction(ERAL) erasesthe whole
memory (all memory bits are set to ’1’). A dummy
addressis input duringthe instructiontransfer and
the erase is made in the same way as the ERASE
instruction. If the ST93C66 is still performing the
erasecycle,theBusysignal(Q=0) willbe returned
if S is driven high,andtheST93C66will ignore any
data on the bus. When the erase cycle is com­pleted, the Ready signal (Q = 1) will indicate (if S
isdriven high)that theST93C66is readyto receive
a new instruction.

WriteAll

For correct operation, an ERAL instruction should
be executed before the WRAL instruction: the
WRALinstructionDOESNOTperformanautomat­ic erase before writing. The Write All instruction
(WRAL) writes theDataInputbyteorwordto all the
addresses of the memory. If the ST93C66 is still
performingthe writecycle,the Busy signal (Q = 0)
willbereturnedifSisdrivenhigh,andtheST93C66
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C66 is
readyto receive a new instruction.

READY/BUSY Status

During every programming cycle (after a WRITE,
ERASE, WRALor ERALinstruction) the DataOut­put (Q) indicates the Ready/Busy status of the
memory when the Chip Select (S) is driven High.
Once the ST93C66 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
broughtLow.

COMMONI/O OPERATION

TheDataOutput(Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywith thisconnection,mostlytoprevent
a shortcircuit betweenthelastentered addressbit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSON application
note”MICROWIREEEPROMCommonI/OOpera­tion”.

CLOCKPULSE COUNTER

The ST93C66 offers a functional security filtering
glitches on the clock input (C), the Clock pulse
counter.

In a normal environment,the ST93C66 expects to
receive the exact amount of data on the D input,
that is, the exact amount of clock pulses on the C
input.

In a noisy environment,the number of pulses re­ceived (on the clock input C) may be greater than
the clockpulsesdeliveredby theMaster(Microcon­troller)drivingtheST93C66.In such a case,a part
of the instruction is delayed by one bit (see Figure

9), andit mayinduceanerroneouswrite of dataat
a wrong address.

TheST93C66hasan on-chipcounterwhichcounts
the clock pulses from the Start bit until the falling
edge of the Chip Select signal. For the WRITE
instructions, the number of clock pulses incoming
to the counter must be exactly 20 (with the Organ­isationby 8) from the Start bit to thefallingedge of
Chip Select signal (1 Start bit + 2 bits of Op-code
+ 9 bits of Address + 8 bits of Data = 20): if so,the
ST93C66 executes the WRITE instruction; if the
number of clock pulses is not equal to 20, the
instruction will not be executed (and data will not
be corrupted).

In the same way, when the Organisationby 16 is
selected, the number of clock pulses incoming to
the countermust be exactly27 (1 Start bit + 2 bits
of Op-code+ 8 bits of Address + 16 bits of Data =

27) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C66 executes the
WRITEinstruction;if the number of clockpulses is
not equal to 27, theinstruction willnotbe executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in­structions(WRITE, ERASE, ERAL, WRALL).

9/13

ST93C66,ST93C67

Figure9. WRITE Sequence with OneClock Glitch

S

C

D

START D0”1””0”

WRITE

ORDERING INFORMATION SCHEME

Example: ST93C66 CM 3 TR

Operating Voltage

66 4.5V to 5.5V
67 3V to 5.5V

Package

B PSDIP8

0.4 mm Frame

CM SO8

150mil Width

An

An-1

Glitch

An-2

ADDRESS AND

ARE SHIFTED BY ONE BIT

TemperatureRange

1 0 to 70 °C
6 –40 to 85 °C

(1)

3

–40 to 125 °C

DATA

AI01395

Option

TR Tape & Reel

Packing

Note: 1. Temperature range on request only.

Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).

For a listof availableoptions (OperatingVoltage,Package, etc...)or for further informationon any aspect
of this device, please contact theSGS-THOMSON Sales Officenearest to you.

10/13

ST93C66, ST93C67

PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame

Symb

Typ Min Max Typ Min Max

A 4.80 0.189
A1 0.70 – 0.028 –
A2 3.10 3.60 0.122 0.142

B 0.38 0.58 0.015 0.023
B1 1.15 1.65 0.045 0.065

C 0.38 0.52 0.015 0.020
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.30 7.10 0.248 0.280
e1 2.54 – – 0.100 – –
eA 8.40 – 0.331 –
eB 9.20 0.362

L 3.00 3.80 0.118 0.150

N8 8

CP 0.10 0.004

PSDIP8

mm inches

Drawing is not to scale.

A2A1A

L

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

11/13

ST93C66,ST93C67

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO8

mm inches

Drawing is not to scale.

12/13

B

SO-a

hx45°

A

C

e

CP

D

N

E

H

1

LA1 α

ST93C66, ST93C67

Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted byimplication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are notauthorized foruse ascritical componentsin life supportdevices or systemswithout express
written approval of SGS-THOMSON Microelectronics.

 1997 SGS-THOMSON Microelectronics - All Rights Reserved

 MICROWIRE isa registered trademark of National Semiconductor Corp.

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SGS-THOMSON Microelectronics GROUP OF COMPANIES

13/13