Datasheet ST92R195B, ST92R195 Datasheet (SGS Thomson Microelectronics)

ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER

■ Register File based 8/16 bit Core Architecture

with RUN, WFI, SLOW and HALT modes

■ 0°C to +70°C Operating Temperature Range

available

■ Up to 24 MHz Operation @ 5V±10%

■ Minimum instruction cycle time: 375ns at

16 MHz internal clock

■ 4 Mbytes address space

■ 256 BytesRAMof Register file(accumulatorsor

index registers)

■ 1024 Bytes of on-chip static RAM

■ 8K Bytes of TDSRAM (Teletext and Display

Storage RAM)

■ 80-lead QFP package

■ 23 fully programmable I/O pins

■ Serial Peripheral Interface

■ Flexible Clock controller for OSD, Data Slicer

and Core clocks running from one single low
frequency external crystal.

■ Enhanced Display Controller with 26 rows of

40/80 characters
– Serial and Parallel attributes
– 10x10 dot Matrix, 512ROM characters, defin-

able by user

– 4/3 and 16/9 supported in 50/60Hz and 100/

120 Hz mode

– Rounding, fringe, double width, doubleheight,

scrolling, cursor, full background color, half­intensity color, translucency and half-tone
modes

■ Teletext unit, including Data slicer, Acquisition

Unit and 8 Kbytes TDSRAM for DataStorage

■ VPS and Wide Screen Signalling slicer

■ Integrated Sync Extractor and Sync Controller

■ 14-bit Voltage Synthesis for tuning reference

voltage

■ Up to 8 ExternalInterrupts plus 1 non-maskable

interrupt

ST92R195B

ROMLESS HCMOS MCU WITH

DATA BRIEFING

QFP80

■ 8 x 8-bit programmable PWM outputs with 5V

open-drain or push-pull capability

■ 16-bit Watchdog timerwith 8-bit prescaler

■ One 16-bit standard timer with 8-bit prescaler

■ 4-channel Analog-to-Digital converter; 5-bit

guaranteed

■ Rich instruction set and 14-Addressing modes

Versatile Development Tools, including Assem­bler, Linker, C-compiler, Archiver, Source Level
Debugger and Hardware Emulators with Real­Time Operating System available from third par­ties

Device Summary

Device

ST92R195B9 ROMLESS 8K Yes PQFP80

Program

Memory

TDS

RAM

VPS/
WSS

Package

Rev. 2.2

January 2000 1/18

1

ST92R195B - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92R195B microcontroller is developed and
manufactured by STMicroelectronics using a pro­prietary n-well HCMOS process. Its performance
derives from the use of aflexible 256-register pro­gramming model for ultra-fast context switching
and real-time event response. The intelligent on­chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti­cal application tasks to get the maximum use of
core resources. The ST92R195B MCU supports
low power consumption and low voltage operation
for power-efficient and low-cost embedded sys­tems.

1.1.1 ST9+ Core

The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.

The general-purpose registers canbe used as ac­cumulators, index registers, or address pointers.
Adjacent registerpairs make up 16-bit registersfor
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera­tions, including arithmetic, loads/stores, and mem­ory/register and memory/memory exchanges.

Two basic addressable spaces are available: the
Memory space and the Register File, which in­cludes the control and status registers of the on­chip peripherals.

1.1.2 Power Saving Modes

To optimize performance versus power consump­tion, a range of operating modes can be dynami­cally selected.

Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit(CCU).

Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un­til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-

cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (LP WFI).

Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.

1.1.3 I/O Ports

Up to 23 I/O lines are dedicated to digital Input/
Output. Theselines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output,analog inputs, external interrupts
and serial or parallel I/O.

1.1.4 TV Peripherals

A set of on-chip peripherals form a complete sys­tem for TV set and VCR applications:

– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD

1.1.5 On Screen Display

The humaninterface isprovided bythe On Screen
Display module, this can produce up to 26 lines of
up to80 characters from a ROM defined 512 char­acter set. The character resolution is 10x10 dots.
Four character sizes are supported. Serial at­tributes allow the user to select foreground and
background colours, character size and fringe
background. Parallel attributes can be used tose­lect additional foreground and background colors
and underline on a character by character basis.

1.1.6 Teletext and Display RAM

The internal 8k Teletext and Display storage RAM
can be usedto store Teletextpages as wellas Dis­play parameters.

2/18

INTRODUCTION (Cont’d)

1.1.7 Teletext, VPS and WSS Data Slicers

The three on-board data slicers using a single ex­ternal crystal are used toextract the Teletext,VPS
and WSS information from the video signal. Hard­ware Hamming decoding is provided.

1.1.8 Voltage Synthesis Tuning Control

14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique canbeused to generate tuning voltages
for TV set applications. The tuning voltage is out­put on one of two separate output pins.

1.1.9 PWM Output

Control ofTV settings isable tobe made withup to
eight 8-bit PWM outputs, with a frequency maxi­mum of 23,437Hz at 8-bitresolution (INTCLK = 12
MHz). Low resolutions with higher frequencyoper­ation can be programmed.

ST92R195B - GENERAL DESCRIPTION

1.1.10 Serial Peripheral Interface (SPI)

The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single line for data in­put and output. A second line is used for a syn­chronous c lock signal.

1.1.11 Standard Timer (STIM)

The ST92R195B has one Standard Timer that in­cludes a programmable 16-bit down counter and
an associated 8-bit prescalerwith Single and Con­tinuous counting modes.

1.1.12 Analog/Digital Converter (ADC)

In a ddition there is a 4 channel Analog t o Digital
Converter with integral s ample and hold, fast

5.75µs conversion time and 6-bit guaranteed reso­lution.

3/18

ST92R195B - GENERAL DESCRIPTION

Figure 1. ST92R195B Block Diagram

ADDR[15:0]
DAT[7:0]

ASN

RWN
DSN
MMU[5:0]

External
Memory I/F

1 Kbyte

RAM

I/O

PORT 0

I/O

PORT 2

P0[2:0]

3

P2[5:0]

6

NMI

INT[7:0]

OSCIN

OSCOUT

RESET

RESETO

SDO/SDI

SCK

MCFM

STOUT

VSO[2:1]

8 Kbytes

TDSRAM

256 bytes

Register File

Management

ST9+ CORE

WATCHDOG

TIMING AND

CLOCK CTRL

STANDARD

VOLTAGE

SYNTHESIS

TRI

8/16-bit

CPU

MMU

Interrupt

RCCU

16-BIT

TIMER/

SPI

TIMER

MEMORY BUS

REGISTER BUS

I/O

PORT 3

I/O

PORT 4

I/O

PORT 5

DATA

SLICER

& ACQUI-

SITION

UNIT

SYNC.

EXTRAC-

TION

VPS/WSS

DATA

SLICER

ADC

SYNC

CONTROL

ON
SCREEN
DISPLAY

PWM

D/A CON-

VERTER

4

8

2

FREQ.

MULTIP.

P3[7:4]

P4[7:0]

P5[1:0]

TXCF

CVBS1

WSCR
WSCF
CVBS2

AIN[4:1]
EXTRG

VSYNC
HSYNC/CSYNC

CSO

PXFM

R/G/B/FB

TSLU
HT

PWM[7:0]

4/18

All alternate functions

(Italic characters)

are mapped on Ports 0, 2, 3, 4 and 5

1.2 PIN DESCRIPTION

ST92R195B - GENERAL DESCRIPTION

ADDR[15:0] External memory interface address

bus.
CVBS1 Composite video input signal for the Tele-

text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/

WSS slicer. Pin AC coupled.

CVBSO, JTDO, JTCK Test pins: leave floating.
DAT[7:0] External memory interface data bus.
DSN Data strobe for external memory interface.
FB

Fast Blanking

. Video analog DAC output.

GND Digital circuit ground.
GNDA Analog circuit ground (must be tied exter-

nally to digital GND).

GNDM External memory interface ground.
HSYNC/CSYNC

Horizontal/Composite sync

. Hori­zontal or composite video synchronisation input to
OSD. Positive or negative polarity.

JTRST0 Test pin: must be tied to GND.
MCFM Analog pin for the display pixel frequency

multiplier.
MMU[5:0] External memory interface MMU seg-

ment bus

OSCIN, OSCOUT

Oscillator

(input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.

PXFM Analog pin for the Display Pixel Frequency
Multiplier

RESET

Reset

(input, active low). The ST9+ is ini-

tialised by the Reset signal. With the deactivation

of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.

R/G/B

Red/Green/Blue

. Video color analog DAC

outputs.
RWN Read/Write strobe for external memory in-

terface.
TEST0 Test pin: must be tied to V

DDA

.

TXCF Analog pin for the teletext PLL.
VDDMainpower supply voltage (5V ±10%, digital)
V

Analog power supply (must be tied external-

DDA

ly to V

V

DDM

VSYNC

).

DDA

External memory interface power supply.

Vertical Sync

. Vertical video synchronisa-

tion input to OSD. Positive or negative polarity.
WSCF, WSCR Analog pins for the VPS/WPP slic-

er. These pins must be tied to ground or not con­nected.

P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]-

Port Lines

(Input/Output, TTL or CMOS compati-

I/O

ble). 23 lines grouped into I/O ports, bit program­mable as general purpose I/Oor as Alternate func­tions (see I/O section).

Important

: Note that open-drain outputs are for

logic levels only and arenot true open drain.

1.2.1 I/O Port Alternate Functions.

Each pin of the I/O ports of the ST92R195B may
assume software programmable Alternate Func­tions as shown in the Pin Configuration drawings.
Table 1. shows the Functions allocated to eachI/O
Port pin.

5/18

ST92R195B - GENERAL DESCRIPTION

Figure 2. 80-Pin Package Pin-Out

ADDR15

ADDR12

ADDR7

ADDR6

ADDR5

ADDR4

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

MMU0
MMU3

ADDR10

DSN

ADDR11

ADDR9
ADDR8

RWN

GNDM

V

DDM

OSCIN

OSCOUT

ADDR13
ADDR14

MMU1
MMU2
MMU4
MMU5

CSO/RESETO/P3.7

ASN/P3.6

P3.5
P3.4

SDI/SDO/INT1/P5.1

SCK/INT2/P5.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25 26 27 28 29 30 31 32 37 38 39

ADDR3

ADDR2

33 34 35 36

ADDR1

ADDR0

DAT0

DAT1

DAT2

DAT7

DAT6

40

DAT5

DAT4

64
63

DAT3

62

GNDA

61

CVBS1

60

CVBS2

59

TEST0

58

CVBSO

57

TXCF

56

JTRST0

55

MCFM

54

RESET

53

PXFM

52

VDDA

51

WSCF

50

WSCR

49

HSYNC/CSYNC
VSYNC

48

R

47

G

46

B

45

FB

44

P4.0/PWM0

43

P4.1/PWM1

42

41

P4.2/PWM2

6/18

INT7/P2.0

NMI/P2.4

INT6/VSO1/P2.3

P0.1

AIN4/P0.2

DD

P0.0

PWM6/P4.6

PWM7/EXTRG/INT3/STOUT/P4.7

V

GND

PWM5/P4.5

INT5/AIN1/P2.1

PWM4/P4.4

INT0/AIN2/P2.2

INT4/AIN3/VSO2/P2.5

PWM3/TSLU/HT/P4.3

Table 1. ST92R195B I/O Port Alternate Function

ST92R195B - GENERAL DESCRIPTION

Port
Name

P0.0
P0.1 29 I/O
P0.2 28 AIN4 I A/D Analog Data Input 4
P2.0 25 INT7 I External Interrupt 7

P2.1 36

P2.2 37

P2.3 26

P2.4 27 NMI I Non Maskable Interrupt Input

P2.5 38

P3.4 22 I/O
P3.5 21 I/O
P3.6 20 ASN O External Memory Interface Address Strobe

P3.7 19

P4.0 43 PWM0 O PWM Output 0
P4.1 42 PWM1 O PWM Output 1
P4.2 41 PWM2 O PWM Output 2

P4.3 40

P4.4 39 PWM4 O PWM Output 4
P4.5 33 PWM5 O PWM Output 5
P4.6 32 PWM6 O PWM Output 6

P4.7 31

P5.0 24

P5.1 23

General
Purpose I/O

All portsuseable
for general pur­pose I/O (input,
output or bidi­rectional)

Pin No.
PQFP80
30 I/O

Alternate Functions

AIN1 I A/D Analog Data Input 1
INT5 I External Interrupt 5
INT0 I External Interrupt 0
AIN2 I A/D Analog Data Input 2
INT6 I External Interrupt 6
VSO1 O Voltage Synthesis Output 1

AIN3 I A/D Analog Data Input 3
INT4 I External Interrupt 4
VSO2 O Voltage Synthesis Output 2

RESET0 O Internal Reset Output
CSO O Composite Sync output

PWM3 O PWM Output 3
TSLU O Translucency Digital Output
HT O Half-tone Output

EXTRG I A/D Converter External Trigger Input
PWM7 O PWM Output 7
STOUT O Standard Timer Output
INT3 I External Interrupt 3
INT2 I External Interrupt 2
SCK O SPI Serial Clock
SDO O SPI Serial Data Out
SDI I SPI Serial Data In
INT1 I External Interrupt 1

7/18

ST92R195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont’d)

1.2.2 I/O Port Styles

Pins Physical Pull-Up Pin Style Reset Values

P0[2:0] no standard I/O BID / OD / TTL
P2[5,4,3,2] no standard I/O BID / OD / TTL
P2[1:0] no std I/O, trigger BID / OD / TTL
P3.7 yes standard I/O AF / PP / TTL
P3[6,5,4] no standard I/O BID / OD / TTL
P4[7:0] no standard I/O BID / OD / TTL
P5[1:0] no standard I/O BID / OD / TTL

Legend:

AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels

How to Read this Table

To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter ofthe datasheet.

Port Style= the hardware characteristics fixed for
each port line.

Inputs:
– Ifport style = Standard I/O,either TTLor CMOS

input level can be selected by software.

– If port style = Schmitt trigger, selecting CMOSor

TTL inputbysoftwarehasno effect,the input will
always be Schmitt Trigger.

Weak Pull-Up = This column indicates if a weak
pull-up is present or not.

– If WPU=yes, then the WPU can be enabled/dis-

able by software

– IfWPU = no,thenenablingthe WPU bysoftware

has no effect

Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:

An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corre-

sponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.

AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected

explicitly by software.

Example 1: ADC trigger digital input

AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC trigger by software as described

in the ADC chapter.

Example 2: PWM 0 output

AF: PWM0, Port: P4.0
Write the port configuration bits (for output push-

pull):
P4C2.0=0
P4C1.0=1
P4C0.0=1

Example 3: ADC AIN1 analog input

AF: AIN1, Port: P2.1,Port style:does not applyto
analog inputs

Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1

8/18

Figure 3. ST92R195B Required External components

R2

5.6K

C10

4.7NF

C8

22PF

ST92R195B - GENERAL DESCRIPTION

10k

R3

1µF

C6

CVBS

82pF

470nF

C2

C1

58

62

63

57

59

616460

DAT3

DAT4

GNDA

TEST0

CVBS1

CVBS2

CVBSO

DAT5

65

DAT6

66

DAT7

67

DAT2

68

DAT1

69

DAT0

70

ADDR0

71

ADDR1

72

ADDR2

73

ADDR3

74

ADDR4

75

ADDR5

76

ADDR6

77

ADDR7

78

ADDR12

79

ADDR15

80

C5

555453525150494847464544434241

TXCF

PXFM

VDDA

MCFM

WSCF

JTRST0

RESETN

ST92R195B

S1

C9

22PF

5.6K

R

HSYNC

VSYNC

RGB

WSCR

VSYNC

CSYNC/HSYNC

1N4148

D1

RST

4.7NF

R4

L1 10uH

C13

4.7 µF

100nF

P4.0/PWM0

P4.1/PWM1

P4.2/PWM2

C12

P4.3/PWM3/TSLU/HT

40

P4.4/PWM4

39

P2.5/INT4/AIN3/VSO2

38

P2.2/INT0/AIN2

37

P2.1/INT5/AIN1

36

GND

35

VDD

34

P4.5/PWM5

33

P4.6/PWM6

32

P4.7/PWM7/INT3

31

P0.0

30

P0.1

29

P0.2/AIN4

28

P2.4/NMI

27

P2.3/INT6/VSO1

26

P2.0/INT7

25

B

G

FB

FB

+5V

L3 10uH

C16

4.7 µF

100nF

C15

U1

MMU0

MMU3

ADDR10

DSN

ADDR11

ADDR9

1562345678

C3

ADDR8

R/WN

GNDM

VDDM

OSCIN

OSCOUT

ADDR13

ADDR14

MMU1

XT1

4MHZ-OSC

C4

MMU2

C7

82pF

9

10111213141516171920212223

82pF

MMU4

P3.7/CSO/RESETO

P3.6/ASN

MMU5

18

100nF

P3.5

P3.4

P5.1/SDI/SDO/INT1

P5.0/SCK/INT2

24

+5V +5V

QFP80

10uH

L2

C14

4.7 µF

9/18

ST92R195B - GENERAL DESCRIPTION

1.3 MEMORY MAP
No Internal ROM

Internal RAM, 1 Kbytes

The internal RAM is mapped in MMU segment
20h; from address FC00h to FFFFh.

Figure 4. ST92R195B Memory Map

External RAM

8 Kbytes

TDSRAM

Internal

RAM

1 Kbyte

229FFFh

228000h

20FFFFh

20FC00h

SEGMENT 22h

64 Kbytes

SEGMENT 21h

64 Kbytes

SEGMENT 20h

64 Kbytes

InternalTDSRAM,8Kbytesexpandableupto16K
(into segment 22h)
TheInternalTDSRAMismappedintotheMMU seg­ment 22h. The TDSRAM is a fully static memory.

The TDSRAM is an 8K bytes mapped at the ad­dress 8000h to 9FFFh.

39FFFFh

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

22FFFFh

22C000h
22BFFFh

228000h
227FFFh

224000h
223FFFh

220000h
21FFFFh

210000h

20FFFFh

20C000h
20BFFFh

208000h
207FFFh

204000h
203FFFh

200000h

PAGE 91 - 16 Kbytes

PAGE 90 - 16 Kbytes

PAGE 89 - 16 Kbytes

PAGE 88 - 16 Kbytes

PAGE 83 - 16 Kbytes

PAGE 82 - 16 Kbytes

PAGE 81 - 16 Kbytes

PAGE 80 - 16 Kbytes

10/18

External ROM/EPROM

SEGMENT 1

64 Kbytes

SEGMENT 0

64 Kbytes

01FFFFh
01C000h

01BFFFh
018000h

017FFFh
014000h

013FFFh

010000h

00FFFFh
00C000h

00BFFFh
008000h

007FFFh
004000h

003FFFh
000000h

PAGE 7 - 16 Kbytes

PAGE 6 - 16 Kbytes

PAGE 5 - 16 Kbytes

PAGE 4 - 16 Kbytes

PAGE 3 - 16 Kbytes

PAGE 2 - 16 Kbytes

PAGE 1 - 16 Kbytes

PAGE 0 - 16 Kbytes

ST92R195B - ELECTRICAL CHARACTERISTICS

2 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD

V

SSA

V

DDA

V

I

V

AI

V

O

T

STG

I

INJ

Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.

Supply Voltage VSS- 0.3 to VSS+ 7.0 V
Analog Ground VSS- 0.3 to VSS+ 0.3 V
Analog Supply Voltage VDD-0.3 to VDD+0.3 V
Input Voltage VSS- 0.3 to VDD+0.3 V

- 0.3 to VDD+0.3

V

Analog Input Voltage (A/D Converter)

V

SS
SSA

- 0.3 to V

DDA

+0.3

V

Output Voltage VSS- 0.3 to VDD+ 0.3 V
Storage Temperature - 55 to + 150 °C
Pin Injected Current

-5to+5

mA
Maximum Accumulated Pin
Injected Current In Device

-50to+50

mA

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter

T

A

V

DD

V

DDA

f

OSCE

f

OSCI

Operating Temperature 0 70 °C
Supply Voltage 4.5 5.5 V
Analog Supply Voltage (PLL) 4.5 5.5 V
External Oscillator Frequency 3.3 8.7 MHz

Internal Clock Frequency (INTCLK) 24 MHz

Value

Min. Max.

Unit

11/18

ST92R195B - ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Symbol Parameter Test Conditions

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

IHCK
ILCK
IH
IL
IH
IL
IHRS
ILRS
HYRS
IHY
IHVH
ILVH
HYHV
OH
OL

Clock in high level external clock 0.7 V
Clock in low level external clock 0.3 V
Input high level TTL 2.0 V
Input low level TTL 0.8 V
Input high level CMOS 0.8 V
Input low level CMOS 0.2 V
Reset in high level 0.7 V
Reset in low level 0.3 V
Reset in hysteresis 0.3 V
P2.(1:0) input hysteresis 0.9 V
HSYNC/VSYNC input high level 0.7 V
HSYNC/VSYNC input low level 0.3 V
HSYNC/VSYNC input hysteresis 0.5 V
Output high level Push-pull Ild=-0.8mA VDD-0.8 V
Output low level Push-pull ld=+1.6mA 0.4 V

bidir. state

I

WPU

I

LKIO

I

LKRS

I

LKAD

I

LKOS

Weak pull-up current

I/O pin input leakage current 0<VIN<V
Reset pin input 0<VIN<V
A/D pin input leakage current alternate funct. op. drain -10 +10 µA
OSCIN pin input leakage current 0<VIN<V

VOL=3V

=7V

V

OL

DD
DD

DD

Value

Min. Max.

DD

DD

DD

DD

Unit

DD

DD

DD

DD

50

350

-10 +10 µA

-10 +10 µA

-10 +10 µA

V
V

V
V
V
V

V
V

µA

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ST92R195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))

Symbol Parameter Conditions

C

IO

Pin Capacitance Digital Input/Output 10 pF

Value

min max

Unit

CURRENT CONSUMPTION

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Symbol Parameter Conditions

I

DD1

I

DDA1

I

DD2

I

DDA2

Notes:

1. Port 0 is configured inpush-pull output mode (output is high). Ports 2, 3,4 and5 are configured in bi-directional weak pull-up mode resistor.

The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz.The internal clock prescaler is in divide-by-1 mode.

2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to
All peripherals working including Display.

3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to
The TDSRAM interface and the Slicers are working; the Display controller is not working.

4. VSYNC and HSYNC tied to

Run Mode Current notes 1,2; all On 70 100 mA
Run Mode Analog Current

DDA

)

(pin V

Timing Controller On 35 50 mA

HALT Mode Current notes 1,4 10 100 µA

HALTMode Analog Current

(pin V

)

DDA

V

. External CLOCK pin (OSCIN) is held low. All peripherals are disabled.

SS

notes 1,4 40 100 µA

min typ. max

V
V

Value

, HSYNCis driven by a 15625Hz clock.

SS

, HSYNCis driven by a 15625Hz clock.

SS

Unit

EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))

Symbol Parameter

T

wLR

T

wHR

TpC is the INTCLK clock period.

Low level pulse width TpC+12 95 ns
High level pulse width TpC+12 95 ns

Conditions Value Unit

INTCLK=24 MHz. min max

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ST92R195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS (Cont’d)
EXTERNAL MEMORY INTERFACE TIMING TABLE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))

Symbol Parameter

T

wDSR

T

wDSW

(DR) DSN↓ to data valid delay TpC*(1/2+WDS)-16 ns

T

dDSR

(DS) Data to DSN↑ hold time 0 ns

T

hDR

(A) DSN↑ to address active delay TpC/2 ns

T

dDS

(AS) DSN↑ to ASN↓ delay TpC/2 + 6 ns

T

hDS

(AS) R/WN setup time before ASN↑ TpC*(1/2 + WAS) - 8 ns

T

sRW

(RW) DSN↑ to R/WN and address not valid delay TpC/2 ns

T

dDSR

(DSW) Write data valid to DSN↓ delay (write) 0 ns

T

dDW

(DW) Data hold time after DSN↑ (write) TpC/2 ns

T

hDS

(DR) Address valid to data valid delay (read) TpC*(3/2+WDS+WAS)-14 ns

T

dA

TpC is the INTCLK clock period.

DSN low level pulse width (read) TpC*(1/2+WDS)-6 ns
DSN low level pulse width (write) TpC*(1/2+WDS)-6 ns

typ max

Value Unit

SPI TIMING TABLE

(VDD= 5V +/-10%; TA= 0 to 70°C; Cload= 50pF)

Symbol Parameter Condition

T
T
T
T
T
T

sDI
hDI
dOV
hDO
wSKL
wSKH

Input Data Set-up Time tbd ns
Input Data Hold Time (1) OSCIN/2 as internal Clock 1INTCLK +100ns ns
SCK to Output Data Valid tbd ns
Output Data Hold Time tbd ns
SCK Low Pulse Width tbd ns
SCK High Pulse Width tbd ns

Value

min max

Unit

(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.

SKEW CORRECTOR TIMING TABLE

(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified)

Symbol Parameter Conditions

T

jskw

(*) TheOSD jitteris measured from leading edgeto leading edge of asingle character rowon consecutive TV lines. The value is an envelope
of 100 fields

Jitter on RGB output 36 MHz Skew corrector clock frequency 5* ns

14/18

max

Value

Unit

ST92R195B - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS (Cont’d)
OSD DAC CHARACTERISTICS

(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified).

Symbol Parameter Conditions

Output impedance: FB,R,G,B 300 500 700 Ohm
Output voltage: FB,R,G,B

Cload= 20pF

RL = 100K
code= 111 1.000 V
code= 011 0.459 0.509 V
code= 000 0.025 0.050 V
FB= 1 2.4 3.0 4.0 V
FB= 0 0 0.025 0.050 V
Global voltage accuracy +/-5 %

A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified

Symbol Parameter

T

low

T

high

T

ext

T

str

T

low

T

high

T

ext

T

str

Pulse Width
Pulse Distance ns
Period/fast Mode
Start Conversion Delay 0.5 1.5 INTCLK

Pulse Width ns
Pulse Distance ns
Period/fast Mode µs
Start Conversion Delay ns

Core Clock issued by Timing Controller

OSCIN divide by

2;min/max

min typical max

OSCIN divide

by 1; min/max

Value

Value

min max

1.5

INTCLK

78+1

INTCLK

Unit

Unit

ns

µs

15/18

ST92R195B - ELECTRICAL CHARACTERISTICS

A/D CONVERTER. ANALOG PARAMETERS TABLE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Parameter

typ (*) min max (**)

Analog Input Range V

Value Unit

SS

V

DD

V
Conversion Time Fast/Slow 78/138 INTCLK (1,2)
Sample Time Fast/Slow 51.5/87.5 INTCLK (1)
Power-up Time 60 µs
Resolution 8 bits
Differential Non Linearity 1.5 2.5 LSBs (4)
Integral Non Linearity 2 3 LSBs (4)
Absolute Accuracy 2 3 LSBs (4)
Input Resistance 1.5 Kohm (3)
Hold Capacitance 1.92 pF

Notes: (*) The values are expected at 25 Celsius degrees with VDD=5V

(**) ’LSBs’, as used here, as a value of
(1) @ 24 MHz external clock
(2) including Sample time
(3) it must be considered as the on-chip series resistance before the sampling capacitor
(4) DNL ERROR= max {[V(i) -V(i-1)] / LSB-1} INL ERROR= max {[V(i) -V(0)] / LSB-i}

ABSOLUTE ACCURACY= overall max conversion error

V

/256

DD

Note

16/18

3 GENERAL INFORMATION

3.1 PACKAGE MECHANICAL DATA
Figure 5. 80-Pin Plastic Quad Flat Package

ST92R195B - GENERAL INFORMATION

0.10mm
.004

seating plane

PQFP080

3.2 ORDERING INFORMATION

Sales Type OSD

ST92R195B9Q1 50/60 or 100/120 Hz 0-70°C PQFP80

Temperature

Range

Dim

A 3.40 0.134
A1 0.25 0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120

B 0.30 0.45 0.012 0.018

C 0.13 0.23 0.005 0.009

D 22.95 23.20 23.45 0.904 0.913 0.923
D1 19.90 20.00 20.10 0.783 0.787 0.791
D3 18.40 0.724

E 16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551 0.555
E3 12.00 0.472

e 0.80 0.031

K 0° 7°

L 0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063

N80 ND24NE16

mm inches

Min Typ Max Min Typ Max

Number of Pins

Package

17/18

ST92R195B - GENERAL INFORMATION

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor forany infringement of patents or otherrights ofthirdpartieswhich may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2

Purchase of I

Australia - Brazil - China - Finland - France -Germany - Hong Kong -India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an

2

I

C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.

2000 STMicroelectronics - All Rights Reserved.

STMicroelectronics Group of Companies

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