Datasheet ST92P141K4M6, ST92P141K4B6, ST92P141 Datasheet (SGS Thomson Microelectronics)

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Page 1

October 2001 1/179

Rev. 1.7

ST92141

8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL

■ Register File based 8/16 b it Core Architecture

with RUN, WFI, SLOW, HALT and STOP modes

■ 0-25 MHz Operation (internal clock) @ 5V±10%

voltage range

■ -40°C to +85°C Operating Temperature Range

■ Fully Programmable PLL Clock Generator, with

Frequency Multiplication and low frequency, low cost external crystal (3-5 MHz)

■ Minimum Instruction Cycle time: 160 ns - (@ 25

MHz internal clock frequency)

■ Internal Memory:

– EPROM/OTP/FA STR OM 16K bytes – RAM 512 bytes

■ 224 general purpose registers available as RAM,

accumulators or index pointers (register file)

■ 32-pin Dual Inline and 34-pin Small Outline

Packages

■ 15 programmable I/O pins wi th Schmitt Trigger

input, including 4 high sink outputs (20mA @ V

=3V)

■ 4 Wake-up Interrupts (one usable as Non-

Maskable Interrupt) for emergency event management

■ 3-phase Induction Motor Controller (IMC)

Peripheral with 3 pairs of PWM outputs and asynchronous emergency stop

■ Serial Peripheral Interface (SPI) with Master/

Slave Mode capability

■ 16-bit Timer with 8-bit Prescaler usable as a

Watchdog Timer

■ 16-bit Standard Timer with 8-bit Prescaler

■ 16-bit Extended Function Timer with Prescaler, 2

Input Captures and 2 Output Compares

■ 8-bit Analog to Di gital Converter allow ing up to

6 input channels with autoscan and watchdog capabili ty

■ Low Voltage Detector Reset

■ Rich Instruction Set with 14 Addressing Modes

■ Division-by-Zero trap generation

■ Versatile Development Tools, including

Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third Parties

DEVICE SUMMARY

DEVICE

Program

Memory

(Bytes)

RAM

(Bytes)

PACKAGE

ST92P141 16K FASTROM 512

PSDIP32/

SO34

ST92E141 16K EPROM 512 CSDIP32W ST92T141 16K OTP 512

PSDIP32/

SO34

PSDIP32

SO34 Shrink

CSDIP32W

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2/179

Table of Contents

179

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.4 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.5 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.6 3-ph ase Induction Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.7 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.8 Standard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.9 Ex tended Funct ion Time r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.11 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.1 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.2 I/O Port Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.3.1 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.3.2 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3.3 Reg ister Pointing Techn iques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.5 Mode Regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.1 DPR[ 3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.7.4 DMASR: DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Table of Contents

3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.3 Sim ultaneou s Inte rrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.9 NMI/WKP0 LINE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.9.1 NMI/Wake-Up Event Handling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.9.2 NMI/Wake-Up Event Handling in STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.9.3 Unused Wake Up Management Unit lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.10INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.11INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.12WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 55

3.12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.12.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.12.4 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4 EM CONFIGURATION REGISTERS (EM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.1 PLL Clock Multiplier Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.2 CPU Clock Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.6.1 Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.7 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.8 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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6.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.1.2 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.4 WDT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2.2 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.3.3 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.3.4 Inte rrupt Managem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.4 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.4.3 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.4.4 T acho Count er Operating mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4.5 IMC Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4.6 IMC Output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.4.7 NM I manage men t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.3 G eneral Descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.4 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.5.5 Inte rrupt Managem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.6 ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

7.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

7.6.2 F unctional Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

7.6.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

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Table of Contents

9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

9.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

9.3 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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ST92141 - GENER AL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92141 microcontroller is developed and manufactured by STMicroelec tronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks al lowing critical application tasks to get the m aximum use of core resources. The new-generation ST9 MCU devices now also support low power co nsump tion and low voltage operation for power-efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt controller, and the Memory Management Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a sing le linear space.

Four independent buses are controlled by the Core: a 16-bit memory bus, an 8 -bit register data bus, an 8-bit register address bus and a 6-bit interrupt bus which connects the interrupt controllers in the on-chip peripherals with the core.

Note: The DMA features of the ST9+ core are not used by the on-chip peripherals of the ST92141.

This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals.

The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.

1.1.2 Power Savin g Modes

To optimize performance versus power consumption, a range of operating modes can be dynamically selected by software according to the requirements of the application.

Run Mode. This is the f ull s pee d execution mod e with CPU and peripherals running at the maximum clock speed delivered either by the Phase Locked Loop controlled by the RCCU (Reset and Clock Control Unit), directly by the oscillator or by an ex-

ternal source (dedicated Pin or Alternate Function).

Slow Mode. Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and RCCU Clock Divider.

Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral with interrupt capability and interrupt controller are kept running at a frequency that can be programmed by software in the RCCU registers. In this mode, the power consumption of t he device can be reduced by more than 95% (Low Power WFI).

Halt Mode. When executing the HALT instruction, and if the Watchdo g is not enab led, the CP U and its peripherals stop operating. If however the Watchdog is enabled, the HALT instruction has no effect. The main difference between Halt mode and Stop mode is that a reset is necessary to exit from Halt mode which causes the system to be reinitialized.

Stop Mode. When Stop mode is requested by executing the STOP sequenc e (see Wake-up Management Unit section), the CPU and the peripherals stop operating. Operations resume after a wake-up line is activated. The difference between Stop mode and Halt mode is in the way the CPU exits each state: when the STO P sequence is executed, the status of the registers is recorded, and when the system exits from Stop mo de the CPU continues execution with the s am e status, without a system reset.

The Watchdog count er, if enable d, is stop ped. A fter exiting Stop mode it restarts counting from where it left off.

When the MCU exits from STOP mode, the oscillator, which was also s leeping, requi res a start-up time to restart working properly. An internal counter is present to guarantee that, after e xiting Stop Mode, all operations take place with the clock stabilised.

1.1.3 System Clock

A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 25MHz.

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ST92141 - GENERAL DESCRIPTION

1.1.4 Low Voltage Reset

The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD works both during power-on as well as when the power supply drops (brown-out). The reference value for the voltage drop is lower than the reference value for p oweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

1.1.5 I/O Ports

The I/O lines are grouped into two I/O Ports and can be configured on a bit basis to provide timing, status signals, an address/data bus for timer inputs and outputs, analog inputs, external wake-up lines and serial or parallel I/O.

1.1.6 3-phase Induction Motor Controll er

The IMC controller is designed f or variable spee d motor control applications. Three pairs of PWM outputs ar e availa ble fo r contro lling a three-ph as e motor drive. Rotor speed feedba ck is provided by capturing a tachogenerator input signal. Emergency stop is provided by putting the PWM outputs in high impedance m ode upon asynchronous faulty event on NMI pin.

1.1.7 Watchdog Timer (WDT)

The Watchdog timer can be used to m onitor system integrity. When enabled, it generates a reset after a timeout period unless the counter is refreshed by the application software. For additional security, watchdog function can be enabled by hardware using a specific pin.

1.1.8 Standard Timer

The standard timer includes a programmable 16bit down-counter and an associated 8-bit prescaler with Single and Continuous counting modes.

1.1. 9 E x tended Function Timer

The Extended Func tion Timer can be used for a wide range of standard timing tasks. It has a 16-bit free running counter with programmable prescaler. Each timer can have up to 2 input capture and 2 output compare pins wi th associated registers. This allows applications to measure pulse intervals or generate pulse waveforms. Timer overflow and other events are f lagged in a status register with optional interrupt generation.

1.1.10 Serial Peripheral Interface (SPI)

The SPI bus is used to communicate with external

devices via the SPI, or I²C bus communication standards.

1.1.11 Analog/Digital Converter (ADC)

The ADC provides up to 6 an alog inputs with onchip sample and hold. The analo g watchdog generates an interrupt when the i nput voltage moves out of a preset threshold.

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ST92141 - GENER AL DESCRIPTION

Figure 1. ST92141 Block Diagram

256 bytes

ST9+ CORE

8/16-bit

CPU

Interrupt

Management

MEMORY BUS

RCCU + LVD

WATCHDOG

MISO MOSI SCK SSN

EF TIMER

SPI

IMC

TACHO UH UL VH VL WH WL

STIN

STOUT

All alternate functions (

Italic characters

) are mapped on Port3 and Port5

Fully Prog.

I/Os

P3[6:0] P5[7:0]

NMI

WKUP[3:0]

INT0 INT6

OSCIN

OSCOUT

RESET

INTCLK

CK_AF

RAM

512 bytes

EPROM/

FASTROM

16K

A/D Converter

with analog

watchdog

AIN[7:2] EXTRG

WDIN WDOUT

STIM TIMER

ICAP1

OCMP1

ICAP2

OCMP2

EXTCLK

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ST92141 - GENERAL DESCRIPTION

1.2 PIN DESCRI PTION

ST92E141

134

1817

TACHO VH VL WH WL UH UL N.C. V

P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN V

PSDIP32/CSDIP32W Package

SO34 Package

ST92E141

132

TACHO VH VL WH WL UH UL V

P5.0/WKUP1/ICAP2 P5.1/NMI/WKUP0 RESET OSCOUT OSCIN V

MOSI/P3.0 MISO/P3.1

SCK/STIN/WKUP3/P3.2

STOUT/SSN/P3.3

EXTRG/OCMP2/P3.4

INT6/OCMP1/P3.5

ICAP1/WKUP2/P3.6

INTCLK/AIN7/P5.7

CK_AF/AIN6/P5.6

AIN5/P5.5 AIN4/P5.4

AIN3/EXTCLK/WDO UT/ P5.3

AIN2/INT0/WDIN/P5.2

MOSI/P3.0 MISO/P3.1

SCK/STIN/WKUP3 /P 3.2

STOUT/SSN/P3.3

EXTRG/OCMP2/P3.4

INT6/OCMP1/P3.5

ICAP1/WKUP2/P3.6

N.C.

INTCLK/AIN7/P5.7

CK_AF/AIN6/P5.6

AIN5/P5.5 AIN4/P5.4

AIN3/EXTCLK/W DO UT/P5.3

AIN2/INT0/WDIN/P5.2

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ST92141 - GENER AL DESCRIPTION

Table 1. Power Supply Pins Table 2. Primary Function pins

Name Function

SDIP32

SO34

Programming voltage for EPROM/OTP devices. Must be connected to V

in user mode.

24 25

Main power supply voltage (5V ± 10% (2 pins internally connected)

17 18

Digital Circuit Ground (2 pins internally connected)

18 19 32 34

Analog V

of the Analog to Digit-

al Converter

910

Analog V

of the Analog to Digit-

al Converter

10 11

Name Function

SDIP32

SO34

TACHO

Signal input from a tachogenerator to the IMC controller for measuring the rotor speed

31 33

UH U-phase PWM output signal 26 28 VH V-phase PWM output signal 30 32 WH W-phase PWM output signal 28 30 UL The complemented UH, VH, WH

output signals with added dead time to avoid crossover conduction from the power driver

25 27 VL 29 31 WL 27 29

RESET

Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET

, program execution begins from the memory location pointed to by the vector contained in memory locations 00h and 01h

21 22

OSCIN

OSCIN is the input of the oscillator inverter and internal clock generator. OSCIN and OSCOUT connect a parallel-resonant crystal (3 to 5 MHz), or an external source to the on-chip clock oscillator and buffer

19 20

OSCOUT

OSCOUT is the output of the oscillator inverter

20 21

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ST92141 - GENERAL DESCRIPTION

1.2.1 I/O Port Configuration

All ports can be individually configured as input, bidirectional, output, or alternate function. Refer t o the Port Bit Configuration Table in the I/O Port Chapter.

All I/Os are implemented with a High Hysteresis or Standard Hysteresis Schmitt trigger function (See Electrical Characteristics).

Weak Pull-Up = This column indicat es if a weak pull-up is present or not (refer to Table 3).

– If WPU = yes, then the WPU can be enabled/dis-

able by software

– If WPU = no, then enabling the WPU by software

has no effect

All port output configurations can be software selected on a bit basis to provide push-pull or open drain driving capabilities. For all ports, when configured as open-drain, the voltage on the pin must never exceed the V

power line value (refer to

Electrical characteristics section).

1.2.2 I/O Port Reset State

I/Os are reset asynchronously as soon as the RESET pin is asserted low.

All I/Os are forced by the Reset in "floating input" configuration mode.

WARNING

When a com mon p in is de clared to be connect ed to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always inputs to the alternate funct ion module declared as input.

When any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. When a given pin is declared to be connected to an analog alternate function input (ADC input for example) and if this pin is programmed in the "AF-OD" mode, the digital input path is disconnected from the pin t o prevent any DC consumption.

Table 3. I/O Port Characteristics

Legend: OD = Open Drain; HC= High current

Input Output Weak Pull-Up Reset State

Port 3[4:0] Port 3[6:5]

Schmitt trigger (High Hysteresis) Schmitt trigger (High Hysteresis)

Push-Pull/OD Push-Pull/OD (HC)

Yes Yes

Floating input

Floating input Port 5.0 Port 5.1 Port 5.2 Port 5[7:3]

Schmitt trigger (High Hysteresis) Schmitt trigger (High Hysteresis) Schmitt trigger (Standard Hysteresis) Schmitt trigger (Standard Hysteresis)

Push-Pull/OD (HC) Push-Pull/OD Push-Pull/OD (HC) Push-Pull/OD

Yes Yes Yes Yes

Floating input

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ST92141 - GENER AL DESCRIPTION

Table 4. ST92141 Alternate functions

How to confi gure the I/O por ts

To configure the I/O ports, use the information in

Table 3 and Table 4 and the Port Bit Configuration

Table in the I/O Ports Chapter on page 81.

I/O no te = The hardware characteristics fixed for each port line in Table 3.

All I/O inputs have Sch mitt trigger fixed by hardware so selecting CMOS or TTL input by software

has no effect, the input will always be Schmitt Trigger. In particular, the Schmitt Triggers present on the P5[7:2] pins have a standard hysteresis whereas the remaining pins have Schmitt Triggers with High Hysteresis (refer to Electrical Specifications).

Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time:

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

SDIP32 PSO34

P3.0

All ports useable for general purpose I/O (input, output or bidirectional)

2 2 MOSI I/O SPI Master Output/Slave Input Data

P3.1 3 3 MISO I/O SPI Master Input/Slave Output Data

P3.2 4 4

WKUP3 I Wake-up line 3 STIN I Standard Timer Input SCK I/O SPI Serial Clock Input/Output

P3.3 5 5

SSN I SPI Slave Select STOUT O Standard Timer Output

P3.4 6 6

EXTRG I A/D External trigger OCPM2 O Ext. Timer Output Compare 2

P3.5 7 7

INT6 I External Interrupt 6 OCMP1 O Ext. Timer - Output Compare 1

P3.6 8 8

ICAP1 I Ext. Timer - Input Capture 1 WKUP2 I Wake-up line 2

P5.0 23 2 4

ICAP2 I Ext. Timer - Input Capture 2 WKUP1 I Wake-up line 1

P5.1 22 2 3

NMI I Not maskable Int. WKUP0 I Wake-up line 0

P5.2 16 1 7

AIN2 I Analog Data Input 2 INT0 I External Interrupt 0 WDIN I Watchdog input

P5.3 15 16

AIN3 I Analog Data Input 3 EXTCLK I Ext. Timer - Input Clock

WDOUT O Watchdog Output P5.4 14 15 AIN4 I Analog Data Input 4 P5.5 13 14 AIN5 I Analog Data Input 5

P5.6 12 13

AIN6 I Analog Data Input 6

CK_AF I Clock Alternative Source

P5.7 11 12

AIN7 I Analog Data Input 7

INTCLK O Internal Main Clock

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ST92141 - GENERAL DESCRIPTION

An alternate function can be selected as follows. AF Inputs:

– AF is selected implicitly by enabling the corre-

sponding peripheral. Exceptions to this are ADC analog inputs which must be explicitly selected

as AF by software. AF Outputs or Bidirectional Lines: – In the case of Outputs or I/Os, AF is selected ex-

plicitly by sof twar e.

Example 1: Standard Timer input

AF: STIN, Port: P3.2, I/O Note: Schmitt trigger. Write the port configuration bits: P3C2.2=1 P3C1.2=0 P3C0.2=1 or P3C2.2=0 P3C1.2=0 P3C0.2=1

Enable the Standard T imer input by softw are as described in the STIM chapter.

Example 2: Standard Timer output AF: STOUT, Port: P3.3 Write the port configuration bits (for AF output

push-pull): P3C2.3=0 P3C1.3=1 P3C0.3=1

Example 3: ADC analog input AF: AIN2, Port: P5.2, I/O Note: doe s not apply to

analog inputs Write the port configuration bits: P5C2.2=1 P5C1.2=1 P5C0.2=1

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ST92141 - GENER AL DESCRIPTION

1.3 MEMORY MA P

1.3.1 Memory Configuration

The Program memory space of the ST92141, 16K bytes of directly addressable on-chip m emory, is fully available to the user.

The first 256 memory locat ions from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predetermined function except segm ent 21h which is reserved for use by STMicroelectronics.

1.3.2 EPROM Programming

The 16K bytes of EPROM memory of the ST92E141 may be programmed by using the EPROM Programming Boards (EPB) or gang programmers available from STMicroelectronics.

EPROM Erasing

The EPROM of the windowed package of the ST92E141 may be erased by exposure to Ultra-Violet light.

The erasure characteristic of the ST92E141 is such that erasure begins when the memory is exposed to light with a wave lengths shorter than ap-

proximately 4000Å. It should be noted that sunlight

and some types of fluorescent lam ps have wavelengths in the range 3000-4000Å. It is thus recommended that the window of the ST92E141 packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment.

The recommended erasure procedure of the EPROM is the exposure to short wave ultraviolet light which have a wave-lengt h 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 30 minutes using an ultraviolet lamp with 12000mW/cm2 power rating. The ST92E141 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure.

Table 5. First 6 Bytes of Program Space

Figure 2. Me m ory Map

0 Address high of Power on Reset routine 1 Address low of Power on Reset routine 2 Address high of Divide by zero trap Subroutine 3 Address low of Divide by zero trap Subroutine 4 Address high of Top Level Interrupt routine 5 Address low of Top Level Interrupt routine

SEGMENT 0

64 Kbytes

00FFFFh 00C000h

00BFFFh 008000h

007FFFh 004000h

000000h

003FFFh

PAGE 0 - 16 Kb y tes

PAGE 1 - 16 Kb y tes

PAGE 2 - 16 Kb y tes

PAGE 3 - 16 Kb y tes

SEGMENT 20h

64 Kbytes

200000h

21FFFFh

20C000h 20BFFFh

208000h 207FFFh

204000h 203FFFh

PAGE 80 - 16 Kbytes

PAGE 81 - 16 Kbytes

PAGE 82 - 16 Kbytes

PAGE 83 - 16 Kbytes

200000h

200200h

RAM

512 bytes

Internal

Reserved

SEGMENT 21h

64 Kbytes

20FFFFh

220000h

210000h

Internal ROM

Reserved Reserved

Reserved

max. 64 Kbytes

000000h

004000h

FASTROM/EPROM

16 Kbytes

003FFFh

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ST92141 - GENERAL DESCRIPTION

1.4 REGISTER MAP

The following pages contain a list of ST92141 registers, grouped by peripheral or function.

Be very careful to correctly program both:

– The set of registers dedicated to a particular

function or peripheral. – Registers common to other functions. – In particular, double-check that any registers

with “undefined” reset values have been correct-

ly initial is ed. WARNING: Note that in the EIVR and each IVR

register, all bits are significant. Take care when defining base vector ad dresses that en tries in the Interrupt Vector table do not overlap.

Table 6. Common Registers

Function or Peripheral Common Registers

ADC CICR + NICR + I/O PORT REGISTERS WDT

CICR + NICR + EXTERNAL INTERRUPT REGISTERS + I/O PORT REGISTERS

I/O PORTS I/O PORT REGISTERS + MODER

EXTERNAL INTERRUPT INTERRUPT REGISTERS + I/O PORT REGISTERS

RCCU INTERRUPT REGISTERS + MODER

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ST92141 - GENER AL DESCRIPTION

Table 7. G roup F Pages

Resources available on the ST92141 devices:

0 2 3 7 11 21 28 48 51 55 57 63

R255

Res.

Res. Res.

Res.

EFT0

IMC

Res.

A/D0

R254

PORT

R253

R252

WCR

R251

WDT

Res.

R250

R249

MMU

R248

Res.

R247

EXT

INT

Res.

R246

PORT

RCCU

R245

Res.R244

MMU

R243

Res. SPI0 STIM0

R242

RCCU

R241

Res.

R240

RCCU

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ST92141 - GENERAL DESCRIPTION

Table 8. Detailed Register Map

Page

(Decimal)

Block

Reg.

No.

Name

Description

Reset Value

Hex.

Doc.

Page

N/A

Core

R230 CICR Central Interrupt Control Register 87 52 R231 FLAGR Flag Register 00 24 R232 RP0 Pointer 0 Register xx 26 R233 RP1 Pointer 1 Register xx 26 R234 PPR Page Pointer Register xx 28 R235 MODER Mode Register E0 28 R236 USPHR User Stack Pointer High Register xx 30 R237 USPLR User Stack Pointer Low Register xx 30 R238 SSPHR System Stack Pointer High Reg. xx 30 R239 SSPLR System Stack Pointer Low Reg. xx 30

I/O

Port

5:4,2:0

R224 P0DR Port 0 Data Register FF

R225 P1DR Port 1 Data Register FF R226 P2DR Port 2 Data Register FF R228 P4DR Port 4 Data Register FF R229 P5DR Port 5 Data Register FF

INT

R242 EITR External Interrupt Trigger Regis ter 00 52 R243 EIPR External Interrupt Pending Reg. 00 53 R244 EIMR External Interrupt Mask-bit Reg. 00 53 R245 EIPLR External Interrupt Priority Level Reg. FF 53 R246 EIVR External Interrupt Vector Regis ter x6 54 R247 NICR Nested Interrupt Control 00 54

WDT

R248 WDTHR Watchdog Timer High Register FF 90 R249 WDTLR Watchdog Timer Low Register FF 90 R250 WDTPR Watchdog Timer Prescaler Reg. FF 90 R251 WDTCR Watchdog Timer Control Register 12 90 R252 WCR Wait Control Register 7F 91

I/O

Port

R252 P3C0 Port 3 Configuration Register 0 00

R253 P3C1 Port 3 Configuration Register 1 00 R254 P3C2 Port 3 Configuration Register 2 00

I/O

Port

R244 P5C0 Port 5 Configuration Register 0 FF R245 P5C1 Port 5 Configuration Register 1 00 R246 P5C2 Port 5 Configuration Register 2 00

7SPI

R240 SPDR SPI Data Register 00 145 R241 SPCR SPI Control Register 00 145 R242 SPSR SPI Status Register 00 146 R243 SPPR SPI Prescaler Register 00 146

11 STIM

R240 STH Counter High Byte Register FF 95 R241 STL Counter Low Byte Register FF 95 R242 STP Standard Timer Prescaler Register FF 95 R243 STC Standard Timer Control Register 14 95

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ST92141 - GENER AL DESCRIPTION

MMU

R240 DPR0 Data Page Register 0 xx 35 R241 DPR1 Data Page Register 1 xx 35 R242 DPR2 Data Page Register 2 xx 35 R243 DPR3 Data Page Register 3 xx 35 R244 CSR Code Segment Register 00 36 R248 ISR Interrupt Segment Register xx 36 R249 DMASR DMA Segment Register xx 36

R245 EMR1 EM Register 1 80 62 R246 EMR2 EM Register 2 0F 62

28 EFT

R240 IC1HR Input Capture 1 High Register xx 108 R241 IC1LR Input Capture 1 Low Register xx 108 R242 IC2HR Input Capture 2 High Register xx 108 R243 IC2LR Input Capture 2 Low Register xx 108 R244 C HR Counter High Register FF 109 R245 C LR Counter Low Register FC 109 R246 ACHR Alternate Counter High Register FF 109 R247 ACLR Alternate Counter Low Register FC 109 R248 OC1HR Output Compare 1 High Register 80 110 R249 OC1LR Output Compare 1 Low Register 00 110 R250 OC2HR Output Compare 2 High Register 80 110 R251 OC2LR Output Compare 2 Low Register 00 110 R252 CR1 Control Register 1 00 111 R253 CR2 Control Register 2 00 112 R254 SR Status Register 00 113 R255 CR3 Control Register 3 00 113

48 IMC

R248 PCR0 Peripheral Control Register 0 80 130 R249 PCR1 Peripheral Control Register 1 00 130 R250 PCR2 Peripheral Control Register 2 00 131 R251 PSR Polarity Selection Register 00 131 R252 OPR Output Peripheral Register 00 132 R253 IMR Interrupt Mask Register 00 132 R254 DTG Dead Time Generator Register 00 133 R255 IMCIVR IMC Interrupt Vector Register xx 133

Page

(Decimal)

Block

Reg.

No.

Name

Description

Reset Value

Hex.

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ST92141 - GENERAL DESCRIPTION

Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details.

51 IMC

R240 TCPTH Tacho Capture Register High xx 125 R241 TCPTL Tacho Capture Register Low xx 125 R242 TCMP Tacho Compare Register xx 125 R243 ISR Interrupt Status Register 3F 36 R244 TPRSH Tacho Prescaler Register High 00 127 R245 TPRSL Tacho Prescaler Register Low 00 127 R246 CPRS PWM Counter Prescaler Register 00 127 R247 REP Repetition Counter Register 00 127 R248 CPWH Compare Phase W Preload Register High 00 128 R249 CPWL Compare Phase W Preload Register Low 00 128 R250 CPVH Compare Phase V Preload Register High 00 128 R251 CPVL Compare Phase V Preload Register Low 00 128 R252 CPUH Compare Phase U Preload Register High 00 129 R253 CPUL Compare Phase U Preload Register Low 00 129 R254 CP0H Compare 0 Preload Register High 00 129 R255 CP0L Compare 0 Preload Register Low 00 129

55 RCCU

R240 CLKCTL Clock Control Register 00 69 R242 CLK_FLAG Clock Flag Register 48, 28 70 R246 PLLCONF PLL Configuration Register xx 71

57 WUIMU

R249 WUCTRL Wake-Up Control Register 00 59 R250 WUMRH Wake-Up Mask Register High 00 60 R251 WUMRL Wake-Up Mask Register Low 00 60 R252 WUTRH Wake-Up Trigger Register High 00 61 R253 WUTRL Wake-Up Trigger Register Low 00 61 R254 WUPRH Wake-Up Pending Register High 00 61 R255 WUPRL Wake-Up Pending Register Low 00 61

63 ADC

R240 D0R Channel 0 Data Register xx 151 R241 D1R Channel 1 Data Register xx 151 R242 D2R Channel 2 Data Register xx 151 R243 D3R Channel 3 Data Register xx 151 R244 D4R Channel 4 Data Register xx 151 R245 D5R Channel 5 Data Register xx 151 R246 D6R Channel 6 Data Register xx 151 R247 D7R Channel 7 Data Register xx 151 R248 LT6R Channel 6 Lower Threshold Reg. xx 152 R249 LT7R Channel 7 Lower Threshold Reg. xx 152 R250 UT6R Channel 6 Upper Threshold Reg. xx 152 R251 UT7R Channel 7 Upper Threshold Reg. xx 152 R252 CRR Compare Result Register 0F 153 R253 CLR Control Logic Register 00 154 R254 ICR Interrupt Control Register 0F 155 R255 IVR Interrupt Vector Register x2 155

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(Decimal)

Block

Reg.

No.

Name

Description

Reset Value

Hex.

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ST92141 - DEVICE ARCHITECTURE

2 DEVICE ARCHITECTURE

2.1 CORE ARCHITECTURE

The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available.

Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bi t Registe r data bus, an 8-bit Register ad dress bus an d a 6-bit Interrupt/DMA bus which connect s th e in terrupt an d DMA controllers in the on-chip peripherals with the Core.

This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources.

2.2 MEMORY SPACES

There are two separate memory spaces:

– The Register File, which comprises 240 8-bit

registers, arranged as 15 groups (Group 0 to E), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in Group F,

which hold data and control bits for the on-chip

peripherals and I/Os. – A sing le linear memory space acc ommodating

both program and data. All of the physically sep-

arate memory areas, including the internal ROM,

internal RAM and ex ternal memory are mapped

in this common address space. The total ad-

dressable memory space of 4 Mbytes (limited by

the size of on-chip memory and the number of

external address pins) is arranged as 64 seg-

ments of 64 Kbytes. Each segment is further

subdivided into four pages of 16 Kbytes, as illus-

trated in Figure 3. A Memory Man agement Unit

uses a set of pointer registers to address a 22-bit

memory field using 16-bit address-based instruc-

tions.

2.2.1 Reg ister File

The Register File consists of (see Figure 4): – 224 general purpose registers (Group 0 to D,

registers R0 to R223) – 6 system registers in the System Group (Group

E, registers R224 to R239) – Up to 64 pages, depending on device configura-

tion, each containing up to 16 registers, mapped

to Group F (R240 to R255), see Figure 5.

Figure 3. Single Program and Data Memory Address Spac e

3FFFFFh

3F0000h 3EFFFFh

3E0000h

20FFFFh

02FFFFh 020000h

01FFFFh 010000h

00FFFFh 000000h

8 7 6 5 4 3 2 1 0

Address 16K Pages 64K Segments

up to 4 Mbytes

Data

Code

255 254 253 252 251 250 249 248 247

21FFFFh 210000h

133

134

135

Reserved

132

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ST92141 - DEVICE ARCHITECTURE

MEMORY SPACES (Cont’d) Figure 4. Regis te r Gr oups Figure 5. Pag e Pointer for Group F m apping

Figure 6. Addressing the Register File

F E D C B A 9 8 7 6 5 4 3

PAGED REGISTERS

SYSTEM REGISTER S

255 240

239 224 223

VA00432

UP TO

64 PAGES

GENERAL

REGISTERS

PURPOSE

224

PAGE 63

PAGE 5

PAGE 0

PAGE POINT ER

R255

R240

R224

VA00433

R234

SYSTEM REGISTER S

GROU P D

GROUP B

GROUP C

(1100)

(0011)

R192

R207

255 240

239 224 223

F E

D C B A 9 8 7 6 5 4 3 2 1 0

VR000118

R195

(R0C3h)

PAGED REGISTERS

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ST92141 - DEVICE ARCHITECTURE

MEMORY SPACES (Cont’d)

2.2.2 Register Addressing

Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see

Figure 6). Group D registers can only be ad-

dressed in Working Register mode. Note that an upper case “R” is used to denote this

direct addressing mode.

Working Re gi st ers

Certain types of instruction require that registers be specified in the form “rx”, where x is in the range 0 to 15: these are known as Working Registers.

Note that a lower case “r” is used to denote this indirect addressing mode.

Two addressing schemes are av ailable: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 2.3.3 Register Pointing Techniques, and illustrated in

Figure 7 and in Figure 8.

System Registers

The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. Thes e registers are described in greater detail in Section 2.3 SYSTEM REGISTER S.

Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to G roup F. These are add ressed using any register addressing mode, in conjunctio n with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.

Therefore if the Page Pointer, R234, is set to 5, the instructions:

spp #5 ld R242, r4

will load the contents of working register r4 into the third register of page 5 (R242).

These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the sam e pages and registers to ensure code com patibility between ST9 devices. The number of these registers therefore depends on the peripherals which are present in the s pecific ST9 family device. In other words, pages only exist if the relevant peripheral is present.

Table 9. Register File Organization

Hex.

Address

Decimal

Address

Function

File Group

F0-FF 240-255

Paged

Registers

Group F

E0-EF 224-239

System

Registers

Group E

D0-DF 208-223

General

Purpose

Registers

Group D C0-CF 192-207 Group C B0-BF 176-191 Group B A0-AF 160-175 Group A

90-9F 144-159 Group 9 80-8F 128-143 Group 8 70-7F 112-127 Group 7 60-6F 96-111 Group 6 50-5F 80-95 Group 5 40-4F 64-79 Group 4 30-3F 48-63 Group 3 20-2F 32-47 Group 2 10-1F 16-31 Group 1 00-0F 00-15 Group 0

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ST92141 - DEVICE ARCHITECTURE

2.3 SYSTEM REGISTERS

The System registers are listed in Table 10 Sy s-

tem Registers (Group E). They are used to per-

form all the important system settings. Their purpose is described in the following pages. Refer t o the chapter dealing with I/O for a description of the PORT[5:0] Data registers.

Table 10. System Registers (Group E)

2.3.1 Central Interrupt Control Register

Please refer to the ”INTERRUPT” chapter for a detailed description of the ST9 interrupt philosophy.

CENTRAL INTERRUPT CONTROL REGISTER (CICR)

R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h)

Bit 7 = GCEN:

Global Counter Enable

. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set after the Reset cycle.

Note: If an MFT is not included in the ST9 device, then this bit has no effect.

Bit 6 = TLIP:

Top Level Interrupt Pending

. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending

Bit 5 = TLI:

Top Level Interrupt bit

0: Top Level Interrupt is acknowledged depending

on the TLNM bit in the NICR Register.

1: Top Level Interrupt is acknowledged depending

on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter).

Bit 4 = IEN:

Interrupt Enable .

This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitl y by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no i nterrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before a ny write operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. 1: Enable Interrupts

Bit 3 = IAM:

Interrupt Arbitration Mode

. This bit is set and cleared by software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode.

Bits 2:0 = CPL[2:0]:

Current Priority Level

. These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the current interrupt is replaced by one of a higher priority, the current priority value is automatically stored until required in the NICR register.

R239 (EFh) SSPLR R238 (EEh)

SSPHR

R237 (EDh)

USPLR

R236 (ECh)

USPHR

R235 (EBh)

MODE REGISTER

R234 (EAh)

PAGE POINTER REGISTER

R233 (E9h)

R232 (E8h)

R231 (E7h)

FLAG REGISTER

R230 (E6h)

CENTRAL INT. CNTL REG

R229 (E5h)

PORT5 DATA REG.

R228 (E4h)

PORT4 DATA REG.

R227 (E3h)

PORT3 DATA REG.

R226 (E2h)

PORT2 DATA REG.

R225 (E1h)

PORT1 DATA REG.

R224 (E0h)

PORT0 DATA REG.

GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d)

2.3.2 Flag Register

The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the system stack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status.

This occurs for all interrupts and, wh en operating in nested mode, up to seven versions of the flag register may be stored.

FLAG REGISTER (FLAGR)

R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h)

Bit 7 = C :

Carry Flag

The carry flag is affected by:

Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left A r ith me t ic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws).

When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations).

The carry flag can be set by the S et Carry Flag (scf ) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Complement Carry Flag (ccf) instruction.

Bit 6 = Z:

Zero Flag

. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left A r ith me t ic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec,

decw),

Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents

of the register being used as an accumulator become zero, following one of the above operations.

Bit 5 = S:

Sign Flag

. The Sign flag is affected by the same instructions as the Zero flag.

The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one.

Bit 4 = V:

Overflow Flag

. The Overflow flag is affected by t he sa me instructions as the Zero and Sign flags.

When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two’s-complement notation.

Bit 3 = DA:

Decimal Adjust Flag

. The DA flag is used f or BCD arithm et ic. Si nce t he algorithm for correcting BCD operations i s different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequen t Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be u sed as a test condition by the programmer.

Bit 2 = H:

Half Carry Flag.

The H flag indicates a carry out of (or a borrow into) bit 3, as the resu lt of addin g or subt racti ng tw o 8-bit bytes, each representing two BCD digits. The H flag is used by the Dec imal Adjust (da) instruc- tion to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not norma lly accessed by the user.

Bit 1 = Reserved bit (must be 0).

Bit 0 = DP:

Data/Program Memory Flag

. This bit indicates the memory area addressed . Its value is affected by the Set Data Memory (sdm) and Set Program Mem ory (spm) instructions. Refer to the Memory Management Unit for further details.

C Z S V DA H - DP

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d)

If the bit is set, dat a is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR regist er); therefore, the user initialization routine must include a Sdm instruction. Note that code is always poi nted to by the Code Pointer (CSR).

Note: In the current ST9 devices, the DP flag is only for co mpatibility wit h software d eveloped for the first generation of ST9 devices. With the single memory addressing space, its us e is now redundant. It must be kept to 1 w ith a Sdm instruction at the beginning of the program to ens ure a normal use of the different memory pointers.

2.3.3 Register Pointing Techniques

Two registers within the System register group, are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces.

For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register mode.

The Set Registe r Pointer instructions srp, srp0 and srp1 automatically inform the C PU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and

specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block.

There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary i n twin 8-register mode, or on a 16-register boundary in single 16register mode.

The block number should always be an even number in single 16-re gister mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers , since this can be confusing if twin mode is subsequently selected.

Thus: srp #3 will be interpreted as srp #2 and will al-

low using R16 ..R31 as r0 .. r15. In single 16-register mode , the working registers

are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instructio n).

Caution:

Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be

addressed explicitly in the form “Rxxx”.

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d) POINTER 0 REGIST ER (RP0)

R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)

Bits 7:3 = RG[4:0]:

These bits contain the num ber (in the range 0 to

31) of the register block s pecified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped.

Bit 2 = RPS:

. This bit is set by the instructions srp0 and srp1 to indicate that the twin register po inting m ode is s elected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode

Bits 1:0: Reserved. Forced by hardware to zero.

POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)

This register is only used in the twin register pointing mode. W hen us ing t he sin gle regist er pointing mode, or when using only one of the twin regi ster groups, the RP1 register must be considered as RESERVED and may NOT be us ed as a general purpose register.

Bits 7:3 = RG[4:0]:

These bits contain the n umber (in the range 0 to

31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped.

Bit 2 = RPS:

. This bit is set by the srp0 and srp1 instructions to indicate that the twin registe r pointing mod e is s elected. The bit is reset by the srp instruction to indicate that the single register pointing mode i s selected. 0: Single register pointing mode 1: Twin register pointing mode

Bits 1:0: Reserved. Forced by hardware to zero.

RG4 RG3 RG2 RG1 RG0 RPS 0 0

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d) Figure 7. Pointing to a single group of 16

registers

Figure 8. Pointing to two groups of 8 registers

BLOCK

NUMBER

GROUP

FILE

POINTER 0

srp #2

set by:

instruction

points to:

GROUP 1

addressed by

BLOCK 2

r15

BLOCK

NUMBER

GROUP

FILE

POINTER 0

srp0 #2

set by:

instructions

point to:

GROUP 1

addressed by

BLOCK 2

& REGISTER POINTER 1

srp1 #7

GROUP 3

addressed by

BLOCK 7

r15

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d)

2.3.4 Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral a lways being associated with the same pages and registers to ensure code compa tibility bet ween ST9 devices. The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present.

The paged registers are addressed using the normal register addressing modes, in conjunction with the Page Pointer register, R234, which is on e of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.

Thus the instructions:

spp #5 ld R242, r4

will load the contents of working register r4 into the third register of page 5 (R242).

Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the interrupt routine.

PAGE POINTER REGIST ER ( PPR)

R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh)

Bits 7:2 = PP[5:0]:

Page Pointer

These bits contain the num ber (in the range 0 to

63) of the page specified in the spp instruction. Once the page pointer has been set , there is no need to refresh it unless a different page is required.

Bits 1:0: Reserved. Forced by hardware to 0.

2.3.5 Mode Regi ster

The Mode Register allows control of the following operating parameters:

– Selection of internal or external System and User

Stack areas,

– Management of the clock frequency, – Enabl ing of Bus request and Wait s ignals when

interfacing to external memory.

MODE REGISTER (MODER)

R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h)

Bit 7 = SSP:

System Stack Point er

. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File

(reset state).

Bit 6 = USP:

User Stack Pointer

. This bit selects an internal or external User S tack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (re-

set state).

Bit 5 = DIV2:

Crystal Oscillator Clock Divided by 2

. This bit controls the divide-by-2 circuit operating on the crystal oscillator clock (CLOCK1). 0: Clock divided by 1 1: Clock divided by 2

Bits 4:2 = PRS[2:0]:

CPUCLK Prescaler

. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Re set and Clock Control chapter for further information.

Bit 1 = BRQEN:

Bus Request Enable

. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on

BREQ

pin (where available).

Note: Disregard this bit if BREQ

pin is not availa-

ble.

Bit 0 = HIMP:

High Impedance Enable

. When any of Po rts 0, 1, 2 or 6 d epending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance

PP5 PP 4 PP3 PP2 PP1 P P0 0 0

SSP USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d)

state by setting the HIMP bit. When this bit is reset, it has no effect.

Setting the HIMP bit is recommended for noise reduction when only internal Memory is used.

If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP b it has no effect on the I/O lines.

2.3.6 Stack Pointers

Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memor y .

The stack pointers point to the “bottom” of the stacks which are filled us ing the pus h comma nds and emptied using the pop command s. The stack pointer is automatically pre-decremented when data is “pushed” in and post-incremented when data is “popped” out.

The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix “u”. To use a stack in- struction for a word, the suffix “w” is added. These

suffixes may be combined.

When bytes (or words) are “popped” out from a stack, the contents of the stack locat ions are unchanged until fresh data is loaded. Thus, when data is “popped” from a stack area, the stack contents remain unchanged.

Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238

& R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value.

System Stack

The System Stack is us ed for the temporary storage of system and/or control data, such as the Flag register and the Program counter.

The following automatically push data onto the System Stack:

– Interrupts When entering an interrupt, the PC and the Flag

Code Segment Re gister is also pushed onto the System Stack.

– Subroutine Cal ls When a call instruction is executed, only the PC

is pushed onto stack, where as when a calls instruction (call segment) is executed, both the PC and the Code Se gment Regist er are pushed ont o the System Stack.

– Link Instruction The link or linku instructions create a C lan-

guage stack frame of user-defined length in the System or User Stack.

All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack.

User Stack

The User Stack provides a totally user-co ntrolled stacking area .

The User Stack Pointer consists of tw o registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved.

Stack Pointers

Both System and User stacks are pointed to by double-byte stack pointers. Stacks m ay be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in t he Register File. The upper byte must then be considered as reserved and must not be used as a general purpose register.

The stack pointer registers are located in the S ystem Group of the Register File, this is illustrated in

Table 10 System Registers (Group E).

Stack Location

Care is necessary when managing stacks as there is no limit to stack sizes apart from t he bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as a stacking area.

Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks).

Note. Stacks must not be located in the Paged Register Group or in the System Register Group.

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ST92141 - DEVICE ARCHITECTURE

SYSTEM REGI STE R S (Cont’d) USER STACK POINTER HIGH REGISTER

(USPHR)

R236 - Read/Write Register Group: E (System) Reset value: undefined

USER STACK POINTER LOW REGISTER (USPLR)

R237 - Read/Write Register Group: E (System) Reset value: undefined

Figure 9. Internal Stack Mode

SYSTEM STACK POINTER HIGH REGISTER (SSPHR)

R238 - Read/Write Register Group: E (System) Reset value: undefined

SYSTEM STACK POINTER LOW REGISTER (SSPLR)

R239 - Read/Write Register Group: E (System) Reset value: undefined

Figure 10. External Stack Mode

USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8

USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0

FILE

STACK POINTER (LOW)

points to:

STACK

SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8

SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0

FILE

STACK POINTER (LOW)

point to:

STACK

MEMORY

STACK POINTER (HIGH)

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2.4 MEMORY ORGANIZATION

Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space.

The ST9 provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kb ytes; each segment is again subdivided into four 16 Kbyte pages.

The mapping of the various memo ry areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved).

Refer to the Register and Memory Map Chapter for more details on the memory map.

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2.5 MEMORY MANAGEMENT UNIT

The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used).

The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within g roup F , Pag e 21 of the Register File. The 7 registers may be

sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data M emory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).

Figure 11. Page 21 Registers

DMASR ISR

EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0

R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240

FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h

MMU

Page 21

MMU

Bit DPRREM=0

SSPLR

SSPHR

USPLR

USPHR

MODER

PPR RP1 RP0

FLAGR

CICR P5DR P4DR P3DR P2DR P1DR P0DR

DMASR

ISR

EMR2 EMR1

CSR DPR3 DPR2

DPR0

Bit DPRREM=1

SSPLR SSPHR USPLR USPHR

MODER

PPR RP1 RP0

FLAGR

CICR P5DR P4DR

P3DR P2DR P1DR P0DR

DMASR

ISR

EMR2 EMR1

CSR DPR3 DPR2 DPR1 DPR0

Relocation of P[3:0] and DPR[3:0] Registers

(default setting)

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2.6 ADDRESS SPACE EXTENSION

To manage 4 Mbytes of addressing space, it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed.

2.6.1 Addressing 16-Kbyte Pages

This extension mode is implicitly used to address Data memory space if no DMA is being performed.

The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a di fferent 16-Kbyte page. The DPR registers allow access to the entire mem ory space which contains 256 pages of 16 Kbytes.

Data paging is performed by extending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted as the identification number of the DPR register to be used. Therefore, the DPR registers

are involved in the following virtual address ranges:

DPR0: from 0000h to 3FFFh; DPR1: from 4000h to 7FFFh; DPR2: from 8000h to BFFFh; DPR3: from C000h to FFFFh.

The contents of the select ed DPR register specify one of the 2 56 p os sible data m em ory pages. This 8-bit data page num ber, in add ition t o the rem aining 14-bit page offset address forms the phy sical 22-bit address (see Figure 12).

A DPR register cannot be modified via an addressing mode that uses the same DPR register. For in-

stance, the instruction “POPW DPR0” is legal only if the stack is kept either in the register file or in a memory location above 8000h, where D PR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the in struction, unpredictable behaviour could result.

Figure 12. Addressing via DPR[3:0]

DPR0 DPR1 DPR2 DPR3

01 10 11

16-bit virtual address

22-bit physical address

8 bits

MMU registers

14 LSB

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ADDRESS SPACE EXTENSION (Cont’d)

2.6.2 Addressing 64-Kbyte Segments

This extension mode is used to address Data memory space during a DMA and Prog ram memory space during any code execution (normal code and interrupt routines).

Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 13).

2.7 MMU REGISTERS

The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register.

Most of these registers do not have a default value after reset.

2.7.1 DPR[3:0]: Data Page Registers

The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes.

2.7.1.1 Data Page Register Relocation

If these registers are to be us ed frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Regist ers, which are re-mapped to the default DPR's locations: R240-243 page 21.

Data Page Register relocation is illustrated in Fig-

ure 11.

Figure 13. Addressing via CSR, ISR, and DMASR

Fetching program

Data Memory

Fetching interrupt

instruction

accessed in DMA

instruction or DMA access to Program

Memory

16-bit virtual address

22-bit physical address

6 bits

MMU registers

CSR

ISR

DMASR

1 2 3

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MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0)

R240 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R224 if EMR2.5 is set.

Bits 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page num ber. T hey are used as the most significant address bits (A21-14) to extend the address during a Dat a Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh.

DATA PAGE REGISTER 1 (DPR1)

R241 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R225 if EMR2.5 is set.

Bits 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page num ber. T hey are used as the most significant address bits (A21-14) to extend the address during a Dat a Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh.

DATA PAGE REGISTER 2 (DPR2)

R242 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R226 if EMR2.5 is set.

Bits 7:0 = DPR2_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh.

DATA PAGE REGISTER 3 (DPR3)

R243 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R227 if EMR2.5 is set.

Bits 7:0 = DPR3_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh.

DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0

DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0

DPR2_7 DP R2_6 DPR2_5 DPR2_4 DPR2_3 DPR 2_2 DPR2_1 DPR2_0

DPR3_7 DP R3_6 DPR3_5 DPR3_4 DPR3_3 DPR 3_2 DPR3_1 DPR3_0

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MMU REGISTERS (Cont’d)

2.7.2 CSR: Code Segment Register

This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes.

To generate the 22-bit P rogram m em ory address , the contents of the CSR register is directly used as the 6 MSBs, an d the 16-bit virtual a ddress as the 16 LSBs.

Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by mean s of the rets instruction.

CODE SEGMENT REGISTER (CSR)

R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h)

Bits 7:6 = Reserved, keep in reset state.

Bits 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16).

2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR)

R248 - Read/Write Register Page: 21 Reset value: undefined

ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details.

Bits 7:6 = Reserved, keep in reset state.

Bits 5:0 = ISR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the m ost significant address bi ts (A21-16). The ISR is used to extend the address space in two cases:

– Whenever an interrupt occurs: ISR points to the

64-Kbyte memory segment containing the interrupt vector table and the interr upt service routine code. See also the Interrupts chapter.

– During DMA transactions between the peripheral

and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction.

2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGIST ER ( D MA SR)

R249 - Read/Write Register Page: 21 Reset value: undefined

Bits 7:6 = Reserved, keep in reset state.

Bits 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the address.

00CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0

0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0

DMA

SR_5

DMA SR_4

DMA SR_3

DMA

SR_2

DMA

SR_1

DMA

SR_0

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MMU REGISTERS (Cont’d) Figure 14. Memory Addressing Scheme (example)

3FFFFFh

294000h

240000h 23FFFFh

20C000h

200000h

1FFFFFh

040000h 03FFFFh

030000h 020000h

010000h

00C000h

000000h

DMASR

ISR

CSR

DPR3

DPR2

DPR1

DPR0

4M bytes

16K

16K 16K

64K

16K

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2.8 MMU USAGE

2.8.1 Normal Program Execution

Program memory is organized as a set of 64Kbyte segments. The program c an span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution bec ause it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruc tion f rom on e memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if ENCSR is re set.

Note that a routine mus t always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used.

In typical microcontroller applications, less than 64 Kbytes of RAM are us ed, so the four Dat a space pages are normally sufficient, and no change of DPR[3:0] is needed durin g Program execution. It may be useful how ever to map part of the ROM into the data space if it contains strings, tables, bit maps, etc .

If there is to be frequent use of paging, the us er can set bit 5 (DPRREM) in regi ster R246 (EMR 2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 0-

3. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused.

2.8.2 Interrupts

The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call.

When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21).

If this bit is reset (default condition), the CPU works in origi nal ST9 comp atibility mo de. For the duration of the interrupt service routine, the ISR is used instead of th e CSR, and the in terrupt stack

frame is kept exactly as in the original S T9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the c ase of an interrupt, ensuring a fast interrupt response time. The drawback is t hat it i s not poss ible fo r an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes.

If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vecto r table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs.

Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the ma in program , as in the ST9. If the interrupt service routine needs to access additional Data memory , it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion.

2.8.3 DMA

Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (whe n the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).

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3 INTERR UPTS

3.1 INTRODUCTION

The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific respo nse routine whe n such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved an d control passes to the appropriate Interrupt Service Routine (refer to Figure 15).

The ST9 CPU can rec eive requests from the following sources:

– On-chip peripherals – External pins – Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an

event occurrence can generate an Interrupt request which depends on the selected mode.

Up to eight external interrupt channe ls, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory.

Figure 15. Inte rru pt Re sponse

3.2 INTERRUPT VECTORING

The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically.

When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer).

Each peripheral has a specific IVR mappe d within its Register File pages.

The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thus allowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU.

The user Power on Reset vector is stored in the first two physical bytes in memory, 000000h and 000001h.

The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR).

With one Interrupt Vec tor regi ster, i t is pos sible to address several interrupt service routines; i n fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector.

Note: The first 256 locations of the memory segment pointed to by ISR can contain program code.

3.2.1 Divide by Zero trap

The Divide by Ze ro trap vector is located at addresses 0002h and 0003h of each c ode s egm ent; it should be noted that for each code segm ent a Divide by Zero service routine is required.

Warning. Although the Divide by Zero Trap oper-

ates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET).

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

IRET

INSTRUCTIO N

INTERRUPT

VR001833

CLEAR

PENDING BIT

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3.2.2 Segment Paging During Interrupt Routines

The ENCSR bit in the EMR2 regist er can be used to select between original ST9 backward compatibility mode and ST9+ interrupt management mode.

ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9

compatibility m ode. For the durat ion of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed.

This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time.

It is not possible for an interrupt service routine t o perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The cod e segment size for all interrupt service routines is thus limited to 64K bytes.

ST9+ m ode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the in-

terrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents o f ISR.

In this cas e, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, bec ause of the need t o also save CSR on the stack.

Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different.

3.3 INTERRUPT PRIORITY LEVELS

The ST9 suppo rts a fully programmable i nterrupt priority structure. Nine priority levels are available to define the channel priority relationships:

– The on-chip peripheral channel s and the eight

external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority).

– The 9th level (Top Level Priority) is reserved for

the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM).

3.4 PRIORITY LEVEL ARBITRATION

The 3 bits of CPL (Current Priority Le vel) in the Central Interrupt Control Register contain the priority of the currently running prog ram (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execut ion either by software or automatically by hardware according to the selected Arbitration Mode.

During every instruction, an arbitration phase takes place, during which, for every channel capable of generating an Interrupt, each priority level is compared to all the other req uests (interrupts or DMA).

If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR regi ster (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority.

3.4.1 Priority level 7 (Lowest)

Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower t han the CPL value. This can be of use in a f ully pol led interrupt environment.

3.4.2 Maximum depth of nesting

No more than 8 routines can be nested. If an interrupt routine at level N is being serviced, n o other Interrup ts located at lev el N can interru pt it. This guarantees a maximum number of 8 nested levels including the Top Level Interrupt request.

3.4.3 Simultaneous Interru pts

If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel

ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped

Registers

PC, FLAGR

PC, FLAGR,

CSR

Max. Code Size for interrupt service routine

64KB

Within 1 segment

No limit

Across segments

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PRIORITY LEVEL ARBITRATION (Cont’d)

with the highest position in the chain, as sh own i n

Table 11.

Table 11. Daisy Chain Priority

3.4.4 Dynamic Priority Level Modification

The main program and routines can be specifically prioritized. Since the CPL is represent ed by 3 bits in a read/write register, it is pos sible to m odify dy namically the current priority value during program execution. This means that a critical section can have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by m odifying the CPL during its execution. See Figure 16

Figure 16. Example of Dynamic priority level modification in Nested Mode

3.5 ARBITRATION MODES

The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested m ode. Concurrent mode is the standard interrupt arbitration mode. Nested mode improves the e ffective interrupt response time when service routine nesting is required, depending on the request priority levels.

The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested A rbitrat ion Mode.

3.5. 1 C oncurre nt Mode

This mode is selected w hen t he I AM bi t is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode.

Start of Interrupt Routine

The interrupt cycle performs the following steps:

– All maskabl e interrupt requests are disabled by

clearing CICR.IEN. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – If ENCSR is set, CSR is pushed onto system

stack. – The Flag register is pushed onto system stack. – The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR. – If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR is used in place of CSR until

iret instruction.

End of Interru pt Routine

The Interrupt Service Routine must be ended with the iret instruction. The iret instruction executes the following operations:

– The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system

stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – All unmas ked Interrupts are enabled by setting

the CICR.IEN bit. – If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumes at the in-

terrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine).

Note: In Concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine’s priority. This may cause undesirable interrupt response sequences.

Highest Position

Lowest Position

INTA0 / Watchdog Timer INTA1 / Standard Timer INTB0 / Extended Function Timer INTC1 / SPI INTD0 / RCCU INTD1 / WKUP MGT Induction Motor Controller

AD Converter

Priority Level

MAIN

CPL is set to 5

CPL=7

MAIN

INT 6

CPL=6

INT6 ei

CPL is set to 7

CPL6 > CPL5: INT6 pending

INTERRUPT 6 HAS PRIORITY LEVEL 6

by MAIN program

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ARBITRATION MODES (Cont’d) Examples

In the following two examples, three interrupt requests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service routine.

Example 1

In the first example, (simplest case, Figure 17) the ei instruction is not used within the interrupt service routines. This means that no new interrupt can be serviced in the m iddle of the current one. The interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes.

Figure 17. Simple Examp le of a Sequence of In te rru pt R equ e st s wi th:

- Concurrent mode selected and

- IEN unchanged by the interrupt routines

Priority Level of

MAIN

INT 5

INT 2

INT 3

INT 4

MAIN

INT 5

INT 4

INT 3

INT 2

CPL is set to 7

CPL = 7

INTERRUPT 2 HAS PRI ORITY LEV E L 2 INTERRUPT 3 HAS PRI ORITY LEV E L 3 INTERRUPT 4 HAS PRI ORITY LEV E L 4 INTERRUPT 5 HAS PRI ORITY LEV E L 5

Interrupt Request

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ARBITRATION MODES (Cont’d) Example 2

In the second example, (more complex, Figure

18), each interrupt service routine sets Interrupt

Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than t he one being serviced.

The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-

ice routines being executed in the opposite order of their priority.

It is therefore recommended to avoid inserting the ei instructio n in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode .

WARNING: If, in Concurrent Mode, in terrupts are

nested (by executing ei in an interrupt service routine), make sure that either ENCSR is set or CSR=ISR, otherwise the i ret of the innermost interrupt will make the CPU use CSR instead of ISR before the outermost interrupt service routine is terminated, thus making the outermost routine fail.

Figure 18. Complex Example of a Sequence of Interrupt Requests with:

- Concurrent mode selected

- IEN set to 1 during interrupt service routine execution

MAIN

INT 5

INT 2

INT 3

INT 4

INT 5

INT 4

INT 3

INT 2

CPL is set to 7

CPL = 7

INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5

INT 2

INT 3

CPL = 7

INT 5

CPL = 7

MAIN

Priority Level of Interrupt Request

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ARBITRATION MODES (Cont’d)

3.5.2 Nested Mode

The difference between Nested mode and Concurrent mode, lies i n the modification of the Current Priority Level (CPL) d uring interrupt process ing.

The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in the Nested Interrupt Control Register (NICR) by setting the NICR bit corresponding to the CPL value (i.e. if the CP L is 3, the bit 3 will be set).

The CPL is then loaded with the priority of the request just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being executed .

Start of Interrupt Routine

The interrupt cycle performs the following steps:

– All maskabl e interrupt requests are disabled by

clearing CICR.IEN. – CPL is saved in the special NICR stack to hold

the priority level of the suspended routine. – Priority level of the acknowledged routine is

stored in CPL, so that the next request priority

will be compared with the one of the routine cur-

rently being serviced. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – If ENCSR is set, CSR is pushed onto system

stack. – The Flag register is pushed onto system stack. – The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR. – If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR is used in place of CSR until

iret instruction.

Figure 19. Simple Examp le of a Sequence of In te rru pt R equ e st s wi th:

- Nested mode

- IEN unchanged by the interrupt routines

MAIN

INT 2

INT0

INT4

INT3

INT2

CPL is set to 7

CPL=2

CPL=7

INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5

MAIN

INT 3

CPL=3

INT 6

CPL=6

INT5

INT 0

CPL=0

INT6

INT2

INTERRUPT 6 HAS PRIORITY LEVEL 6

INTERRUPT 0 HAS PRIORITY LEVEL 0

CPL6 > CPL3: INT6 pending

CPL2 < CPL4: Serviced next

INT 2

CPL=2

INT 4

CPL=4

INT 5

CPL=5

Priority Level of Interrupt Request

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ARBITRATION MODES (Cont’d) End of Interru pt R ou tine

The iret Interrupt Return instruction executes the following steps:

– The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system

stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – All unmasked Interrupts are enabled by setting

the CICR.IEN bit. – The priority level of the interrupted routine is

popped from the special register (NICR) and

copied into CPL.

– If ENCSR is reset, CSR is used instead of ISR,

unless the program returns to another nested routine.

The suspended routine thus resumes at the in terrupted instruction.

Figure 19 contains a simple example, showing that

if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent.

Figure 20 contains a more complex example

showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routines using the ei instruction) according to their priority level.

Figure 20. Complex Example of a Sequence of Interrupt Requests with:

- Nested mode

- IEN set to 1 during the interrupt routine execution

INT 2

INT 3

CPL=3

INT 0

CPL=0

INT6

MAIN

INT 5

INT 4

INT0

INT4

INT3

INT2

CPL is set to 7

CPL=5

CPL=4

CPL=2

CPL=7

INTERRUPT 2 HAS PRIORITY LE VEL 2 INTERRUPT 3 HAS PRIORITY LE VEL 3 INTERRUPT 4 HAS PRIORITY LE VEL 4 INTERRUPT 5 HAS PRIORITY LE VEL 5

INT 2

INT 4

CPL=2

CPL=4

INT 5

CPL=5

MAIN

INT 2

CPL=2

INT 6

CPL=6

INT5

INT2

INTERRUPT 6 HAS PRIORITY LE VEL 6

INTERRUPT 0 HAS PRIORITY LE VEL 0

CPL6 > CPL3: INT6 pending

CPL2 < CPL4: Serviced just after ei

Priority Level of Interrupt Request

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3.6 EXTERNAL INTERRUPTS

The standard ST9 core c ontains 8 external interrupts sources grouped into four pairs.

Table 12. E xt ernal Inter rupt Channe l Gr ouping

Each source has a trigger cont rol bit TEA0,..TE D1 (R242,EITR.0,..,7 Page 0) to select triggering on the rising or falling edge of the external pin. If the

Trigger control bit is set to “1”, the correspondin g pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page

0) is set on the input pin rising edge, if it is cleared, the pen din g bit is s e t on the falling edge o f th e i n put pin. Each source can be individually m asked through the corresponding control bit IMA0,..,IMD1 (EIMR.7,..,0). See Figure 22.

The priority level of the external interrupt sources can be programmed among the eight priority levels with the control register EIPLR (R245). The priority level of each pair is software defined using the bits PRL2, PRL1. For each pair, the even channel (A0,B0,C0,D0) o f the grou p has the even priority level and the odd channel (A1,B1,C1,D1) has the odd (lower) priority level.

Figure 21. Priority Level Examples

Figure 21 shows an example of priority levels. Figure 22 gives an overview of the External inter-

rupt control bits and vectors. – The source of the in terrupt channel A0 can be

selected between the external pin INT0 (when IA0S = “1”, the reset value) or the On-chip Timer/ Watchdog peripheral (when IA0S = “0”).

– The source of the interrupt c hannel D0 can be

selected between the external pin INT6 (when INT_SEL = “0”) or the on-chip RCCU.

WARNING: When using channels shared by both external interrupts and peripherals, special care must be taken t o configure their control registers for both peripherals and interrupts.

Table 13. Multiplexed Interrupt Sources

External Interrupt Channel

none

INT6

INTD1 INTD0

none none

INTC1 INTC0

none none

INTB1 INTB0

none

INT0

INTA1 INTA0

Channel

Internal Interrupt

Source

External Interrupt

Source

INTA0 Timer/Watchdog INT0 INTD0 RCCU INT6

1001001

PL2D P L1D PL2CPL1C PL2B PL1BPL2A PL1A

INT.D1:

INT.C1: 00 1= 1

INT.D0:

SOURCE PRIORITY PRIORIT

SOURCE

INT.A0: 010=2 INT.A1: 011=3

INT.B1: 101=5

INT.B0: 100=4INT.C0: 000=0

EIPLR

VR000151

100=4

101=5

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EXTERNAL INTERRUPTS (Cont’d) Figure 22. Extern al Interrupts Control B its and Vecto rs

INT A0 request

VECTOR

Priority level Mask bit Pending bit

IMA0

IPA0

V7V6V5 V4 0

000

“0”

“1”

IA0S

Watchdog/ T i m er

End of count

INT 0 pin

INT A1 request

INT B0 request

INT B1 request

INT C0

request

INT C1 request

INT D0 request

TED0

INT 6 pin

INT D1 request

VECTOR

Priority level Mask bit Pending bit

IMA1

IPA1

V5 V4 0

V7V6V5 V4 0

110

V7V6V5 V4 1

000

V7V6V5 V4 1

010

V7V6V5 V4 1

100

V7V6V5V41

110

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

Mask bit

IMB0

Pendin g bi t IPB0

Pending bit

IPB1

Pendin g bi t

IPC0

Pendi ng bit

IPC1

Pendi ng bit

IPD0

Pendi ng bit

IPD1

Mask bit

IMB1

Mask bit

IMC0

Mask bit

IMC1

Mask bit

IMD0

Mask bit

IMD1

Shared channels, s ee warning

EFTIS

EFT Interrupt

SPIS

SPI Interrupt

“1”

“0”

INT_SEL

RCCU interrupt

“1”

“0”

TEA0

“0”

PL2A PL1A

PL2CPL1C

PL2B PL1B

PL2A PL1A

PL2B PL1B

PL2CPL1C

PL2DPL1D

“1”

“0”

ID1S

WUIMU interrupt

not connected

“1”

INTS

STIM Interrupt

“1”

not connecte d

“0”

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3.7 TOP LEVEL INTERRUPT

The Top Level I nterrupt channe l can be assigne d either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high (the reset condition) the source is the external pin NMI. If it is low, the source is the Timer/ Watchdog En d Of Count. When the source is the NMI external pin, the control bit EIVR.TLTE V (R246.3; P age 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. Wh en the selected event occurs, the CICR.TLIP bit (R230.6) is set. Depending on the mask situation, a Top Level Interrupt request may be generated. Two kinds of masks are available, a Maskable mask and a Non-Maskable mask. T he first mask is the CICR.TLI bit (R230.5): it can be set or cleared to enable or disable respectively the Top Level Interrupt request. If it is enabled, the global Enable Interrupt bit, CICR.IEN (R230.4) must also be enabled in order to allow a Top Level Request.

The second mask NICR.TLNM (R247.7) is a setonly mask. Once set, it enable s the To p Level Interrupt request independently of the value of CICR.IEN and it cannot be cleared by the program. Only the processor RESET cycle can clear this bit. This does not prevent the user from ignoring some sources due to a change in TLIS.

The Top Level Interrupt Service Routine cannot be interrupted by any other interrupt or DMA request, in any arbitration mode, not even by a subsequent Top Level Interrupt request.

WARNING. The interrupt machine cycle of the Top Level Interrupt does not clear the CICR.IEN bit, and the corresponding iret does not set it. Furthermore the TLI never modifies the CPL bits and the NICR register.

3.8 ON-CHIP PERIPHERAL INTERRUPTS

The general structure of the peripheral interrupt unit is described here, however each on-chip peripheral has its ow n specific interrupt unit containing one or more interrupt channels, or DM A c hannels. Please refer to the specific peripheral chapter for the description of its interrupt featu res and control registers.

The on-chip peripheral interrupt channels provide the following control bits:

– Interrupt Pending bit (IP). Set by hardware

when the Trigger Event occurs. Can be set/ cleared by software to generate/cancel pending interrupts and give the status for Interrupt polling.

– Interrupt Mask bit (IM). If IM = “0”, no interrupt

request is generated. If IM =“1” an interrupt request is generated whenever IP = “1” and CICR.IEN = “1”.

– Priority Level (PRL, 3 bits). These bits define

the current priority level, PRL=0: the highest priority, PRL=7: the lowest priority (the interrupt cannot be acknowledged)

– Interru pt Vector Registe r (IVR, up to 7 bits).

The IVR points to the vector table which itself contains the interrupt routine start address.

Figure 23. Top Le vel Interrupt Structure

WATCHDOG ENABLE

WDEN

WATCHDOG TIMER

END OF COUNT

NMI

TLTEV

MUX

TLIS

TLIP

TLNM

TLI

IEN

PENDING

MASK

TOP LEVEL

INTERRUPT

VA00294

CORE RESET

REQUEST

IMC

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3.9 NMI/WKP0 LINE MANAGEMENT

In the ST92141, the Non Maskable Interrupt (NMI) and the Wake Up 0 line (WKUP0) functionalities are both physically m apped on the same I /O Port pin P5.1 (refer to Section 1.2).

The NMI/WKUP0 is a single alternate func tion Input, associated with pin P5.1. It is input to the In-

duction Motor Controller (IMC) an d the Wake Up Management Unit (WUIMU).

The IMC Controller processes the NMI Input and generates the Non Ma skable Interrupt request to the CPU (refer to Figure 24 and IMC Figure 71).

Figure 24. NMI/WKUP0 Line Management

NMI Event Handling

To enable an NMI event on the NM I/WKUP0 line, the following bits must be programmed:

– TLNM bit in the NICR register, – TLI and IEN bits in the CICR register – NMI bit in the IMCIVR register – NMI L b it i n the PBR regi s ter – NMI E bit in the PCR1 register An event on the NMI/WKUP0 line is handled by

the ST92141 in the following way: – a NMI event is acknowledged in the CPU only

when the internal clock INTCLK is running (i.e.

when the ST92141 is not in Stop Mode). – a NMI event is immediately acknowledged in the

IMC. The ST92141 can be either in Stop or in

Run Mode (the NMI/WKUP0 line is detected asynchronously).

Wake-up Event H andling

To enable a wa ke-up event on the NMI/WKUP0 line, the following bits must be programmed:

– WUMx bits in the WUMRL register – WUTx bits in the WUTRL register An event on the NMI/WKUP0 or the WKUP[3:1]

lines is handled by the ST92141 in the following way:

– a wake up event of one external line (out of the

four available), is immediately acknowledged in the WUIMU. The ST92141 can be either in Stop or in Run mode (the NMI/WKUP0 and WKUP[3:1] lines are detected asynchronously).

UH/UL/VH

VL/WH/WL

Input Buffer

CPU

WUIMU

Output Buffers

P5.1

IMC

Stop request to RCCU

NMI/WKUP0

WKUP0

NMI

NMI to CPU

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NMI/WKP0 LINE MANAGEMENT (Cont’d)

3.9.1 NMI/Wake-Up Event Handling in Run mode

The four external lines WKUP0/NMI, WKUP1-3 can also be used when the device is in Run Mode. In addition, if the WKUP0/NMI line is used and the NMI and WKUP0 events are enabled by programming the CPU, IMC and WUIMU registers, a transition on the input pin can generat e the following events:

– IMC: the six output phases UH/UL/VH/VL/WH/

WL are released in High Impedance. The NMI bit

of the IMCIVR register is automatically set to “1”.

A non maskable interrupt request is then sent to

the CPU. – CPU: the NMI pending bit of the CICR register is

set and the corresponding NMI interrupt routine

is immediately executed. Note 1: The NMI pendin g bits of the IMCIVR reg-

ister must be cleared by software in the NMI routine, whereas the NMI pending bit of the CICR register is cleared by hardware when NMI routine is acknowledged.

Note 2: The external NMI/WKUP0 event is flagged in the NMI pending bit of the IMCIVR register. The NMI routine must clear this bit. This operation must occur after disactivation of the NMI/WKUP0 line (otherwise, the next NMI/WKUP0 event will be lost, if the CPU is sensitive to a rising edge on the NMI input).

The flexibility of the ST9 also allows the use of the NMI/WKUP0 line as a wake up function only or as a Non Maskable Interrupt only.

WARNING:

1. The NMI management implemented in the

ST92141 impose s the following constr aints on the P5.3 (NMI/WKUP0) I.O pin:

– No glitches should occur on the pin to avoid un-

intentional NMI/wake up requests. – A minim um pulse width is requested for the pin

activation (refer to ST92141 Electrical Specifica-

tion).

2. The WKUP0-3 management implemented in

the ST92141 imposes the following constraints on the P5.0 (WKUP1), P5.2 (WKUP0), P3.2 (WKUP3) and P3.6 ( WK UP2 ) :

– No glitches should occur on WKUP0-3 pins to

avoid unintentional requests.

3.9.2 NMI/Wake-Up Event Handling in STOP mode

The ST92141 enters St op Mode by software writing a special Stop bit setting sequence in the WUCTRL register of the WUIMU. After entering Stop Mode, the device can be woken up by one of the four Wake Up external lines (refer to Section

3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU).

In addition, if the WKUP0/NMI line is used and the NMI and WKUP0 events are enabled by programming the CPU, IMC and WUIMU registers, a transition on the input pin can generat e the following events:

– IMC : the six output phases UH/UL/VH/VL/WH/

WL are released in High Impedance. The NMI bit of the IMCIVR register is automatically set to “1”. A non maskable interrupt request is then sent to the CPU.

– WUIMU: the NMI/WKUP0 activation wakes up

the ST92141 from Stop mode, allowing the CPU to acknowledge the NMI request from IMC

– CPU: the NMI pending bit of the CICR register is

set and the corresponding NMI interrupt routine is executed as soon as the ST92141 is exited from Stop mode.

Note: The NMI pending bits of the IMCIVR register must be cleared by software in the N MI routine, whereas the NMI pending bit of the CICR register is cleared by hardware when the NMI routine is acknowledged.

3.9.3 Unused Wake Up Management Unit lines

The WUIMU can mana ge up to 16 External-Interrupt/ Wake up lines. Usually, only a subset of these 16 lines is used.

In the ST92141, 4 lines out of 1 6 are available as external lines (WKUP0/1/2/3) but the Pending and Mask bits of the unused lines (WKUP4 to WKUP

15) are also accessible by software (refer to Sec-

tion 3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNI T (WUI MU) ) . Therefore, it is possi-

ble to generate a software interrupt by disabling the Mask and by setting the Pendi ng bit of an unused channel.

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ST92141 - INTERRUPTS

3.10 INTERRUPT RESPONSE TIME

The interrupt arbitration protocol functions completely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles.

If the interrupt request comes from an external pin, the trigger event must occur a minimum of one INTCLK cycle before the sampling time.

When an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immediately and the interrupt request is serviced; if no t, the CPU waits until the current instruction is terminated and then services the request. Instruction execution can normally be aborted provided no write operation has been performed.

For an interrupt deriving from an external interrupt channel, the response time between a us er event and the start of the i nterrupt service routine can range from a minimum of 26 clock cycles to a maximum of 55 clock cycles (DIV in struction), 53 cl ock

cycles (DIVWS and MUL instructions) or 49 for other instructions.

For a non-maskable Top Level interrupt, the response time between a user event and the start of the interrupt service routine can range from a minimum of 22 clock cycles to a maximum of 51 clock cycles (DIV instruction), 49 clock cycles (DIVWS and MUL instructions) or 45 for other instructions.

In order to guarantee edge detection, input signals must be kept low/high for a minimum of one INTCLK cycle.

An interrupt machine cycle requires a basic 18 internal clock cycles (CPUCLK), to which must be added a further 2 clock cycles if the stack is in the Register File. 2 more clock cycles must further be added if the CSR is pushed (ENCSR =1).

The interrupt machine cycle duration forms part of the two examples of interrupt response time previously quoted; it includes the time required to pus h values on the stack, as well as interrupt vector handling.

In Wait for Interrupt mode, a further cycle is required as wake-up delay.

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ST92141 - INTERRUPTS

3.11 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER

(CICR)

R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h)

Bit 7 = GCEN:

Global Counter Enable.

This bit enables the 16-bit Multifunction Timer peripheral. 0: MFT disabled 1: MFT enabled

Bit 6 = TLIP:

Top Level Interrupt Pending

. This bit is set by hardware when Top Level Interrupt (TLI) trigger event occurs. It is cleared by hardware when a TLI is acknowledged. It can also be set by software to implement a software TLI. 0: No TLI pending 1: TLI pending

Bit 5 = TLI:

Top Level Interrupt.

This bit is set and cleared by software. 0: A Top Level Interrupt is generated when TLIP is

set, only if TLNM=1 in the NICR register (independently of the value of the IEN bit).

1: A Top Level Interrupt request is generated when

IEN=1 and the TLIP bit are set.

Bit 4 = IEN:

Interrupt Enable

. This bit is cleared by the interrupt machine cycle (exce pt fo r a T L I). It is set by the iret instruction (except for a return from T L I). It is set by the EI instructio n. It is cleared by the DI instruction. 0: Maskable interrupts disabled 1: Maskable Interrupts enabled

Note: The IEN bit can also be changed by software using any instruction that operates on register CICR, however in this case, take care to avoid spurious interrupts, since IEN cannot be cleared in the middle of an interrupt arbi tration. Only modify

the IEN bit when interrupts are disabled or when no peripheral can gene rate interrupts. For example, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequence DI; POP CICR to make sure that no interrupts are being arbitrated when CICR is modified.

Bit 3 = IAM:

Interrupt Arbitration Mode

. This bit is set and cleared by software. 0: Concurrent Mode 1: Nested Mode

Bit 2:0 = CPL[2:0]:

Current Priority Level

. These bits define the Current Priority Level. CPL=0 is the highest priority. CPL=7 is the lowest priority. These bits may be modified directly by the interrupt hardware when Nested Interrupt Mode is used.

EXTERNAL INTERRUPT TRIGGER REGISTER (EITR)

R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = TED1:

INTD1 Trigger Event

Bit 6 = TED0:

INTD0 Trigger Event

Bit 5 = TEC1:

INTC1 Trigger Event

Bit 4 = TEC0:

INTC0 Trigger Event

Bit 3 = TEB1:

INTB1 Trigger Event

Bit 2 = TEB0:

INTB0 Trigger Event

Bit 1 = TEA1:

INTA1 Trigger Event

Bit 0 = TEA0:

INTA0 Trigger Event

These bits are set and cleared by software. 0: Select falling edge as interrupt trigger event 1: Select rising edge as interrupt trigger event

GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0

TED1 TED0 TEC 1 TEC0 TEB1 TEB0 TEA1 TEA0

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ST92141 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER

(EIPR)

R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = IPD1:

INTD1 Interrupt Pending bit

Bit 6 = IPD0:

INTD0 Interrupt Pending bit

Bit 5 = IPC1:

INTC1 Interrupt Pending bit

Bit 4 = IPC0:

INTC0 Interrupt Pending bit

Bit 3 = IPB1:

INTB1 Interrupt Pending bit

Bit 2 = IPB0:

INTB0 Interrupt Pending bit

Bit 1 = IPA1:

INTA1 Interrupt Pending bit

Bit 0 = IPA0:

INTA0 Interrupt Pending bit

These bits are set by hardware on occurrence of a trigger event (as specified in the EITR register) and are cleared by hardware on interrupt acknowledge. They can also be s et by software to implement a software interrupt. 0: No interrupt pending 1: Interrupt pending

EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR)

R244 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = IMD1:

INTD1 Interrupt Mask

Bit 6 = IMD0:

INTD0 Interrupt Mask

Bit 5 = IMC1:

INTC1 Interrupt Mask

Bit 4 = IMC0:

INTC0 Interrupt Mask

Bit 3 = IMB1:

INTB1 Interrupt Mask

Bit 2 = IMB0:

INTB0 Interrupt Mask

Bit 1 = IMA1:

INTA1 Interrupt Mask

Bit 0 = IMA0:

INTA0 Interrupt Mask

These bits are set and cleared by software. 0: Interrupt masked 1: Interrupt not masked (an interrupt is generated if

the IPxx and IEN bits = 1)

EXTERNAL INTERRUPT PRIORITY LEVEL REGISTER (EIP LR)

R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)

Bit 7:6 = PL2D, PL1D:

INTD0, D1 Priority Level.

Bit 5:4 = PL2C, PL1C:

INTC0, C1 Priority Level.

Bit 3:2 = PL2B, PL1B:

INTB0, B1 Priority Level.

Bit 1:0 = PL2A, PL1A:

INTA0, A1 Priority Level.

These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by

hardware at 0 for Channels A0, B0, C0 and D0 and at 1 for Channels A1, B1, C1 and D1.

IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0

IMD1 IMD0 IMC1 IMC0 IMB1 I MB0 IMA1 IMA0

PL2D PL1D PL2 C PL1C PL2B PL1B PL2A PL1A

PL2x PL1x

Hardware

bit

Priority

0 1

0 (Highest) 1

0 1

2 3

0 1

4 5

0 1

6 7 (Lowest)

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ST92141 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER

(EIVR)

R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h)

Bit 7:4 = V[7:4]:

Most significant nibble of External

Interrupt Vector

. These bits are not initialized by reset. For a representation of how the full vec tor is generated from V[7:4] and the selected external interrupt channel, refer to Figure 22.

Bit 3 = TLTEV:

Top Level Trigger Event bit.

This bit is set and cleared by software. 0: Select falling edge as NMI trigger event 1: Select rising edge as NMI trigger event

Bit 2 = TLIS:

Top Level Input Selection

. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source

Bit 1 = IA0S:

Interrupt Channel A0 Selection.

This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source

Bit 0 = EW EN:

External Wait Enable.

This bit is set and cleared by software.

0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external

memory access cycle).

Note: For more details on Wait mode refer to the section describing the W AITN pin in the External Memory Chapter.

NESTED INTERRUPT CONTROL (NICR)

R247 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = TLNM:

Top Level Not Maskable

. This bit is set by software and cleared only by a hardware reset. 0: Top Level Interrupt Maskable. A top level re-

quest is generated if the IEN, TLI and TLIP bits =1

1: Top Level Interrupt Not Maskable. A top level

request is generated if the TLIP bit =1

Bit 6:0 = HL[6:0]:

Hold Level

x These bits are set by h ardware when, in Nested Mode, an interrupt service rou tine at level x is interrupted from a request with higher priority (other than the Top Level interrupt request). They are cleared by hardware at the iret execution when the routine at level x is recovered.

V7 V6 V5 V4 TLTEV TLIS IAOS EWEN

TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0

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ST92141 - INTERRUPTS

3.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)

3.12.1 Intro duction

The Wake-up/Interrupt Management Unit extends the number of external interrupt li nes f rom 8 t o 2 3 (depending on the number of external interrupt lines mapped on external pins of the device). It allows the source of the INTD1 external interrupt channel to be used for up to 16 additional external Wake-up/interrupt pins.

These 16 WKUP pins can b e programmed as ex ternal interrupt lines or as wake-up lines, able to exit the microcontroller from low power mode (STOP mode) (see Figure 25).

3.12.2 Main Features

■ Supports up to 16 additional external wake-up

or interrupt lines

■ Wake-Up lines can be used to wake-up the ST9

from STOP mo de.

■ Programmable selection of wake-up or interrupt

■ Programmable wake-up trigger edge polarity

■ All Wake-Up Lines maskable

Note: The number of available p ins is device dependent. Refer to the device pinout description.

Figure 25. W ake-Up Lines / Interrupt Manag em ent Unit Block D iag ra m

WUTRH

WUTRL

WUPRH

WUPRL

WUMRH

WUMRL

TRIGGERING LEVEL REGISTERS

PENDING REQUEST REGISTERS

MASK REGISTERS

WKUP[7:0]

WKUP[15:8]

Set

WUCTRL

SW SETTING

WKUP-I NT

ID1S

STOP

Reset

TO RCCU - S top Mode Control

TO CPU

INTD1 - External Interrupt Chan nel

Note: Reset Signal on stop bit

is stronger than the set signal

INT7 (n ot connected)

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

3.12.3 Functional Description

3.12 .3 . 1 Inter rupt Mode

To configure the 16 wake-up lines as interrupt sources, use the following procedure:

1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH).

2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH).

3. Set bit 7 of EIMR (R244 Page 0) and EITR (R242 Page 0) registers of the CPU: so an interrupt coming from one of the 16 lines can be correctly acknowledged.

4. Reset t he WKUP -IN T bit in the WUCTRL register to disable Wake-up Mode.

5. Set the ID1S bi t in the WUCT RL register to disable the INT7 external interrupt source and enable the 16 wake-up lines as external interrupt source lines.

To return to standard mode (I NT7 external interrupt source enabled and 16 wake-up lines disabled) it is sufficient to reset the ID1S bit.

3.12.3.2 Wake-up Mode Selection

To configure the 16 lines as wake-up sources, use the following procedure:

1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH).

2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH).

3. Set, as for Interrupt Mode selection, bit 7 of EIMR and EITR registers only if an interrupt routine is to be executed after a wake-up event. Otherwise, if the wake-up event only restarts the execution of the code from where it was stopped, the INTD1 interrupt channel m ust be masked or the external source must be selected by resetting the ID1S bit.

4. Since the RCCU can generate an interrupt request when exiting from STOP mode, take care to mask it even if the wake-up event is only to restart code execution.

5. Set the WKUP -INT bit in the WUCTRL register to select Wake-up Mode.

6. Set the ID1S bi t in the WUCT RL register to disable the INT7 external interrupt source and enable the 16 wake-up lines as external interrupt source lines. This is not mandatory if the wake-up event does not require an interrupt response.

7. Write the sequence 1,0,1 to the STOP bit of the WUCTRL register with three consecutive write operations. This is the STOP bit setting sequence.

To detect if STO P Mode was entered or not, immediately after the STOP bit setting sequence, poll the RCCU EX_STP bit (R242.7, Page 55) and the STOP bit itself.

3.12.3.3 STOP Mode Entry Conditions

Assuming the ST9 is in Run mode: during the STOP bit setting sequence the following cases may occur:

Case 1: Wrong STOP bit setting sequence

This can happen if an Interrupt/DMA request is acknowledged during the STOP bit setting sequence. In this case polling the STOP and EX_STP bi ts w ill giv e :

STOP = 0, EX_STP = 0 This means that the ST9 did not enter STOP mode

due to a bad S TO P bit set ting sequence: the user must retry the sequence.

Case 2: Correct STOP bit setting sequence

In this case the ST9 enters STOP mode. To exit STOP mo de, a wake -up interrupt must be

acknowledged. That implies:

STOP = 0, EX_STP = 1

This means that the ST9 entered and exited STOP mode due to an external wake-up line event.

Case 3: A wake-up event on the external wakeup lines occurs during the STOP bit setting sequence

There are two possible cases:

1. Interrupt requests to the CPU are disabled: in this case the ST9 will not ent er STOP mode, no interrupt service routine will be executed and the program execution continues from the instruction following the STOP bit setting sequence. The status of STOP and EX_STP bits will be again:

STOP = 0, EX_STP = 0

The application can determine why the ST9 did not enter STOP mode by polling the pending bits of the external lines (at least one must be at

1).

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

2. Interrupt requ ests to CPU are enabled : in this case the ST9 will not enter STOP mode and the interrupt service routine will be executed. The status of STOP and EX_STP bits will be agai n:

STOP = 0, EX_STP = 0

The interrupt service routine can determine why the ST9 did not enter STOP mode by polling the pending bits of the external lines (at least one must be at 1).

If the MCU really exits from STOP Mode, the RCCU EX_STP bit is still set and must be reset by software. Otherwise, if an Interrupt/DMA request was acknowledged during the STOP bit setting sequence, the RCCU EX_STP bit is reset. This means that the MCU has filtered the STO P Mode entry request.

The WKUP-INT bit can be used by an interrupt routine to detect and to distinguish events coming from Interrupt Mode or from Wake-up Mode, allowing the code to execute different procedures.

To exit STOP mode, it is sufficient that one of the 16 wake-up lines (not masked) generates an event: the clock restarts after the delay needed for the oscillator to restart.

Note: After exiting from STOP Mode, the software can successfully reset the pending bits (edge sensitive), even though the corresponding wake-up line is still active (high or low, depending on the Trigger Event register programming); the user must poll the external pin status to detect and distinguish a short event from a long one (for example keyboard input with keystrokes of varying length).

3.12.4 Programming Considerations

The following paragraphs give some guidelines for designing an application program.

3.12.4.1 Procedure for Entering/Exiting STOP mode

1. Program the polarity of the trigger event of external wake-up lines by writing registers WUTRH and WUTRL.

2. Check that at least one mask bit (registers WUMRH, WUMRL) is equal to 1 (so at least one external wake-up line is not masked).

3. Reset at least the unm asked pending bits: this allows a rising edge to be generated on the INTD1 channel when the trigger event occurs (an interrupt on channel INTD1 is recognized when a rising edge occurs).

4. Select the i nterrupt source of the INTD1 channel (see description of ID1S bi t in the WUCT RL register) and set the WKUP-INT bit.

5. To generate an interrupt on channel INTD1, bits EITR.1 (R242.7, Page 0) and EIMR.1 (R24 4.7, Page 0) must be set and bit EIPR.7 must be reset. Bits 7 and 6 of register R245, Page 0 must be written with the desired priority level for interrupt channel INTD1.

6. Reset the STOP bit in register WUCTRL and the EX_STP bit in the CLK_FLAG register (R242.7, Page 55). Refer to the RCCU chapter.

7. To enter S TOP m ode, write the s equence 1, 0, 1 to the STOP bit i n the W UCTRL register with three consecutive write operations.

8. The code to be executed just after the STOP sequence must che ck the status of the STOP and RCCU EX_STP bits to determine if the ST9 entered STOP mode or not (See “Wake-up Mode Selection” on page 56. for details). If the ST9 did not enter in STOP mode it is necessary to reloop the procedure from the beginning, otherwise the procedure continues from next point.

9. Poll the wake-up pending bits to determine which wake-up line ca used the exit f rom STOP mode.

10.Clear the wake-up pending bit that was set.

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

3.12.4.2 Simultaneous Setting of Pending Bits

It is possible that several simu ltaneous ev ents set different pending bits. In order to accept subsequent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this operation allows a rising e dge t o be generated on the INTD1 line (if there is at least one more pe nding bit set and not masked ) and so to set EIPR. 7 bit again. A further interrupt on channel INTD1 will be serviced depending on the status of bit EIMR.7. Two possible situations may arise:

1. Th e user chooses to reset all pending bits: no further interrupt requests will be generated on channel INTD1. In this case the user has to:

– Reset EIMR.7 bit (to avoid generating a spuri-

ous interrupt request during the next reset operation on the WUPRH register)

– R eset WUPRH register using a read-modify-

write instruction (AND, BRES, BAND) – Clear the EIPR.7 bit – Reset the WUPRL register using a read-mod-

ify-write instruction (AND, BRES, BAND)

2. The user choos es to keep at least one pending bit active: at least one additional interrupt request will be generated on the INTD1 channel. In this case the user has to reset the desired pending bits with a read-modify-write instruction (AND, BRES, BAND). This operation will generate a rising edge on the INTD1 channel and the EIPR.7 bit will be set again. An interrupt on th e INTD 1 cha nnel will b e se rviced depending on the status of EIMR.7 bit.

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

3.12.5 Register Description WAKE-UP CONTROL REGISTER (WUCTRL)

R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 2 = STOP:

Stop bit.

To enter STOP Mode, write the sequence 1,0,1 to this bit wi th three consecutive wr ite o pera tions. When a correct sequence is recognized, the STOP bit is set and the RCCU p uts the MCU in STOP Mode. The software sequence succeeds only if the following conditions are true:

– The WKUP-INT bit is 1, – All unmasked pending bit s are reset, – At least one mask bit is equal to 1 (at least one

external wake-up line is not masked).

Otherwise the MCU cannot enter STOP mode, the program code con tinues e xe cuting and the STOP bit remains cleared.

The bit is reset by hardware if, while the MCU is in STOP mode, a wake-up interrupt c ome s from any of the unmasked wake-up lines. The STOP bit is at 1 in the two following cases (See “Wak e-up Mod e Selection” on page 56. for details):

– After the first write instruction of the sequence (a

1 is written to the STOP bit)

– At the end of a successful sequenc e (i.e. after

the third write instruction of the sequence)

WARNING: Writing the sequence 1,0,1 to the STOP bit will enter STOP mode on ly if no other register write instructions are executed during the sequence. If Interrupt or DMA reques ts (which always perform register write operations) are acknowledged during the sequence, the ST9 will not

enter STOP mode: the user m ust re-enter the sequence to set the STOP bit.

WARNING: Whenever a S TOP request is issued to the MCU, a few clock cycles are needed to enter STOP mode (see RCCU chapter for further details). Hence the execution of the instruction f ollowing the STOP bit s etting sequence m ight start before entering STOP mode: if such instruction performs a register write operation, the ST9 will not enter in STOP mo de. In order t o avoi d t o ex ecute register write instructions after a correct STOP bit setting sequence and before entering the STOP mode, it is mandatory to execute 3 NOP instructions after the STOP bit setting sequence.

Bit 1 = ID1S:

Interrupt Channel INTD1 Source.

This bit is set and cleared by software. 0: INT7 external interrupt source selected, exclud-

ing wake-up line interrupt requests

1: The 16 external wake-up lines enabled as inter-

rupt sources, replacing the INT7 external pin function

WARNING: To avoid spurious interrupt requests on the INTD1 channel due to changing the interrupt source, do the following before modifying the ID1S bit:

1. Mask the INTD1 interrupt channel (bit 7 of register EIMR - R244, Page 0 - reset to 0).

2. Program the ID1S bit as needed.

3. Clear the IPD1 interrupt pending bit (bit 7 of register EIPR - R243, Page 0).

4. Remove the mask on INTD1 (bit EIMR.7=1).

Bit 0 = WKUP-INT:

Wakeup Interrupt.

This bit is set and cleared by software. 0: The 16 external wakeup lines can be used to

generate interrupt requests

1: The 16 external wake-up lines to work as wake-

up sources for exiting from STOP mode

-----STOPID1SWKUP-INT

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH)

R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUM[15:8]:

Wake-Up Mask bits.

If WUMx is set, an interrupt on channel INTD1 and/or a wake-up ev ent (depending on ID1S an d WKUP-INT bits) are generated if t he corresponding WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then:

– If ID1S=1 and WKUP-INT=1 then an interrupt on

channel INTD1 and a wake-up event are generated.

– If ID1S=1 and WKUP-INT=0 only an interrupt on

channel INTD1 is generated.

– If ID1S=0 and WKUP-INT=1 only a wake-up

event is generated.

– If ID1S=0 and WKUP-INT=0 neither interrupts

on channel INTD1 nor wake-up events are generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7.

If WUMx is rese t, n o wa ke -up e ven ts ca n b e generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0).

WAKE-UP MASK REGISTER LOW (WUMRL) R251 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUM[7:0]:

Wake-Up Mask bits.

If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the corresponding WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then:

– If ID1S=1 and WKUP-INT=1 then an interrupt on

channel INTD1 and a wake-up event are generated.

– If ID1S=1 and WKUP-INT=0 only an interrupt on

channel INTD1 is generated.

– If ID1S=0 and WKUP-IN T=1 only a wake-up

event is generated.

– If ID1S=0 and WKUP-IN T=0 neither interrupts

on channel INTD1 nor wake-up events are generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7.

If WUMx is reset, no wake-up events can be generated. Interrupt requests on channel INTD1 m ay be generated only from external interrupt source INT7 (resetting ID1S bit to 0).

WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8

WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0

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ST92141 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER HIGH

(WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUT[15:8]:

Wake-Up Trigger Polarity

Bits

These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set

on the falling edge of the input wake-up line.

1: The corresponding WUPx pending bit will be set

on the rising edge of the input wake-up line.

WAKE-UP TRIGGER REGIST ER L OW ( WUTRL) R253 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUT[7:0]:

Wake-Up Trigger Polarity Bits

These bits are set and cleared by software. 0: The corresponding WUPx pending bit will be set

on the falling edge of the input wake-up line.

1: The corresponding WUPx pending bit will be set

on the rising edge of the input wake-up line.

WARNING

1. As the external wake-up lines are edge triggered, no glitches must be generated on th ese lines.

2. If either a rising or a falling edge on the external wake-up lines occurs while writing the WUTRH or WUTRL registers, the pe nding bit will no t be set.

WAKE-UP PENDING REGISTER HIGH

(WUPRH) R254 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUP[15:8]:

Wake-Up Pending Bits

These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by sof tware. They c an be set by software to implem ent a software interrupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occurred

WAKE-UP PENDI NG REGI STER LO W (WUPRL) R255 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUP[7:0]:

Wake-Up Pending Bits

Note: To avoid losing a trigger event while clearing the pending bits, it is reco mmended to use read-modify-write instructions (AND, BRES, BAND) to clear them.

WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8

WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0

WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8

WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0

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ST92141 - EM CONFIGURATION REGISTERS (EM)

4 EM CONF IGURAT ION REGISTERS (EM)

In ST9 devices with external memory, the EM registers (External Memory Registers) are used to configure the external memory interface. In the ST92141, only the BSZ, ENCSR and DPREM bits must be programmed. All other bits in these registers must be left at their reset values.

EM RE GISTER 1 (EMR 1 )

R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h)

Bit 7:2 = Reserved.

Bit 1 = BSZ:

Buff e r size.

0: I/O ports P3.6, P3.5, P5.0, P5.2 use output buff-

ers with standard current capability (less noisy).

1: I/O ports P3.6, P3.5, P5.0, P5.2 use output buff-

ers with high current capability (more noisy)

Bit 0 = Reserved.

EM RE GISTER 2 (EMR 2 )

R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh)

Bit 7 = Reserved, keep in reset state.

Bit 6 = ENCSR:

Enable Code Segment Register.

This bit is set and cleared by software. It affects

the ST9 CPU behaviour whenever an interrupt request is issued. 0: The CPU works in original ST9 compatibility

mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes.

1: ISR is only used to point to the interrupt vector

table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this ca se, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs.

Bit 5 = DPRREM:

Data Page Registers remapping

0: The locations of the four MMU (Memory Man-

agement Unit) Data Page Registers (DPR0, DPR1, DPR2 and DPR3) are in page 21.

1: The four MMU Data Page Registers are

swapped with that of the Data Registers of ports 0-3.

Refer to Figure 11

Bit 4:0 = Reserved, keep in reset state.

100000BSZ0

70 0ENCSRDPREM01111

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5 RESET AND CLO CK CONTROL UNI T (RCCU)

5.1 INTRODUCTION

The Reset and Cloc k Control Unit (RCCU) comprises two distinct sections:

– the Clock Control Unit, which generates and

manages the internal clock signals.

– the Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog generated resets.

In Stop mode and Halt mode, all oscillators are frozen in order to achieve the lowest possible power consumption.

Entering and exiting Stop mode is controlled by the WUIMU.

Halt mode is entered by executing the HALT instruction. Halt mode can only be exited by a res et event.

5.2 CLOCK CONTROL UNIT

The Clock Control Unit generates the internal clocks for the CPU core (CPUCLK) and for the onchip peripherals (INTCLK). The Clock Control Unit may be driven by an external crystal circuit, connected to the OSCIN and OSCOUT pins, or by an external pulse generator, connected to OSCIN (see Figure 34 and Figure 36). If present, a not her clock source named CK_AF can be provided to the system. Depending on t he device, i t can be a periodic signal applied to the CK_AF pin or a signal generated internally by the MCU (RC oscillator).

5.2.1 Clock Control Unit Overview

As shown in Figure 26, a programmable divider can divide the CLOCK1 input clock signal by two. The resulting signal, CLOCK2, is the reference in-

put clock to the programmable Phase Locked Loop frequency multiplier, which is capable of multiplying the clock frequency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a programmable divider, b y a factor of 1 to 7. B y this means, the ST9 ca n operate with cheaper, m edium frequency (3-5 MHz) crystals, while still providing a high frequency internal clock for maximum system performance; the range of available multiplication and division factors allow a great number of operating clock frequencies to be derived from a single crystal frequency. The undivided PLL clock is also available for special purposes (hig h-speed peripheral).

For low power operation, especially in Wait for Interrupt mode, the Clock Multiplier unit may be turned off, whereupon the output clock signal may be programmed as CLOCK2 divided by 16. Furthermore, during the execution of a WFI in Low Power mode, the CK_AF clock is automatically divided by 16 for further consumption reduction. (for the selection of this signal refer to the description the CK_AF clock source in t he following sect ions of this chapter).

The internal system clock, INTCLK, is r outed to all on-chip peripherals, as well as t o the programmable Clock Prescaler Unit which generates the clock for the CPU core (CPUCLK).

The Clock Prescaler is programmable and can slow the CPU clock by a factor of up to 8, allowing the programmer to reduce CPU processing speed, and thus power consumpt ion, while maintaining a high speed clock to the peripherals . This is p articularly useful when little actual processing is be ing done by the C PU and the peripherals are do ing most of the work.

Figure 26. Clock Control Unit Simplified Block Diagram

Quartz

CK_AF

1/16

1/2

oscillator

CLOCK2

CLOCK1

CK_AF

PLL

Clock Multiplier

CPU Clock

Prescaler

CPU Core

Peripherals

CPUCLK

INTCLK

Unit/Divider

1/16

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

Figure 27. ST92141 Clock Distribution Diagram (settings given for 5MHz crystal & 25MHz lnternal clock)

5 MHz

PLL

1/16

1/2

DIV2=1

Oscillator

MX1=0 MX0=0

CSU_CKSEL=1

XT_DIV16=1

0 1

RCCU

25 MHz INTCL K

CLOCK2

3-bit Prescaler

CPU

IMC

16-bit Down

Counter

1/4

WDG

CPUCLK

EMBEDDED MEMORY

RAM

EPROM/FASTROM

STIM

1...8

A/D

8-bit Pres ca le r

1...256

P5.7

Quartz

DX2=0 DX1=0 DX0=0

1/16

CK_AF

1 0

WFI and LPOWFI=1 and WFI_CKSEL = 1

CK_AF

and WFI_CK SEL=1 or CKAF_SEL=1

and LPOWFI =1

WFI

1/4

Conversion time

N X 138 X INTCLK

3-bit Prescaler

1...8

Baud Rate

Generator

1/N

N=2,4,16,32

SCK

Master

SCK

Slave

(Max INTCLK/2)

SPI

LOGIC

1/2

EFT

1/N

16-bit Up

Counter

EXTCLKx

(Max INTCLK/4)

N=2,4,8

8-bit Prescaler

1/2

16-b i t Down

Count er

8-bit Prescaler

1...256

10-bit PWM

12-bit Prescaler

Counter

/OTP

N=1,4,6,8,10,12,14,16

1/N

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.3 CLOCK MANAGEMENT

The various programmable features and operating modes of the CCU are handled by four registers:

– MODER (Mode Register)

This is a System Register (R235, Group E). The input clock divide-by-two and the CPU clock

prescaler factors are handled by this register.

– CLKCTL (Clock Control Register)

This is a Paged Register (R240, Page 55). The low power modes and the interpretation of

the HALT instruction are handled by this register.

– CLK_FLAG (Clock Flag Register)

This is a Paged Register (R242, Page 55). This register contains various status flags, as

well as control bits for clock selection.

– PLLCONF (PLL Configuration Register)

This is a Paged Register (R246, Page 55). The PLL multiplication and division factors are

programmed in this register.

Figure 28. C l ock Control Unit Pro gram m i ng

Quartz

PLL

1/16

1/2

DIV2 CKAF_SEL

1/N

oscillator

MX(1:0)

0 1

CKAF_ST

CSU_CKSEL

6/8/10/14

XT_DIV16

DX(2:0)

CLOCK2

CLOCK1

(MODER)

(CLK_FLAG)

(CLKCTL)

(PLLCON F )

(CLK_FLAG)

CK_AF

INTCLK

Periphe rals

and

CPU Clock Pres caler

XTSTOP

(CLK_FLAG)

Wait for Interrupt and Low Power Modes: LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.

WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode. XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.

1/16

CK_AF

WFI and LPOWFI=1 and WFI_CKSEL = 1

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

5.3.1 PLL Clock Multiplier Programming

The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condition), CLOCK2, is equal to CLOCK1 divided by two; if DIV2 is reset, CLOCK2 is identical to CLOCK1. Since the input clock to the Clock Multiplier circuit requires a 50% duty cycle for correct PLL operation, the divide by two circuit should b e enabled when a crystal oscillator is used, or when the external clock generator does not provide a 50% duty cycle. In practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the PLL multiplier circuit. A CLOCK1 signal with a semiperiod (high or low) shorter than 40ns is forbidden if the divider by two is disabled.

When the PLL is active, it multiplies CLOCK2 by 6, 8, 10 or 14, depending on the status of the MX0 -1 bits in PLLCONF. The multiplied clock is then divided by a factor in the range 1 to 7, determined by the status of the DX0-2 bits; when these bits are programmed to 111, the PLL is switched off.

Following a RESET phase, programming bits DX0-2 to a value different from 111 will turn the PLL on. After allowing a stabilisation period for the PLL, setting the CSU_CKSEL bit in the CLK_FLAG Register selects the multiplier clock This peripheral contains a lock-in logic that verifies if the PLL is locked to the CLOCK2 frequency. The bit LOCK in CLK_FLAG register becomes 1 whe n this event occurs.

The maximum frequency allowed for INTCLK is 25MHz for 5V operation, and 12MHz for 3V operation. Care is required, when programming the PLL multiplier and divider factors, not to exceed the maximum permissible operating frequency for INTCLK, according to supply voltage.

The ST9 being a static machi ne, there is no lo wer limit for INTCLK. However, below 1MHz, A/D converter precision (if present) decreases.

5.3.2 CPU Clock Prescaling

The system cloc k, INTCLK, which may be the output of the PLL clock multiplier, CLOCK2, CLOCK2/ 16 or CK_AF, drives a programmable prescaler which generates the basic time base, CPUCLK, for the instruction executer of the ST9 CPU core. This allows the user to slow down program execution during non processor intensive routines, thus reducing power dissipation.

The internal peripherals are not affected by the CPUCLK prescaler and continue to operate at the full INTCLK frequency. This is particularly useful when little processing i s being done and the peripherals are doing most of the work.

The prescaler divides the input clock by the value programmed in the control bits PRS2,1,0 in the MODER register. If the prescaler value is zero, no prescaling takes place, thus CPUCLK has the same period and phase as INTCLK. If the value is different from 0, the prescaling is equal to the value plus one, ranging thus from two (PRS2,1,0 = 1) to eight (PRS2,1,0 = 7).

The clock generated is shown in F igure 29, and it will be noted that the prescaling of the clock does not preserve the 50% duty cycle, since the high level is stretched to replace the missing cycles.

This is analogous to the introduction of wait cycles for access to external memory. When External Memory Wait or Bus Request events occur, CPUCLK is stretched at the high level for the whole period required by the function.

Figure 29. CPU Clock Prescaling

5.3.3 Peripheral Clock

The system clock, INTCLK, which may be the output of the PLL clock multiplier, CLOCK2, CLOCK2/ 16 or CK_AF, is also routed to all ST9 on-chip peripherals and acts as the central timebas e for all timing functions.

INTCLK

CPUCLK

VA00260

000 001 010 011 100 101 110 111

PRS VALUE

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

5.3.4 Low Power Modes

The user can select an automatic slowdown of clock frequency during Wait for Interrupt operation, thus idling in low power mode while waiting for an interrupt. In WFI opera tion the clock to the CPU core (CPUCLK) is stopped, thus sus pendin g program execution, while the clock to the peripherals (INTCLK) may be programmed as described in the following paragraphs. An example of Low Power operation in WFI is illustrated in Figure 30.

If low power operation during WFI is disabled (LPOWFI bit = 0 in the CLKCTL Register), the CPU CLK is stopped but INTCLK is unchanged.

If low power operation during Wa it for Interrupt is enabled (LPOWFI bit = 1 in the CLKCTL Register), as soon as the CPU executes the WFI instruction, the PLL is turned off an d the system clock will b e forced to CLOCK2 divided by 16, or to the external low frequency clock, CK_A F divided by 1 6 if this has been selected by setting WFI_CKSEL, and providing CKAF_ST is set, thus indicating that the external clock is sel ected and actually pres ent o n the CK_AF pin. The division by 16 is only selected by Hardware after entering Low Power WFI mode.

If the external clock source is used, the crystal oscillator may be stopped by setting the XTSTOP bit, providing that the CK_A F clock is present and selected, indicated by CKAF_ST being set. The crys-

tal oscillator will be stopped automatically on entering WFI if the WFI_CKSEL bit has been set. It should be noted that selecting a non-existent CK_AF clock source is impossible, since such a selection requires that the auxiliary clock source be actually present an d selected. I n no event can a non-existent clock source be selected inadvertently.

It is up to the user program to switch back to a faster clock on the occurrence of an interrupt, t aking care to re spect the os c illator and PLL stabil is at io n delays, as appropriate.It should be noted that any of the low power m odes m ay al so be selected explicitly by the user program even when not in Wait for Interrupt mode, by setting the appropriate bits.

5.3.5 Interr up t Ge ne ra tion

System clock selection modifies the CLK CTL and CLK_FLAG registers.

The clock control unit generates an ex tern al interrupt request when CK_AF and CLOCK2/16 are selected or deselected as system clock sou rce , as well as when the system clock restarts after a stop request (when the STOP MODE feature is available on the specific dev ice). This interrupt can be masked by resetting the INT_SEL bit in the CLKCTL register. In the RCCU the interrupt is generated with a high to lo w transition (see interrupt and DMA chapters for further information).

Table 14. Summary of Operati ng Mod es using main Crystal Con trolled Osci llator

MODE INTCLK C PUCLK DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI XT_DIV16

PLL x BY 14

XTAL/2

x (14/D)

INTCLK/N 1 N-1 1 1 0 D-1 X 1

PLL x BY 10

XTAL/2

x (10/D)

INTCLK/N 1 N-1 1 0 0 D-1 X 1

PLL x BY 8

XTAL/2

x (8/D)

INTCLK/N 1 N-1 1 1 1 D-1 X 1

PLL x BY 6

XTAL/2

x (6/D)

INTCLK/N 1 N-1 1 0 1 D-1 X 1

SLOW 1 XTAL/2 INTCLK/N 1 N-1 X X 111 X 1 SLOW 2 XTAL/32 INTCLK/N 1 N-1 X X X X 0

WAIT FOR

INTERRUPT

If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.

LOW POWER

WAIT FOR

INTERRUPT

XTAL/32 STOP 1 X X X X 1 1

RESET XTAL/2 INTCLK 1 0 0 00 111 0 1

EXAMPLE

XTAL=4.4 MHz

2.2*10/2

= 11MHz

11MHz 1 0 1 00 001 X 1

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

Figure 30. Example of Low Power Mode programming

Begin

WFI_CKSEL ← 1

WFI status

User’s Program

LPOWFI ← 1

User’s Program

WFI

End

PROGRAM FLOW

COMMENTS SYSTEM CLOCK FREQUENCY

Interrupt

Quartz divided by 2

PLL multiply factor

Multiplier divider’s factor set

Wait for the

CK_AF clock selected when WFI

Wait For Interrupt

No code is executed until

Interrupt served

fixed to 10.

to 1, and PLL turned ON

an interrupt is requested

Low Power Mode enabled

Main code execution

continued

2.5 MHz

25 MHz

2.5 MHz

25 MHz

** T2 = Quartz oscillator start-up time

* T

= PLL lock-in time

=5 MHz, Vcc=5 V and T=25°C

CK_AF/16

WAIT

DX2-0 ← 000

Xtal is selected to

restart the PLL quickly

CSU_CKSEL 1

PLL is system clock source

CSU_CKSEL<- 1

while the CK_AF is

the system clock

CKAF_SEL <- 0

The system CK switches to Xtal

The PLL is locked and becomes the system clock

XTSTOP ← 0

To restart Xtal and

PLL

To stop PLL and Xtal when a WFI occurs

XTSTOP ← 1

PLL locking

SET UP AFTER RESET PHASE:

DIV2 = 1

XTSTOP = 0

MX(1:0) = 00

CSU_CKSEL

= 0

Interrupt

WAIT

Routine

(LOCK->1)

CK_AF

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.4 CLOCK CONTROL REGISTERS

MODE REGISTER (MODER)

R235 - Read/Write System Register Reset Value: 1110 0000 (E0h)

*Note:

This register contains bits which relate to other functions; these are described in the chapter dealing with Device Architecture. Only those bits relating to Clock functions are described here.

Bit 5 = DIV2:

OSCIN Divided by 2

. This bit controls the divide by 2 circuit which operates on the OSCIN Clock. 0: No division of the OSCIN Clock 1: OSCIN clock is internally divided by 2

Bit 4:2 = PRS[2:0]:

Clock Prescaling

. These bits define the prescaler value used to prescale CPUCLK from INTCLK. When these three bits are reset, the CPUCLK is not prescaled, and is equal to INTCLK; in all other cases, the internal clock is prescaled by the value of these three bits plus one.

CLOCK CONTROL REGISTER (CLKCTL)

R240 - Read Write Register Page: 55

Reset Value: 0000 0000 (00h)

Bit 7 = INT_SEL:

Interrupt Selection

0: Select the external interrupt pin as interrupt

source (Reset state)

1: Select the internal RCCU interrupt (see Section

5.3.5)

Bit 4:6 = Reserved. Must be kept reset for normal operation.

Bit 3 = SRESEN:

Software Reset Enable.

0: The HALT instruction turns off the quartz, the

PLL and the CCU

1: A Reset is generated when HALT is executed

Bit 2 = CKAF_SEL:

Alternate Function Cl ock Se-

lect.

0: CK_AF clock not selected 1: Se lect CK_AF c lock

Note: To check if the selection has actually occurred, check that CKAF_ST is set. If no clock is present on the CK_AF pin, the selection will not occur.

Bit 1 = WFI_CKSEL:

WFI Clock Select

. This bit selects the clock used during Low power WFI mode if LPOWFI = 1. 0: INTCLK during WFI is CLOCK2/16 1: INTCLK during WFI is CK_AF, further divided

by 16, providing it is present. In effect this bit sets CKAF_SEL in WFI mode

WARNING: When the CK_AF is selected as Low Power WFI clock but the XTAL is not turned off (R242.4 = 0), after exiting from the WFI, CK_AF will be still selected as system clock. In this case, reset the R240.2 bit to switch back to the XT.

Bit 0 = LPOWFI:

Low Power mode during Wait For

Interrupt

0: Low Power mode during WFI disabled. When

WFI is executed, the CPUCLK is stopped and INTCLK is unchanged

1: The ST9 enters Low Power mode when the WFI

instruction is executed. The clock during this state depends on WFI_CKSEL

- - DIV2 PRS2 PRS1 PRS0 - -

INT_SEL - - - SRESEN CKAF_SEL WFI_CK SEL LPOWFI

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG)

R242 -Read/Write Register Page: 55 Reset Value: 0100 1000 after a Watchdog Reset Reset Value: 0010 1000 after a Software Reset Reset Value: 0000 1000 after a Power-On Reset

WARNING: If this register is accessed with a logical instru ction, su ch as AND or OR, so me bit s may not be set as expected.

WARNING: If you select the CK_AF as system clock and turn off t he oscillator (bits R240.2 and R242.4 at 1), and then switch back to the XT clock by resetting the R240.2 bi t, you must wa it for the oscillator to restart correctly.

Bit 7 = EX_STP:

Stop Mode flag

This bit is set by hardware and cleared by software. 0: No Stop condition occurred 1: Stop condition occurred

Bit 6 = WDGRES:

Watchdog reset flag.

This bit is read only. 0: No Watchdog reset occurred 1: Watchdog reset occurred

Bit 5 = SOFTRES:

Software Reset Flag.

This bit is read only. 0: No software reset occurred 1: Software reset occurred (HALT instruction)

Bit 4 = XTSTOP:

Oscillator Stop Enable.

0: Xtal oscillator stop disabled 1: The Xtal oscillator will be stopp ed as soon as

the CK_AF clock is present and selected, whether this is done explicitly by the user program, or as a result of WFI, if WFI_CKSEL has previously been set to select the CK_AF clock during WFI.

WARNING: When the program writes ‘1’ to the XTSTOP bit, it will still be read as 0 and is only set when the CK_AF clock is running (CKAF_ST=1).

Take care, as any operation such as a subsequent AND with `1' or an OR with `0' to the XTSTOP bit will reset it and the oscillator will not b e stopped even if CKAF_ST is subsequently set.

Bit 3 = XT_DIV16:

CLOCK/16 Selection

This bit is set and cleared by software. An interrupt is generated when the bit is toggled. 0: CLOCK2/16 is selected and the PLL is off 1: The input is CLOCK2 (or the PLL output de-

pending on the value of CSU_CKSEL)

WARNING: After this bit is modified from 0 to 1, take care that the PLL lock-in time has elapsed before setting the CSU_CKSEL bit.

Bit 2 = CKAF_ST: (Read Only) If set, indicates that the alternate function clock

has been selected. If no clock signal is present on the CK_AF pin, the selection will not occur. If reset, the PLL clock, CLOCK 2 or CLO CK 2/16 is s elected (depending on bit 0).

Bit 1= LOCK :

PLL locked-in

This bit is read only. 0: The PLL is turned off or not locked and cannot

be selected as system clock source.

1: The PLL is locked

Bit 0 = CSU_CKSEL:

CSU Clock Select

This bit is set and cleared by software. It also cleared by hardware when:

– bits DX[2:0] (PLLCONF) are set to 111; – the quartz is stopped (by hardware or software); – WFI is executed while the LPOWF I bit is set; – the XT_DIV16 bit (CLK_FLAG) is forced to ‘0’. This prevents the P LL, when not yet locked, from

providing an irregular clock. Furthermore, a ‘0’ stored in this bit speeds up the PLL’s locking.

0: CLOCK2 provides the system clock 1: The PLL Multiplier provides the system clock.

NOTE: Setting the CKAF_SEL bit overrides any other clock selection. Resetting the XT_DIV16 bit overrides the CSU_CKSEL selection (see Figure

EX_ STP

WDG

RES

SOFT

RES

XTSTOP

XT_

DIV16

CKAF_STLOCKCSU_

CKSEL

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK CONTROL REGISTERS (Cont’d) PLL CONFIGURATION REGISTER (PLLCONF)

R246 - Read/Write Register Page: 55 Reset Value: xx00 x111

Bit 5:4 = MX[1:0]:

PLL Multiplication Factor

. Refer to Table 15 PLL Multiplication Factors for multiplier settings.

Bit 2:0 = DX[2:0]:

PLL output clock divider factor.

Refer to Table 16 Divider Configuration for divider settings.

Table 15. PLL Multiplication Factors

Table 16. Divider Configuration

Figure 31. RCCU General Timing

- - MX1 MX0 - DX2 DX1 DX0

MX1 MX0 CLOCK2 x

10 14 00 10 11 8 01 6

DX2 DX1 DX0 CK

0 0 0 PLL CLOCK/1 0 0 1 PLL CLOCK/2 0 1 0 PLL CLOCK/3 0 1 1 PLL CLOCK/4 1 0 0 PLL CLOCK/5 1 0 1 PLL CLOCK/6 1 1 0 PLL CLOCK/7

111

CLOCK2

(PLL OFF, Reset State)

STOP

Acknowledged

STOP

External

Multiplier

Xtal

INTCLK

Internal

reset

clock

RESET

request

(*)

PLL selected by user

20478xT

Xtal

(**)

PLL

Lock-in

time

PLL

Lock-in

time

4 xT

sys

Quartz

start-up

Exit from RESET

10239*CLOCK2

Switch to PLL clock

(*) WUIMU

PLL turned on by user

Xtal/2 PLL

PLL

Xtal/2

(**) +/- 1 T

Xtal

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

Figure 32. RCCU Timing during STOP (CK_AF System Clock)

Figure 33. Low Power WFI Mode with a Stopped Quartz Oscillator

STOP

Xtal

clock

reques t (*)

20478 x T

Xtal

(**)

4 xT

sys

Quartz

start-up

Exit from

STOP

10239*CLOCK2

Acknowledged

CK_AF

clock

(*) from WUIMU

INTCLK

RESET

CK_AF

selected

CKAF_SEL< -1

(**) +/- 1 T

Xtal

INTCLK

WFI state

Multiplier

clock

Xtal

clock

Interrupt

Xtal’s restart time

PLL Lock-in time

sys

=2 xT

Xtal

PLL

With:

DIV2=1

CK_AF

clock

sys

=16* T

CK_AF

)

XTSTOP<-0

CSU_CKSEL<-1

CKAF_SEL<-0

PLL

sys

= T

CK_AF

)

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.5 OSCILLATOR CHARACTERISTICS

The on-chip oscillator circuit uses an inverting gate circuit with tri-state output.

Notes:

Owing to the Q factor required, Ceramic Resonators may not provide a reliable oscillator source

OSCOUT must not be directly used to drive external circuits.

When the oscillator is stopped, OSCOUT goes high impedance.

The parallel resistor, R, is disc onnected and the oscillator is disabled, forcing the internal clock, CLOCK1, to a high level, and OSCOUT to a high impedance state.

To exit the HALT condition and restart the oscillator, an external RESET pulse is required.

It should be noted that, if the Watchdog function is enabled, a HALT instruction will not disable the oscillator. This to avoid stopping the Watchd og if a HALT code is executed in error. When this occurs, the CPU will be reset when the Watchdo g times out or when an external reset is applied.

Figure 34. Crystal Oscillator

Table 17. Crystal Specification (5V)

Legend:

, CL2: Maximum To tal Capacitances on pins OSCIN and OSCOUT (the value includes the external capacitance tied to the pin CL1 and CL2 plus the parasitic capacitance of the board and of the device).

Note: The tables are relative to the fundam ental quartz crystal only (not ceramic resonator).

Figure 35. Internal Oscillator Schematic

Figure 36. External Clock

OSCIN

OSCOUT

ST9

CRYSTAL CLOCK

VR02116A

1M*

*Recommended for oscillator stability

Rs max (ohm)

L1=CL2

56pF

CL1=CL2=

47pF

CL1=CL2=

22pF

Freq.=

3 MHz

270 350 850

Freq.= 4 MHz

150 200 510

Freq.= 5 MHz

110 120 340

VR02086A

HALT

OSCIN

OSCOUT

OUT

OSCIN OSCOUT

CLOCK

INPUT

EXTERNAL CLOCK

VR02116B

ST9

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.6 RESET/STOP MANAGER

The Reset/Stop Manager resets the MCU when one of the three following events occurs:

– A Hardware reset, initiated by a low level on the

Reset pin.

– A Software reset, initiated by a HALT instruction

(when enabled). – A Watchdog end of count condition . The Low Voltage Detector (LVD) (see Section 5.8)

generates a reset when: – the power supply, when rising, is under the LVD

LVDR

Threshold.

– the power supply, when falling, is under the LVD

LVDF

Threshold.

The event which caus ed the last Reset is flag ged in the CLK_FLAG register, by setting the SOFTRES or the WDGRES bits respectively; a hardware initiated reset will leave both these bits reset.

The hardware reset overrides a ll other conditions and forces the ST9 to the reset state. During Reset, the internal registers are set to their reset values, where these are defined, and the I/O pins are set to the Bidirectional Weak Pull-up mode.

Reset is asynchronous: as soon as the reset pin is driven low, a Re se t c ycle is initiated .

Figure 37. Oscillator Start-up Sequ ence and Reset Timing

VDD MAX

MIN

OSCIN

INTCLK

RESET

OSCOUT

5.1 ms (*)

VR02085A

START-UP

INTCLK

(*) with 4 MHz quartz

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

RESET/STOP MANAGER (Cont’d)

The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, 55h) written to the appropriate register. The input pin RESET is not driven low by the onchip reset generated by the Timer/Watchdog.

When the Reset pin goes high again, a delay occurs before exiting the Reset state. Subsequently a short Boot routine is executed from the device internal Boot ROM, and control then passes to the user program.

The Boot routine sets the device characteristics and loads the correc t values in the Memo ry Management Unit’s pointer registers, so that these point to the physical memory areas as mapped i n the specific device. The precise duration of this short Boot routine varies from device to device, depending on the Boot ROM contents.

At the end of the Boot routine the Program Counter will be set to the location specified in the Reset Vector located in the lowest two bytes of memory.

5.6.1 Reset Pin Timing

To improve the noise immunity of the device, the Reset pin has a Schmitt trigger input circuit with hysteresis . In add ition, a filt er will p revent an unwanted reset in case of a single glitch of less than 50 ns on the Reset pin. The device is certain to reset if a negative pulse of mo re than 20µs i s ap-

plied. When the reset pin goes high again, a delay of up to 4 µs will el apse bef ore the RCCU detects this rising front. From this event on , 20478 (about 5 ms with a 4M Hz quartz) oscillator clock cycles (CLOCK1) are counted before exiting the Reset state (+-1 CLOCK1 period depending on the delay between the positive edge the RCCU detects and the first rising edge of CLOCK1)

If the ST9 is a ROMLESS version, without on-chip program memory, the memory interface ports are set to external mem ory mode (i.e Alternate Function) and the memory accesses are made to external Program memory with wait cycles insertion.

Figure 38. Recommended Signal to be Applied on Reset Pin

RESET

0.7 V

0.3 V

20 µs

Minimum

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.7 STOP MODE

Under control of the Wake-up Interrupt Management Unit (WUIMU), the Reset/Stop M anager can also stop all oscillators without resetting the device.

In Stop Mode all context information will be preserved. During this condition the internal clock will be frozen in the high state.

Stop Mode is entered by programming the WUIMU

registers (See “WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)” on page 55.). An

active transition on an External Wake Up line, exits the chip from Stop Mode and the MCU resumes execution after a delay of between 10239 CLOCK2 periods and 10239 CLOCK2 periods plus the Oscillator Start Up Time.

On exiting from Stop mode an interrupt is generated and the EX_STP bit in CLK_FLAG wil l be set, to indicate to the user program that the machine is exiting from Stop mode.

Table 18. Internal Registers Reset Values

Number

System Register Reset Value Page 0 Register Reset Value

F (SSPLR) undefined Reserved E (SSPHR) undefined (SPICR) 00h D (USPLR) undefined (SPIDR) undefined C (USPHR) undefined (WCR) 7Fh B (MODER) E0h (WDTCR) 12h A (Page Ptr) undefined (WDTPR) undefined

9 (Reg Ptr 1) undefined (WDTLR) undefined

8 (Reg Ptr 0) undefined (WDTHR) undefined

7 (FLAGR) undefined (NICR) 00h

6 (CICR) 87h (EIVR) x2h

5 (PORT5) FFh (EIPLR) FFh

4 (PORT4) FFh (EIMR) 00h

3 (PORT3) FFh (EIPR) 00h

2 (PORT2) FFh (EITR) 00h

1 (PORT1) FFh Reserved

0 (PORT0) FFh Reserved

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

Figure 39. Oscillator Start-up seq uence on Exit from Stop Mode

VDD MAX

MIN

OSCIN

STOP

OSCOUT

disactivation

INTCLK

START-UP

5.1 ms (*) < T

INTCLK

< 5.1 ms + T

START-UP

(*) with 4MHz quartz and RCCU programmed with XT_STOP bit = 1 when read

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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.8 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V

supply voltage is below a V

LVDf

reference value. This means that it secures the power-up as well as the power-down keeping the ST9 in reset.

The V

LVDf

reference value for a voltage drop is

lower than the V

LVDr

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

is below:

–V

LVDr

when VDD is rising

–V

LVDf

when VDD is falling

The LVD function is illustrated in Figure 40. Provided the minimum V

value (guaranteed for

the oscillator frequency) is b elow V

LVDf

, the MC U

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

Figure 40. Low Voltage Detector vs Reset

LVDr

RESET

LVDf

HYSTERISIS

LVDhyst

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ST92141 - I/O PORTS

6 I/O PORTS

6.1 INTRODUCTION

ST9 devices feature flexible individua lly programmable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin allocations. These lines, which are logically grouped as 8-bit ports, can be individually programmed to provide digital input/output and analog input, or to connect input/output signals to the on-chip peripherals as alternate pin functions. All ports can be individually configured as an input, bi-directional, output or alternate function. In addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their p lace, to avoid the need for off-chip resistive pull-ups. Ports configured as open drain must never have voltage on the port pin exceeding V

(refer to the Electrical Characteristics section). Depending on the specific port, input buffers are soft ware sele ctabl e to be TTL or CMO S com pat ible, h owever on S chmitt trigger ports, no selection is possible.

6.2 SPECIFI C PORT CONF IGURATIONS

Refer to the Pin Description chapter for a list of the specific port styles and reset values.

6.3 PORT CONTROL REGISTERS

Each port is associated with a Data register (PxDR) and three Control registers (PxC0, PxC1, PxC2). These define the port configuration and allow dynamic configuration changes during program execution. Port Data and Control registers are mapped into the Register File as shown in Fig-

ure 41. Port Data and Control registers are treated

just like any other general purpose register. There are no special instructions for port manipulation: any instruction that can address a register, can address the ports. Data ca n be directly accessed in the port register, without passing through other

memory or “accumulator” locations.

Figure 41. I/O Register Map

GROUP E GROUP F

PAGE 2

GROUP F

PAGE 3

GROUP F

PAGE 43

System

Registers

FFh Reserved P7DR P9DR R255 FEh P3C2 P7C2 P9C2 R254 FDh P3C1 P7C1 P9C1 R253 FCh P3C0 P7C0 P9C0 R252 FBh Reserved P6DR P8DR R251 FAh P2C2 P6C2 P8C2 R250

F9h P2C1 P6C1 P8C1 R249

F8h P2C0 P6C0 P8C0 R248

F7h Reserved Reserved

Reserved

R247

F6h P1C2 P5C2 R246

E5h P5DR R229 F5h P1C1 P5C1 R245 E4h P4DR R228 F4h P1C0 P5C0 R244 E3h P3DR R227 F3h Reserved Reserved R243 E2h P2DR R226 F2h P0C2 P4C2 R242 E1h P1DR R225 F1h P0C1 P4C1 R241 E0h P0DR R224 F0h P0C0 P4C0 R240

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ST92141 - I/O PORT S

PORT CONTROL REGISTERS (Cont’d)

During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This cond ition is also held after Reset, except for Ports 0 and 1 in ROMless devices, and can be redefined under software control.

Bidirectional ports without weak pull-ups are set in high impedance during reset. To ensure proper levels during reset, these ports must be externally connected to either V

or VSS through external

pull-up or pull-down resistors. Other reset conditions may apply in specific ST9

devices.

6.4 INPUT/OUTPUT BIT CONFIGURATION

By programming the control bits PxC0.n and PxC1.n (see Figure 42) it is possible to configure bit Px.n as Input, Output, Bidirectional or Alternate Function Output, where X is the number of the I/O port, and n the bit within the port (n = 0 to 7).

When programmed as input, it is possible to select the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit. This option is not available on Schmitt trigger ports.

The output buffer can be programmed as pushpull or open-drain.

A weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirectional (except where the weak pull-up option has been permanently disabled in the pin hardware assignment).

Each pin of an I/O port may assume software programmable Alternate Functions (refer to the device Pin Description and to Section 6.5 ALTERNATE FUNCTION ARCHITECTURE). To output signals from the ST9 peripherals, the port must be configured as AF OUT. On ST 9 devices with A/D Converter(s), configure the ports used for ana log inputs as AF IN.

The basic structure of the bit Px.n of a general purpose port Px is shown in Figure 43.

Independently of the c hosen configuration, when the user addresses the port as the destination register of an instruction, the port is written to and the data is transferred from the internal Data Bus to the Output Master La tches. When the port is addressed as the source register of an instruction, the port is read and the data (stored in t he Input Latch) is transferred to the internal Data Bus.

When Px.n is programmed as an Input: (See Figure 44).

– The Output Buffer is forced tristate. – The da ta pres ent on the I/ O pin is sample d into

the Input Latch at the beginning of each instruction execution.

– The data stored in the Output Master Latch is

copied into the Output Slave Latch at the end of the execution of each instruction. Thus, if bit Px.n is reconfigured as an Output or Bidirectional, the data store d in the Ou tput S lave L atch will be r eflected on the I/O pin.

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ST92141 - I/O PORTS

INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 42. Control Bits

Table 19. Port Bit Configuration Table (n = 0, 1... 7; X = port number)

(1)

For A/D Converter inputs.

Legend:

X = Port n = Bit AF = Alternate Function BID = Bidirectional CMOS= CMOS Standard Input Levels HI-Z = High Impedance IN = Input OD = Open Drain OUT = Output PP = Push-Pull TTL = TTL Standard Input Levels WP = Weak Pull-up

Bit 7 Bit n Bit 0

PxC2 PxC27 PxC2n PxC20

PxC1 PxC17 PxC1n PxC10

PxC0 PxC07 PxC0n PxC00

General Purpose I/O Pins A/D Pins

PXC2n PXC1n PXC0n

0 0 0

1 0 0

0 1 0

1 1 0

0 0 1

1 0 1

0 1 1

1 1 1

1 1

1 PXn Configuration BID BID OUT OUT IN IN AF OUT AF OUT AF IN PXn Output Type WP OD OD PP OD HI-Z HI-Z PP OD HI-Z

(1)

PXn Input Type

TTL

(or Schmitt

Trigger)

TTL

(or Schmitt

Trigger)

TTL

(or Schmitt

Trigger)

TTL

(or Schmitt

Trigger)

CMOS

(or Schmitt

Trigger)

TTL

(or Schm i t t

Trigger)

TTL

(or Schm i t t

Trigger)

TTL

(or Schmitt

Trigger)

Analog

Input

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ST92141 - I/O PORT S

INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 43. Basic Structure of an I/O Port Pin

Figure 44. Input Configuration

n n

Figure 45. Output Configuration

OUTPUT SLAVE LATCH

OUTPUT MASTER LATCH INPUT LATCH

INTERNAL DATA BUS

I/O PIN

PUSH-PULL

TRISTATE

OPEN DRAIN

WEAK PULL-UP

FROM

PERIPHERAL

OUTPUT

INPUT

BIDIRECTIONAL

ALTERNATE

FUNCTION

TO PERIPHERAL

INPUTS AND

TTL / CMOS

(or Schmitt Trigger)

INTERRUPTS

ALTERNATE

FUNCTION

INPUT

OUTPUT

BIDIRECTIONAL

OUTPUT MASTER LATCH IN PUT LATCH

OUTPUT SLAVE LATCH

INTERNAL DATA BUS

I/O PIN

TRISTATE

TO PERIPHERAL

INPUTS AND

TTL / CMOS

(or Schmitt Trigger)

INTERRUPTS

OUTP UT MAS T ER LATCH I NPUT LATCH

OUTPUT SLAVE LATCH

INTERNAL DATA BUS

I/O PIN

OPEN DRAIN

TTL

(or Schmitt Trigger)

PUSH-PULL

TO PERIPHERAL

INPUTS AND

INTERRUPTS

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ST92141 - I/O PORTS

INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output:

(Figure 45) – The Output Buffer is turned on in an Open-drain

or Push-pull configuration.

– The data stored in the Output Master Latch is

copied both into the Input Latch and into the Output Slave Latch, driving the I/O pin, at the end of the execution of the instruction.

When Px.n is programmed as Bidirectional: (Figure 46)

– The Output Buffer is turned on in an Open-Drain

or Weak Pull-up configuration (except when disabled in hardware).

– The data pres ent on t he I/O pin is sampled into

the Input Latch at the beginning of the execution of the instruction.

– The data stored in the Output Master Latch is

copied into the Output Slave Latch, driving the I/ O pin, at the end of the execution of the instruction.

WARNING: Due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithmetic/logic and Boolean instructions performed on a bidirectional port pin.

These instructions use a read-modify-write sequence, and the result written in the port register depends on the logical level present on the external pin.

This may bring unwanted modifications to the port output register content.

For example: Port register content, 0Fh

external port value, 03 h (Bits 3 and 2 are externally forced to 0)

A bset instruction on bit 7 will return: Port register content, 83h

external port value, 83 h (Bits 3 and 2 have been cleared).

To avoid this situation, it is suggested that all operations on a port, using at least one bit in bidirectional mode, are performed on a copy of the port register, then transferring the result with a load instruction to the I/O port.

When Px.n is programmed as a digital Alternate Functi on Output:

(Figure 47) – The Output Buffer is turned on in an Open-Drain

or Push-Pull configuration.

– The da ta pres ent on the I/ O pin is sample d into

the Input Latch at the beginning of the execution of the instruction.

– The signal from an on-chip function is allowed to

load the Output Slave Latch driving the I/O pin. Signal timing is under control of the alternate function. If no alternate function is connected to Px.n, the I/O pin is driven to a high level when in Push-Pull configuration, and to a high impedance state when in open drain configuration.

Figure 46. Bidi re ct i on a l Conf i guration

n n

Figure 47. Alternate Function Configuration

n n n n n n

OUTPUT MASTER LATCH INPUT LATCH

OUTPUT SLAVE LATCH

INTE RNAL DATA BUS

I/O PIN

WEAK PULL-UP

TTL

(or Schmitt Trigger)

OPEN DRAIN

TO PERIPHERAL

INPUTS AND

INTERRUPTS

INPUT LATCH

FROM

INTERNAL DATA BUS

I/O PIN

OPEN DRAIN

TTL

(or Schmitt Trigger)

PUSH-PULL

PERIPHERAL

OUTPUT

TO PERIPHERAL

INPUTS AND

INTERRUPTS

OUTPUT SLAVE LATCH

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ST92141 - I/O PORT S

6.5 ALTERNATE FUNCTION ARCHITECTURE

Each I/O pin m ay be connected to three different types of internal signal:

– Da ta bus Input/Output – Alternat e Funct ion Input – Alternat e Funct ion Output

6.5.1 Pin Declared as I/O

A pin declared as I/O, is connected to the I/O buffer. This pin may be an Input, a n Output, or a bid irectional I/O, depending on the value stored in (PxC2, PxC1 and PxC0).

6.5.2 Pin Declared as an Alternate Function Input

A single pin may be directly connected to several Alternate Function inputs. In this case, the user must select the required input mode (with the PxC2, PxC1, PxC0 bits) and enable the selected Alternate Function in the Control Regist er of the peripheral. No specific port configuration is required to enable an Alternate Function input, since the input buffer is directly connected to each alternate function module on t he shared pin. As m ore than one module can use the same input, it is up to the user software to enable the required module as necessary. Parallel I/Os remain operational even when using an Alternate Function in put. Th e exception to this is when an I/O port bit is permanently assigned by hardware as a n A/D b it. In this case , after software programming of the bit in AFOD-TTL, the Alternate function output is forced to logic level 1. The anal og voltage level on the corresponding pin is directly input to the A/D (See Fig-

ure 48).

Figure 48. A/D Input Configuration

6.5.3 Pin Declared as an Alternate Function Output

The user must select the AF OUT configuration using the PxC2, PxC1, PxC0 bits. Several Alternate Function outputs may drive a common pin. In such case, the Alternate Func tion output signals are logically ANDed before driving the common pin. The user must t herefore enable the required Alternate Function Output by software.

WARNING: When a pin is connected both to an alternate function output and to an alternate function input, it should be noted that the output signal wi ll always be present on the alternate function input.

6.6 I/O STATUS AFTER WFI, HALT AND RESET

The status o f th e I/ O port s duri ng the Wait F or Interrupt, Halt and Reset operational modes is shown in the following table. The External Memory Interface ports are shown separately. If only the internal memory is being used and the ports are acting as I/O, the status is the same as shown for the other I/O ports.

INPUT LATCH

INTERNAL DATA BUS

I/O PIN

TRISTATE

INPUT

BUFFER

OUTPUT SLAVE LATCH

OUTPUT MASTER LATCH

TOWARDS A/D CONVERTER

GND

Mode

Ext. Mem - I/O Ports

I/O Ports

P1, P2,

P6, P9

WFI

High Imped-

ance or next

address (de-

pending on

the last

memory op-

eration per-

formed on

Port)

Address

Not Affected (clock outputs running)

HALT

High Imped-

ance

Address

Not Affected (clock outputs stopped)

RESET

Alternate function pushpull (ROMless device)

Bidirectional Weak Pull-up (High impedance when disabled in hardware).

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ST92141 - TIMER/WATCHDOG (WDT)

7 ON-CHIP PERIPHERALS

7.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip-

tion of the WDT peripheral. However depending on the ST9 device, som e or all of WDT interface signals described may not be connect ed to external pins. For the list of WDT pins present on the ST9 device, refer to the device pinout descrip tion in the first section of the data sheet.

7.1.1 Introd uction

The Timer/Watchdog (WDT) peripheral consists of a programmable 16-bit timer and an 8-bit prescaler. It can be used, for example, to:

– G enerate periodic interrupts – Meas ure inpu t signal pulse widths – Request an interrupt after a set number of events – G enerate an output signal waveform – Act as a Watchdog timer to monitor system in-

tegrity

The main WDT registers are: – Control register for the input, output and interrupt

logic blocks (WDTCR) – 16-bit counter register pair (WDTHR, WDTLR) – Prescaler register (WDTPR) The hardware interface consists of up to five sig-

nals: – WDIN External clock input – WDOUT Square wave or PWM signal output – INT0 External interrupt input – NMI Non-Maskable Interrupt input – HW0SW1 Hardware/Software Wa tchdog ena-

ble.

Figure 49. Timer/Watchdog Block Diagram

INT0

INPUT

CLOCK CONT ROL LOGIC

INEN

INMD1 INMD2

WDTPR

8-BIT PRESCALER

WDTRH, WDTRL

16-BIT

INTCLK/4

WDT

OUTMD

WROUT

OUTPUT CONTROL LOGIC

INTERR UPT

CONTROL LOGIC

END OF COUNT

RESET TOP LEVEL INTERRUPT REQUEST

OUTEN

MUX

WDOUT

IAOS

TLIS

INTA0 REQUEST

NMI

WDGEN

HW0SW1

WDIN

MUX

DOWNCOUNTER

CLOCK

Pin not present on some ST9 devices.

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.2 Functional Description

7.1.2.1 External Signals

The HW0SW1 pin can be used to permanently enable Watchdog mode. Refer to section 7.1.3.1 on page 87.

The WDIN Input pin can be used in one of four modes:

– Event Counter Mode – Gated External Input Mode – Tr iggerab le Input Mode – Re triggerable Input Mode The WDOUT output pin can be used to generate a

square wave or a Pulse Width Modulated signal. An interrupt, generated whe n the WDT is running

as the 16-bit Timer/Counter, can be used as a Top Level Interrupt or as an interrupt source connected to channel A0 of the external interrupt structure (replacing the INT0 interrupt input).

The counter can be driven either by an external clock, or internally by INTCLK divided by 4.

7.1.2.2 Initialisation

The prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be loaded with i nitial values before starting the Timer/Counter. If this is not done, counting will start with reset values.

7.1.2.3 Start/Stop

The ST_SP bit enables downcoun ting. When this bit is set, the Timer will start at the beginning of the following instruction. Resetting this bit stops the counter.

If the counter is stopped and restarted, counting will resum e fr om the la st v alue un les s a n ew co nstant has been entered in the Timer registers (WDTRL, WDTRH).

A new constant can be written in the WDTRH, WDTRL, WDTPR registers while the counter is running. The new value of the WDT RH, WDTRL registers will be loaded at the next End of Count (EOC) condition while the new value of the WDTPR register will be effective immediately.

End of Count is when the counter is 0. When Watchdog mode is enabled the state of the

ST_SP bit is irrelevant.

7.1.2.4 Single/Continuous Mo de

The S_C bit allows selection of single or continuous mode.This Mode bit can be written with the Timer stopped or running. It is possible to tog gle the S_C bit and start the counter with the same instruction.

Single Mode

On reaching the End Of Count condition, the Timer stops, reloads the constant, and resets the Start/ Stop bit. Software can check the current status by reading this bit. To restart the Timer, set the Start/ Stop bit.

Note: If the Timer constant has been modified during the stop period, it is reloaded at start time.

Continuous Mode

On reaching the End Of Count condition, the counter automatically reloads the constant and restarts. It is stopped only if the Start/Stop bit is reset.

7.1.2.5 Input Section

If the Timer/Counter input is enabled (INEN bit) it can count pulses input on the WDIN pin. Otherwise it counts the internal clock/4.

For instance, when INTCLK = 24MHz, the End Of Count rate i s :

2.79 seconds for Maximum Count (Timer Const. = FFFFh, Prescaler Const. = FFh)

166 ns for Minimum Count (Timer Const. = 0000h, Prescaler Const. = 00h)

The Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – Retriggerable Input Mode The mode is configurable in the WDTCR.

7.1.2.6 Event Counter Mode

In this mode the Timer is driven by the external clock applied to the input pin, thus operating as an event counter. The ev ent is defined as a high to low transition of the input signal. Spacing between trailing edges should be at least 8 INTCLK periods (or 333ns with INTCLK = 24MHz).

Counting starts at the next input event after the ST_SP bit is set and stops when the ST_SP bit is reset.

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.2.7 Gated Input Mode

This mode can be used for pulse width measurement. The Timer is clocked by INTCLK /4, and is started and stopped by means of the input pin and the ST_SP bit. When the input pin is high, the Timer counts. When it is low, counting stops. The maximum input pin frequency is equivalent to INTCLK/8.

7.1.2.8 Triggerable Input Mode

The Timer (clocked internally by INTCLK/4) is started by the following sequence:

– setti ng the Start-Stop bit, followed by – a High to Low transition on the input pin. To stop the Timer, reset the ST_SP bit.

7.1.2.9 Retriggerable Input Mode

In this mode, the Timer (clocked internally by INTCLK/4) is started by setting the ST_SP bit. A High to Low transition on the input pin causes counting to restart from the initial value. When the Timer is stopped (ST_SP bit reset), a High to Low transition of the input pin has no effect.

7.1.2.10 Timer/Counter Output Mod es

Output modes are selected by means of the OUTEN (Output Enable) and OUTMD (Output Mode) bits of the WDTCR register.

No Output Mo de

(OUTEN = “0”) The output is disabled an d the corresponding pi n

is set high, in order to allow other alternate functions to use the I/O pin.

Square Wave Output Mode

(OUTEN = “1”, OUTMD = “0”) The Timer outputs a signal with a frequency equal

to half the End of Count repetition rate on the WDOUT pin. With an INTCLK frequency of 20MHz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 seconds.

Pulse Width Modulated Output Mode

(OUTEN = “1”, OUTMD = “1”) The state of the WROUT bit is transferred to the

output pin (WDOUT) at the End of Count, and is held until the next End of Count condition. The user can thus generate PWM signals by modifying the status of the WROUT pin between End of Count events, based on softw are counters dec remented by the Timer Watchdog interrupt.

7.1.3 Watchdog Timer Operati on

This mode is used t o detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. The Watchdog, when enabled, resets the MCU, unless the program executes the correct write sequence before expiry of the programmed time period. The ap plication program must be designed so as to correctly write to the WDTLR Watchdog register at regular intervals during all phases of normal operation.

7.1.3.1 Hardware Watchdog/Software Watchdog

The HW0SW1 pin (when available ) selects Hardware Watchdog or Software Watchdog.

If HW0SW1 is held low: – The Watchdog is enabled by hardware immedi-

ately after an external reset. (Note: Software re-

set or Watchdog reset have no effect on the

Watchdog enable status). – The initial counter value (FFFFh) cannot be mod-

ified, however software can change the prescaler

value on the fly. – The WDGEN bit has no effect. (Note: it is not

forced low). If HW0SW1 is held high, or is not present: – The Watchdog can be enabled by resetting the

WDGEN bit.

7.1.3.2 Starting the Watchdog

In Watchdog mode the Timer is clocked by INTCLK/4.

If the Watchdog is software enabled, the time base must be written in the timer registers before entering Watchdog mode by resetting the WDGEN bit. Once reset, this bit cannot be changed by software.

If the Watchdog is hardware enabled, the time base is fixed by the reset value of the registers.

Resetting WDGEN causes the counter to start, regardless of the value of the Start-Stop bit.

In Watchdog mode, only the Prescaler Cons tant may be modified.

If the End of Count condit ion is rea ched a S ys tem Reset is generated.

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.3.3 Preventing Watchdog System Reset

In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h ha s been w ritten, the Timer reloads the constant and counting restarts from the preset value.

To reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the WDTLR register between the writing operations. The maximum allowed time between two reloads of the counter depends on the Watchdog t imeout period.

7.1.3.4 Non-Stop Operation

In Watchdog Mode, a Halt instruction is regarded as illegal. Execution of the Halt instruction stops further execution by the CPU and interrupt acknowledgment, but does not stop INTCLK, CPUCLK or the Watchdog Timer, which will cause a System Reset when the En d of Count c ondi tion is reached. Furthermore, ST_SP, S_C and the Input Mode selection bits are ignored. Hence, regardless of their status, the counter always runs in Continuous Mode, driven by the internal clock.

The Output mode should not be enabled, s ince in this context it is meaningless.

Figure 50. Watchdog Timer Mode

TIMER S TAR T C O UN TIN G

WRITE WDTRH,WDTRL

WD EN=0

WRITE AAh,55h

INTO WD TR L

RESET

SOFTWARE FAIL

(E.G . INFIN ITE LOOP) OR PERIPHERAL FAIL

VA00220

PRODUCE

COUNT RELOAD

VALUE

COUNT

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.4 WDT Interrupts

The Timer/Watchdog issues a n interrupt request at every End of Count, when this feature is e nabled.

A pair of control bits, IA0S (EIVR.1, Interrupt A0 selection bit) and TLIS (EIVR.2, Top L evel Input Selection bit) allow the selection of 2 interrupt sources (Timer/Watchdog End of Coun t, or External Pin) handled in two different ways, as a Top Level Non Maskable Interrupt (Software Reset), or as a source for channel A0 of the external interrupt logic.

A block diagram of the interrupt logic is given in

Figure 51.

Note: Software traps can be generated by setting the appropriate interrupt pending bit.

Table 20 Interrupt Configuration bel ow, shows all

the possible configurations of interrupt/reset sources which relate to the Timer/Watchdog.

A reset caused by the watchdog will set bit 6, WDGRES of R242 - Page 55 (Clo ck Flag Register). See section CLOCK CONTROL REGIS-

TERS.

Figure 51. Interrupt Sou rce s

Table 20. Interrupt Configuration

Legend:

WDG = Watchdog function SW TRAP = Software Trap

Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0 interrupts), only the INTA0 interrupt is taken into account.

TIMER WATCHDOG

RESET

WDGEN (W CR . 6 )

INTA0 REQUEST

IA0S (EIVR.1)

MUX

1INT0

MUX

TOP LEVEL

INTERR UPT RE Q UEST

VA00 293

TLIS (EIVR.2)

NMI

Control Bits Enabled Sources

Operating Mode

WDGEN IA0S TLIS Reset INTA0 Top Level

0 0 0 0

0 0 1 1

0 1 0 1

WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset WDG/Ext Reset

SW TRAP SW TRAP

Ext Pin Ext Pin

SW TRAP

Ext Pin

SW TRAP

Ext Pin

Watchdog Watchdog Watchdog Watchdog

1 1 1 1

0 0 1 1

0 1 0 1

Ext Reset Ext Reset Ext Reset Ext Reset

Timer

Timer Ext Pin Ext Pin

Timer

Ext Pin

Timer

Ext Pin

Timer Timer Timer Timer

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.5 Register Description

The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File.

WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register

Three additional control bits are mapped in the following registers on Page 0:

Watchdog Mode Enable, (WCR.6) Top Level Interrupt Selection, (EIVR.2) Interrupt A0 Channel Selection, (EIVR.1) Note: The registers containing these bits also con-

tain other functions. Only the bits relevant to the operation of the Timer/Watchdog are shown here.

Counter Register This 16-bit register (WDTLR, WDTHR) is u sed to

load the 16-bit counter value. The registers can be read or written “on the fly”.

TIMER/WATCHDOG HIGH REGISTER (WDTHR)

R248 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)

Bits

7:0 = R[15:8]

Counter Most Significant Bits

TIMER/WATCHDOG LOW REGISTER (WDTLR)

R249 - Read/Write Register Page: 0 Reset value: 1111 1111b (FFh)

Bits 7:0 = R[7:0]

Counter Least Significant Bits.

TIMER/WATCHDOG PRESCALER REGISTER (WDTPR)

R250 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)

Bits 7:0 = PR[7:0]

Prescaler value.

A programmable value from 1 (00h) to 256 (FFh).

Warning: In order to prevent incorrect operation of

the Timer/Watchdog, the prescaler (WDT PR) and counter (WDTRL, WDTRH) regi sters must be initialised before starting the Timer/Wa tchdog . If this is not done, counting will start with the reset (un-initialised) values.

WATCHDOG TIMER CONTROL REGISTER (WDTCR)

R251- Read/Write Register Page: 0 Reset value: 0001 0010 (12h)

Bit

7 = ST_SP:

Start/Stop Bit

. This bit is set and cleared by software. 0: Stop counting 1: Start counting (see Warning above)

Bit 6 = S_C:

Single/Continuous

. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode

Bits 5:4 = INMD[1:2]:

Input mode selection bits

These bits select the input mode:

R15 R14 R13 R 12 R11 R10 R9 R8

R7 R 6 R5 R4 R3 R2 R1 R0

PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN

INMD1 INMD2 INPUT MODE

0 0 Event Counter 0 1 Gated Input (Reset value) 1 0 Triggerable Input 1 1 Retriggerable Input

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ST92141 - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d) Bit 3 = INEN:

Input Enable

. This bit is set and cleared by software. 0: Disable input section 1: Enable input section

Bit 2 = OUTMD:

Output Mode.

This bit is set and cleared by software. 0: The output is toggled at every End of Count 1: The value of the WROUT bit is transferred to the

output pin on every End Of Count if OUTEN=1.

Bit 1 = WROUT:

Write Out

. The status of this bit is transferred to the Output pin when OUTMD is set; it is user definable to a llow PWM output (on Reset WROUT is set).

Bit 0 = OUTEN:

Output Enable bit

. This bit is set and cleared by software. 0: Disable output 1: Enable output

WAIT CONTROL REGISTER (WCR)

R252 - Read/Write Register Page: 0 Reset value: 0111 1111 (7Fh)

Bit 6 = WDGEN:

Watchdog Enable

(active low) . Resetting this bit via software enters the Watchdog mode. Once reset, it ca nnot be set anymore by the user program. At System Reset, the Watchdog mode is disabled.

Note: This bit is ignored if t he Hardware Watchdog option is enabled by pin HW0SW1 (if available).

EXTERNAL INTERRUPT VECTOR REGISTER (EIVR)

R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h)

Bit 2 = TLIS:

Top Level Input Selection

. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source

Bit 1 = IA0S:

Interrupt Channel A0 Selection.

This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source

Warning: To avoid spurious interrupt requests,

the IA0S bit should be accessed only when the interrupt logic is disabled (i.e. after the DI instruction). It is a lso nec ess ary to clear any poss ib le interrupt pending requests on channel A0 before enabling this interrupt channel. A delay instruction (e.g. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the IA0S write instruction.

Other bits are described in the Interrupt section.

70 xWDGENxxxxxx

x x x x x TLIS IA0S x

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ST92141 - STANDARD TIMER (STIM)

7.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip-

tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals described may not be connected to external pins. For the list of STIM pins present on the part icular ST 9 device, refer to the pinout description in the first section of the data sheet.

7.2.1 Introd uction

The Standard Timer includes a programmable 16bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes capability. The Standard Timer uses an input pin (STIN) and an output (STOUT) pin. These pins, when available, may be independent pins or connected as Alternate Functions of an I/O port bit.

STIN can be used in one of four programmable input modes:

– even t counter, – ga ted external inpu t mode,

– triggerable input mode, – retriggerable input mode. STOUT can be used to gen erate a Square Wave

or Pulse Width Modulated signal. The Standard Timer is composed of a 16-bit down

counter with an 8-bit prescaler. The input clock to the prescaler can be driven either by an internal clock equal to INTCLK divided by 4, or by CLOCK2 derived directly from the external oscillator, divided by device dependent presc aler value, thus providing a stable time reference independent from the PLL programming or by an external clock connected to the STIN pin.

The Standard Timer End Of Count condition is able to generate an interrupt which is connected to one of the external interrupt channels.

The End of Count condition is defined as the Counter Underflow, whenever 00h is reached.

Figure 52. Stand ard Ti m er B l ock Di agram

STOUT

EXTERNAL

INPUT

CLOCK CO NTROL LO GIC

INEN

INMD1 INMD2

STP

8-BIT PRESCALER

STH,STL

16-BIT

STANDARD TIMER

CLOCK

OUTMD1

OUTMD2

OUTPUT CO NT R OL LO GIC

INTERR UPT

CONTROL LOGIC

END OF COUNT

INTS

INTERRUPT REQUEST

CLOCK2/x

STIN

INTERRUPT

DOWNCOUNTER

(See Not e 2)

Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block

may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the

INTCLK/4

MUX

Note 1: Pin not present on all ST 9 devices.

INEN bit must be held at 0.

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ST92141 - STANDARD TIMER (STIM)

STANDARD TIMER (Cont’d)

7.2.2 Functional Description

7.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is u sed

in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the b eginni ng of the next instruction. Resetting this bit will stop the counter.

If the counter is stopped and restarted, counting will resu me fr om t he va lue held at the stop cond ition, unless a new constant has been entered in the Standard Timer registers during the stop period. In this case, the new constant will be loaded as soon as counting is restarted.

A new constant can be written in STH, STL, STP registers while the counter is running. The new value of the STH and STL registers will be loade d at the next End of Count condi tion, while the ne w value of the STP register will be l oaded immediately.

WARNING: In order to prevent incorrect counting of the Standard Timer, the prescaler (STP) and counter (STL, STH) registers must be initialised before the starting of the timer. If this is not done, counting will start with the reset values (STH=FFh, STL=FFh, STP=F Fh).

Single/Continuous Mode.

The S-C bit (STC.6) selects between the Single or Continuous mode.

SINGLE MODE: at the End of Count, the Standard Timer stops, reloads the constant and resets the Start/Stop bit (the user programmer can inspect the timer current status by reading this bit). Setting the Start/Stop bit will restart the counter.

CONTINUOUS MODE: At the End of the Count, the counter automatically reloads the constant and restarts. It is only stopped by resetting the Start/Stop bit.

The S-C bit can be written either with the timer stopped or running. It is possible to toggle the S-C bit and start the Standard Timer with the same instruction.

7.2.2.2 Standard Timer Input Modes (ST9 devices with Standard Timer Inpu t STIN)

Bits INMD2, INM D1 and INEN are used to select the input modes. The Input Enable (INEN) bit ena-

bles the input mode selected by the INMD2 and INMD1 bits. If the input is disabled (INEN="0"), the values of INMD2 and INMD1 are not taken into account. In this case, this unit ac ts as a 16-bit timer (plus prescaler) directly driven by INTCLK/4 and transitions on the input pin have no effect.

Event Counter Mode (INMD1 = "0", INMD2 = "0") The Standard Timer is driven by the signal applied

to the input pin (STIN) which ac ts as an external clock. The unit works therefore as an event counter. The event is a high to low transition on STIN. Spacing between trailing edges should be at least the period of INTCLK multiplied by 8 (i.e. the maximum Standard Timer input frequency is 3 MHz with INTCLK = 24MHz).

Gated Inpu t M od e (INMD1 = "0", INMD2 = “1”) The Timer uses the internal clock (INTCLK divided

by 4) and starts and stops t he Timer ac cording to the state of STIN pin. When the status of the STIN is High the Standard Timer c ount operation proceeds, and when Low, counting is stopped.

Triggerable Input Mode (INMD1 = “1”, INMD2 = “0”) The Standard Timer is started by: a) setting the Start-Stop bit, AND b) a High to Low (low trigger) transition on STIN. In order to stop the Standard Timer in this mode, it

is only necessary to reset the Start-Stop bit. Retriggerable Input Mode (INMD1 = “1”, INMD2

= “1”) In this mode, when the Standard Timer is running

(with internal clock), a High to Low transition on STIN causes the counting to start from the last constant loaded into the S T L/ST H and STP registers. When the Standard Timer is stopped (ST-SP bit equal to zero), a High to Low transition on STIN has no effect.

7.2.2.3 Time Base Generator (ST9 devices without Stan da r d Ti m e r Input STIN)

For devices where STIN is replaced by a connection to CLOCK2, the condition (INMD1 = “0”, INMD2 = “0”) will allow the Standard Timer to generate a stable time base independent from the PLL programming.

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ST92141 - STANDARD TIMER (STIM)

STANDARD TIMER (Cont’d)

7.2.2.4 Standard Timer Output Mo des

OUTPUT modes are selected using 2 b its of the STC register: OUTMD1 and OUTMD2.

No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled an d the corresponding pi n

is set high, in order to allow other alternate functions to use the I/O pin.

Square Wave Output Mode (OUTMD1 = “0”, OUTMD2 = “1”)

The Standard Timer toggles the state of the STOUT pin on every End Of Count condition. With INTCLK = 24MHz, this allows generation of a square wave with a period ranging from 333ns to

5.59 seconds. PWM Output Mode (OUTMD1 = “1”) The value of the OUTMD2 bit is transferred to the

STOUT output pin at the End Of Count. T his allows the user to generate PWM signal s, by mod ifying the status of OUTMD2 between End of Count events, based on software counters dec remented on the Standard Timer interrupt.

7.2.3 Interrupt Selection

The Standard Timer may generate an interrupt request at every End of Count.

Bit 2 of the STC register (INTS) selects the interrupt source between the Standard T imer interrupt and the external interrupt pin. Thus the Standard Timer Interrupt uses the interrupt channel and takes the priority and vector of the external interrupt channel.

If INTS is set to “1”, the Standard Timer interrupt is disabled; otherwise, an interrupt request is generated at every End of Count.

Note: When enabling or disabling the Standard Timer Interrupt (writing INTS in the STC register) an edge may be generated on t he interrup t channel, causing an unwanted interrupt.

To avoid this spurious interrupt request , the INTS bit should be accessed only when the interrupt log-

ic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. A delay instruction (i.e. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the INTS write instruction.

7.2.4 Reg ister Mapp ing

Depending on the ST9 device there may be up to 4 Standard Timers (refer to the block diagram in the first section of the data sheet).

Each Standard Timer has 4 registers mapped into Page 11 in Group F of the Register File

In the register description on the following page, register addresses refer to STIM0 only.

Note: The four standard timers are not implemented on all S T9 devi ces. Refer to the block diagram of the device for the number of timers.

STD Timer Register Register Address

STIM0 STH0 R240 (F0h)

STL0 R241 (F1h) STP0 R242 (F2h) STC0 R243 (F3h)

STIM1 STH1 R244 (F4h)

STL1 R245 (F5h) STP1 R246 (F6h) STC1 R247 (F7h)

STIM2 STH2 R248 (F8h)

STL2 R249 (F9h) STP2 R250 (FAh) STC2 R251 (FBh)

STIM3 STH3 R252 (FCh)

STL3 R253 (FDh) STP3 R254 (FEh) STC3 R255 (FFh)

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ST92141 - STANDARD TIMER (STIM)

STANDARD TIMER (Cont’d)

7.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH)

R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)

Bits 7:0 = ST.[15:8]:

Counter High-Byte.

COUNTER LOW BYTE REGISTER (STL)

R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)

Bits 7:0 = ST.[7:0]:

Counter Low Byte.

Writing to the STH and STL registers allows the user to enter the Standard Timer constant, while reading it provides the counter’s current value. Thus it is possible to read the counter on-the-fly.

STANDARD TIMER PRESCALER REGISTER (STP)

R242 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh)

Bits 7:0 = STP.[7:0]:

Prescaler.

The Prescaler value for the Standard Timer is programmed into this register. When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256

STANDARD TIMER CONTROL REGISTER (STC)

R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h)

Bit 7 = ST-SP:

Start-Stop Bit.

This bit is set and cleared by software. 0: Stop counting 1: Start counting

Bit 6 = S-C:

Single-Continuous Mode Select.

This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode

Bits 5:4 = INMD[1:2]:

Input Mode Selection.

These bits select the Input funct ions as shown in Section 7.2.2.2, when enabled by INEN.

Bit 3 = INEN:

Input Enable.

This bit is set and cleared by software. If neither the STIN pin nor the CLOCK2 line are present, INEN must be 0. 0: Input section disabled 1: Input section enabled

Bit 2 = INTS:

Interrupt Selection.

0: Standard Timer interrupt enabled 1: Standard Timer interrupt is disabled and the ex-

ternal interrupt pin is enabled.

Bits 1:0 = OUTMD[1:2]: Output Mode Selection. These bits select the output functions as described in Section 7.2.2.4.

ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8

ST.7 ST.6 ST.5 ST.4 ST.3 ST.2 ST. 1 ST.0

STP.7 STP.6 STP.5 STP.4 STP .3 STP.2 STP.1 STP.0

ST-SP S-C INMD1 INMD2 INEN INTS OUTMD1 OUTMD2

INMD1 INMD2 Mode 00Event Counter mode 01Gated input mode 10Triggerable mode 11Retriggerable mode

OUTMD1 OUTMD2 Mode 00No output mode 01Square wave output mode 1xPWM output mode

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ST92141 - EXTENDED FUNCTION TIMER (EFT)

7.3 EXTENDED FUNCTION TIMER (EFT)

7.3.1 Introd uct i on

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (

input capture

) or generation of up to two out-

put waveforms (

output compare

and

PWM

Pulse lengths and waveform perio ds c an be m odulated from a few microseconds to several milliseconds using the timer presc aler an d the

INTCLK

prescaler.

7.3.2 Main Features

■ Programmable prescale r: INTCLK divided by 2,

4 or 8.

■ Overflow status flag and maskable interrupts

■ External clock inpu t (must be at least 4 tim es

slower than the INT CLK

clock speed) with the

choice of active edge

■ Output compare functions with

– 2 dedicat ed 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicat ed ma skable interrupt

■ Input capture functions with

– 2 dedicat ed 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicat ed ma skable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternate functions on I/O ports*

■ Up to 3 separate Timer interrupts or a global

interrupt (depending on device) mapped on external interrupt channels:

– ICI: Timer Input capture interrupt. – OCI: Timer Output compare interrupt. – TOI: Timer Overflow interrupt. – EFTI: Timer Global interrupt (replaces ICI,

OCI and TOI).

The Block Diagram is shown in Figure 53.

Table 21. EFT Pin Naming conventions

*Note 1: Some external pins are not available on

all devices. Refer to the device pin out description. *Note 2: Refer to the dev ice interrupt description,

to see if a s ingle timer interrupt is used, or three separate interrupts.

7.3.3 Functional Description

7.3.3.1 Counter

The principal block of the P rogrammable T imer is a 16-bit free running counter and its associated 16-bit registers:

Counter Registers

– Counter High Register (CHR) is the most sig-

nificant byte (MSB).

– C ounter Low Register (CLR) is the least sig-

nificant byte (LSB).

Alternate Counter Registers

– Alternate Count er Hi gh Re gister ( ACHR) is t he

most significant byte (MSB).

– A lternate Counter Low Register (ACLR) is the

least significant byt e (LSB).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (overflow flag), (see note page 98).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value.

The timer clock depends on the cloc k control bits of the CR2 register, as illustrated in Table 22 Clock

Control Bits. The value in the counter regi ster re-

peats every 131.072, 262.144 or 524.288 INTCLK cycles depending on the CC1 and CC0 bits.

Function EFT0 EFT1 EFTn

Input Capture 1 ICAP1

ICAPA0 ICAPA1 ICA PAn

Input Capture 2 ICAP2

ICAPB0 ICAPB1 ICA PBn

Output Compare 1 OCMP1

OCMPA0 OCMPA1 OCMPAn

Output Compare 2 OCMP2

OCMPB0 OCMPB1 OCMPBn

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ST92141 - EXTENDED FUNCTION TIMER (EF T)

EXTEND ED FU NCTION TI ME R (Cont ’d) Figure 53. Timer Block Diagram

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT COMPARE REGISTER

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT CIRCUIT

1/2 1/4 1/8

8-bit

buffer

ST9 INTERNAL BUS

LATCH1

OCMP1

ICAP1

EXTCLK

INTCLK

EFTI

ICF2ICF1 000OCF2OCF1 TOF

PWMOC1E

EXEDG

IEDG2CC0CC1

OC2E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

ICAP2

LATCH2

OCMP2

8 low

8 high

16 16

CR1

CR2

8 8 8

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT

COMPARE

INPUT

CAPTURE

INPUT

CAPTURE

CC1 CC0

16 BIT

FREE RUNNING

COUNTER

EFTIS

ICISOCISTOIS

CR3

0 10 10

EICIEOCETOI

EEFTI

TOI OCI ICI

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ST92141 - EXTENDED FUNCTION TIMER (EFT)

EXTEND ED FU NCTION TI ME R (Cont’d) 16-bit read sequence: (from either the Counter

The user must read the MSB first, then the LSB value is buffered automatically.

This buffered value rem ains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read.

An overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TO IE bit of the CR1 register is set – TO IS bit of the CR3 register is set (or EFTIS

bit if only global interrupt is available).

If one of these cond itions is false, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done by:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by acces ses t o ACLR register. This feature allows simultaneous use of the overflow f unction and rea ds of t he free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Count ing then resumes from the reset count (MCU awakened by a Reset).

7.3.3.2 External Clock

The external clock (wh ere available) is selected if CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit determi nes the type of level transition on the external clock pin EX TCLK that will trigger the free running counter.

The counter is synchronised with t he falling edge of INTCLK.

At least four falling edges of the INT CLK m ust occur between two consecutive ac tive edges of the external clock; thus the external clo ck frequency must be less than a quarter of the INTCLK frequency.

LSB is buffered

Read MSB

At t0

Read LSB

Returns the buffered

LSB value at t0

At t0 +Dt

Other

instructions

Beginning of the sequence

Sequence completed

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ST92141 - EXTENDED FUNCTION TIMER (EF T)

EXTEND ED FU NCTION TI ME R (Cont’d) Figure 54. Counter Timing Diagram, INTCLK divided by 2

Figure 55. Counter Timing Diagram, INTCLK

divided by 4

Figure 56. Counter Timing Diagram, INTCLK divided by 8

INTCLK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

OVERFLOW FLAG TOF

FFFC FFFD 0000 0001

INTCLK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

OVERFLOW FLAG TOF

INTCLK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

OVERFLOW FLAG TOF

FFFC F FFD

0000

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ST92141 - EXTENDED FUNCTION TIMER (EFT)

EXTEND ED FU NCTION TI ME R (Cont ’d)

7.3.3.3 Input Capture

In this section, the index,

, may be 1 or 2.

The two input capture 16-bit registers (IC1R and IC2R) are used to latch the valu e of the free running counter after a transition detected by the ICAP

pin (see figure 5).

Rregister is a read-only register.

The active transition is software programmable through the IEDG

bit of the Control Register (CRi).

Timing resolution is one count of the free running counter: (

INTCLK

/CC[1:0]

Procedure

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0] (see Table 22

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit.

And select the following in the CR1 register:

– Set the ICIE bit to generat e an interrupt after an

input capture.

– Select the edge of the active tran sition on the

ICAP1 pin with the IEDG1 bit. When an input capture occurs: – ICF

bit is set.

– The IC

R register contains t he val ue of the free running counter on the active transition on the ICAP

pin (see Figure 58).

– A timer interrupt is generated if the ICIE bit i s s e t

and the ICIS bit (or EFTIS bit if only global interrupt is available) is set. O therwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request is done by:

1. Reading the SR register while the ICF

bit is set.

2. An access (read or write) to the IC

iLR

Note: After reading the IC

HR register, transfer of

input capture data is inhibited until the IC

LR regis-

ter is also read. The IC

R register always contains the free running counter value which corresponds to the most recent input capture.

MS Byte LS Byte

RIC

HR ICiLR

Datasheet ST92P141K4M6, ST92P141K4B6, ST92P141 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual