Datasheet ST92F120V9, ST92F120V9Q, ST92F120V6Q, ST92F120V1Q, ST92F120R9T Datasheet (SGS Thomson Microelectronics)

...

Page 1

January 2000 1/320

This ispreliminary information on a new product now in development or undergoing evaluation.Details are subject to change without notice.

Rev. 2.1

ST92F120

8/16-BIT FLASH MCU FAMILY

WITH RAM, EEPROM AND J1850 BLPD

PRELIMINARY DATA

■ Register oriented 8/16 bit CORE with RUN,

WFI, SLOW, HALT and STOP modes

■ 0 - 24 MHz Operation (internal Clock), 4.5 - 5.5

Volt voltage range

■ PLL Clock Generator (3-5 MHz crystal)

■ -40

C to 105oC or -40oCto85oC temperature

range

■ Minimum instruction time: 83 ns (24 MHz

internal clock)

■ Internal Memory: Single Voltage FLASH up to

128 Kbytes, RAM 1.5 to 4 Kbytes, EEPROM 512 to 1K bytes

■ 224 general purpose registers (register file)

available as RAM, accumulators or index pointers

■ TQFP64 or PQFP100 package

■ DMA controller for reduced processor overhead

■ 48 (77 on PQFP100 version) I/O pins

■ 4 external fast interrupts + 1 NMI

■ Up to 16 pins programmable as wake-up or

additional external interrupt with multi-level interrupt handler

■ 16-bit Timer with 8 bit Prescaler, able to be

used as a Watchdog Timer with a large range of service time (HW/SW enabling through dedicated pin)

■ 16-bit Standard Timer that can be used to

generate a time base independent of PLL Clock Generator

■ Two 16-bit independent Extended Function

Timers (EFTs) with Prescaler, 2 Input Captures and two Output Compares (PQFP100 only)

■ Two 16-bit Multifunction Timers, with Prescaler,

2 Input Captures and two Output Compares

■ 8-bit Analog to DigitalConverterallowingupto 8

input channelsonTQFP64 or 16 input channels on PQFP100

■ One or two Serial Communications Interfaces

with asynchronous and synchronous capabilities. Software Management and synchronous mode supported

■ Serial Peripheral Interface (SPI) with Selectable

Master/Slave mode

■ J1850 Byte Level Protocol Decoder (JBLPD)

(on some versions only)

■ Full I

C multiple Master/Slave Interface

supporting ACCESS BUS

■ Rich InstructionSet with 14 Addressing Modes

■ Division-by-zero trap generation

■ Versatile Development Tools, including

Assembler, Linker, C-Compiler, Archiver, Source Level Debugger, Hardware Emulators and Real Time Operating System

DEVICE SUMMARY

Device

J1850

Pack-

age

EFT

I/Os

SCI

Flash RAM E

ST92F120R6T -

TQFP

-48 1 36K 1.5K 512

ST92F120JR6T 1 ST92F120V6Q -

PQFP

100

277

ST92F120JV6Q 1 ST92F120R9T -

TQFP

-481

60K 2K 512

ST92F120JR9T 1 ST92F120V9Q -

PQFP

100

2772

ST92F120JV9Q 1 ST92F120R1T -

TQFP

-481

128K 4K 1K

ST92F120JR1T 1 ST92F120V1Q -

PQFP

100

2772

ST92F120JV1Q 1

PQFP100

TQFP64

Page 2

2/320

Table of Contents

320

1 GENERAL DESCRIPTION . . . . . . ................................................ 7

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 7

1.1.1 ST9+ Core . . . . . . . . . ................................................7

1.1.2 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.3 On-chip Peripherals . . . . . . ............................................ 7

1.2 PIN DESCRIPTION . . .................................................... 10

1.2.1 Electromagnetic Compatibility (EMC) . .................................. 10

1.2.2 I/O Port Alternate Functions ...........................................10

1.2.3 Termination of Unused Pins ...........................................10

1.2.4 Avoidance of Pin Damage . . . . . . . . . . . . . . . . . ........................... 11

1.3 I/O PORTS . . . . . . . . . . . . . . . . . . ...........................................19

1.4 OPERATING MODES .. . . . ...............................................24

2 DEVICE ARCHITECTURE . . . . . . . . . . ...........................................25

2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . ................................25

2.2 MEMORY SPACES . . . . . . . . . . . . . . ........................................ 25

2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2.2 Register Addressing . . . . . . ...........................................27

2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . .............................. 28

2.3.1 Central Interrupt Control Register . . . . . ................................. 28

2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 29

2.3.3 Register Pointing Techniques . . . . . . . . . . . .............................. 30

2.3.4 Paged Registers . . . . ............................................... 33

2.3.5 Mode Register . . . . . . ...............................................33

2.3.6 Stack Pointers . . . . . . . . . . . . . ........................................34

2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . ................................. 36

2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . .................................. 37

2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . .............................. 38

2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........39

2.7 MMU REGISTERS . ...................................................... 39

2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 39

2.7.2 CSR: Code Segment Register . ........................................41

2.7.3 ISR: Interrupt Segment Register . . . . . . ................................. 41

2.7.4 DMASR: DMA Segment Register . . . . . ................................. 41

2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 43

2.8.1 Normal Program Execution . . . . . . . . . . .................................43

2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 43

2.8.3 DMA . . . . . . . . . . . . . . . . . . ...........................................43

3 SINGLE VOLTAGE FLASH & EEPROM . . . . . . . . .................................. 44

3.1 INTRODUCTION . . . . . . . . . . . . . ...........................................44

3.2 FUNCTIONAL DESCRIPTION . . . . . ......................................... 45

3.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 45

3.2.2 Software or Hardware EEPROM Emulation (Device dependent option) . ........ 45

3.2.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 46

3.3 REGISTER DESCRIPTION . ............................................... 47

3.3.1 Control Registers . . . . . . . . . . . . . . . . . . . . . .............................. 47

3.3.2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 50

3.4 WRITE OPERATION EXAMPLE . . . . . . . . .................................... 52

Page 3

3/320

Table of Contents

3.5 EEPROM ..............................................................53

3.5.1 Hardware EEPROM Emulation ........................................53

3.5.2 EEPROM Update Operation . . . . . . . . . . . . .............................. 54

3.6 PROTECTION STRATEGY . ...............................................55

3.6.1 Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 55

3.6.2 Temporary Unprotection .. . . . . . . . . . . .................................57

3.7 FLASH IN-SYSTEM PROGRAMMING . . . . . . . ................................57

3.7.1 First Programming of a virgin Flash . . . . . . . . . . . . . . . . . . . . . . ............... 57

4 REGISTER AND MEMORY MAP ................................................ 59

4.1 INTRODUCTION . . . . . . . . . . . . . ...........................................59

4.2 MEMORY CONFIGURATION .. . . . . . . . . . . . ................................. 59

4.3 ST92F120 REGISTERMAP . . . . . . . . . . . . . ..................................62

5 INTERRUPTS . . ............................................................. 72

5.1 INTRODUCTION . . . . . . . . . . . . . ...........................................72

5.2 INTERRUPT VECTORING ................................................ 72

5.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . ................................. 72

5.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . .................... 73

5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.4 PRIORITY LEVEL ARBITRATION . . . ........................................73

5.4.1 Priority level 7 (Lowest) . . . ...........................................73

5.4.2 Maximum depthof nesting . . . . . . . . . . .................................. 73

5.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.4.4 Dynamic Priority Level Modification . . . . . ................................74

5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . .................................. 74

5.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 77

5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . .............................. 79

5.6.1 Standard External Interrupts . . . . . . . . .................................. 79

5.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . ................................81

5.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........81

5.9 INTERRUPT RESPONSE TIME . ........................................... 82

5.10INTERRUPT REGISTERS . . ...............................................83

5.11WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 86

5.11.1Introduction . . . . ...................................................86

5.11.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 86

5.11.3Functional Description . . . . . . . ........................................ 87

5.11.4Programming Considerations . . . . . . . .................................. 90

5.11.5Register Description . . . . . . . . . ........................................ 91

6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . .................................. 94

6.1 INTRODUCTION . . . . . . . . . . . . . ...........................................94

6.2 DMA PRIORITY LEVELS . . . ...............................................94

6.3 DMA TRANSACTIONS . . . . . . . . . . . ........................................95

6.4 DMA CYCLE TIME . . . . . . . . . . . . . . . ........................................ 97

6.5 SWAP MODE . . . . . . . . . . . . ...............................................97

6.6 DMA REGISTERS . . . . . . . . . . . . ...........................................98

Page 4

4/320

Table of Contents

320

7 RESET AND CLOCK CONTROL UNIT (RCCU) . . . ................................. 99

7.1 INTRODUCTION . . . . . . . . . . . . . ...........................................99

7.2 CLOCK CONTROL UNIT . . . . . . . ........................................... 99

7.2.1 Clock Control Unit Overview . . . . . . . . . . . . . . . ........................... 99

7.3 CLOCK MANAGEMENT . . . . . . . . . . .......................................101

7.3.1 PLL Clock Multiplier Programming . . . . . . . . ............................. 102

7.3.2 CPU Clock Prescaling . . . . . . . . . . . . . .................................102

7.3.3 Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . .......................... 103

7.3.4 Low Power Modes . . . .............................................. 103

7.3.5 Interrupt Generation . . . . . . . . . ....................................... 103

7.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . ............................. 106

7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . .............................109

7.6 RESET/STOP MANAGER . . . . . . .......................................... 111

7.6.1 Reset Pin Timing . . . . ..............................................112

7.7 STOP MODE . . . . . . . . . . . . . . . . . . . .......................................113

8 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

8.1 INTRODUCTION . . . . . . . . . . . . . ..........................................114

8.2 EXTERNAL MEMORY SIGNALS.. . . . . . . . . . . . . . . . .......................... 115

8.2.1 AS: Address Strobe . . .............................................. 115

8.2.2 DS: Data Strobe ................................................... 115

8.2.3 DS2: Data Strobe 2 . . . . . . . . . .......................................115

8.2.4 RW: Read/Write . . . . . . . . . . . . . . . . . . . . . . ............................. 118

8.2.5 BREQ, BACK: Bus Request, Bus Acknowledge . . . . . . . . . . . . . . . . ..........118

8.2.6 PORT 0 . . . . . . . . . . . . . . . .......................................... 119

8.2.7 PORT 1 . . . . . . . . . . . . . . . .......................................... 119

8.2.8 WAIT: External Memory Wait . . . . . . ................................... 119

8.3 REGISTER DESCRIPTION . .............................................. 120

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . .......................................123

9.1 INTRODUCTION . . . . . . . . . . . . . ..........................................123

9.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 123

9.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . .......................... 123

9.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . ..........128

9.5.1 Pin Declared as I/O . . .............................................. 128

9.5.2 Pin Declared as an Alternate Input . . . . . ...............................128

9.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . ....... 128

9.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . ..........128

10 ON-CHIP PERIPHERALS . . . . . . .............................................. 129

10.1TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . ................................. 129

10.1.1Introduction . . . . ..................................................129

10.1.2Functional Description . . . . . . . .......................................130

10.1.3Watchdog Timer Operation . . . . . . . . . . ................................ 131

10.1.4WDT Interrupts . . . . . . . . . . . . . .......................................133

10.1.5Register Description . . . . . . . . . .......................................134

10.2STANDARD TIMER (STIM) . .............................................. 136

10.2.1Introduction . . . . ..................................................136

10.2.2Functional Description . . . . . . . .......................................137

Page 5

5/320

Table of Contents

10.2.3Interrupt Selection . . . .............................................. 138

10.2.4Register Mapping .. . . . . . . . . . . . . . . . . . . . . . . .......................... 138

10.2.5Register Description . . . . . . . . . .......................................139

10.3EXTENDED FUNCTION TIMER (EFT) . . . . . . ................................ 140

10.3.1Introduction . . . . ..................................................140

10.3.2Main Features . . . . . . . . . . . . . . . . . . . . ................................140

10.3.3Functional Description . . . . . . . .......................................140

10.3.4Interrupt Management . . . . . . . . . . . . . .................................150

10.3.5Register Description . . . . . . . . . .......................................152

10.4MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . ................... 160

10.4.1Introduction . . . . ..................................................160

10.4.2Functional Description . . . . . . . .......................................162

10.4.3Input Pin Assignment . . . . . ..........................................165

10.4.4Output Pin Assignment . . . . . . ....................................... 169

10.4.5Interrupt and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 171

10.4.6Register Description . . . . . . . . . .......................................173

10.5SERIAL COMMUNICATIONS INTERFACE (SCI) . .............................184

10.5.1Introduction . . . . ..................................................184

10.5.2Functional Description . . . . . . . .......................................185

10.5.3SCI Operating Modes . . . . . . . . . . . . . . . . . ............................. 186

10.5.4Serial Frame Format ............................................... 189

10.5.5Clocks And Serial Transmission Rates . . . . ............................. 192

10.5.6SCI Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 192

10.5.7Input Signals . . . . . . . . . . . . . . . . . . . . . . . . ............................. 194

10.5.8Output Signals . . . . . . .............................................. 194

10.5.9Interrupts and DMA . . . . . . . . . . . . . . . . . ...............................195

10.5.10Register Description . .............................................. 198

10.6SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . ..........209

10.6.1Introduction . . . . ..................................................209

10.6.2Main Features . . . . . . . . . . . . . . . . . . . . ................................209

10.6.3General description . . . . . . ..........................................209

10.6.4Functional Description . . . . . . . .......................................211

10.6.5Interrupt Management . . . . . . . . . . . . . .................................218

10.6.6Register Description . . . . . . . . . .......................................219

10.7 I2C BUS INTERFACE . . . . . . . . . . . . . . . . . . ................................. 221

10.7.1Introduction . . . . ..................................................221

10.7.2Main Features . . . . . . . . . . . . . . . . . . . . ................................221

10.7.3Functional Description . . . . . . . .......................................222

10.7.4I2C State Machine . . . . . . . ..........................................224

10.7.5Interrupt Features . . . .............................................. 229

10.7.6DMA Features . . . . . . .............................................. 230

10.7.7Register Description . . . . . . . . . .......................................232

10.8J1850 BYTE LEVEL PROTOCOL DECODER (JBLPD) . . . . . . . . . . . .............. 243

10.8.1Introduction . . . . ..................................................243

10.8.2Main Features . . . . . . . . . . . . . . . . . . . . ................................243

10.8.3Functional Description . . . . . . . .......................................245

10.8.4Peripheral Functional Modes . . ....................................... 256

10.8.5Interrupt Features . . . .............................................. 257

10.8.6DMA Features . . . . . . .............................................. 259

Page 6

6/320

Table of Contents

320

10.8.7Register Description . . . . . . . . . .......................................263

10.9EIGHT-CHANNELANALOG TO DIGITAL CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . 284

10.9.1Introduction . . . . ..................................................284

10.9.2Functional Description . . . . . . . .......................................285

10.9.3Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . ...............................287

10.9.4Register Description . . . . . . . . . .......................................288

11 ELECTRICAL CHARACTERISTICS . . . . ........................................ 292

12 GENERAL INFORMATION ................................................... 319

12.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . ..........................319

Page 7

7/320

ST92F120 - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92F120 microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central Processing Unit(CPU),theRegisterFile, theInterrupt and DMA controller, and the Memory Management Unit. The MMU allows a single linear address space of up to4 Mbytes.

Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt/DMA bus which connects the interrupt and DMA controllersin the on-chip peripherals with the core.

This multiple busarchitecture makes the ST9 family deviceshighlyefficient foraccessing onand offchip memory and fast exchange of data with the on-chip peripherals.

The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.

The powerful I/O capabilities demanded by microcontroller applications are fulfilled by the ST92F120 with48(TQFP64) or 77 (PQFP100)I/O lines dedicated to digital Input/Output. These lines are grouped into up to ten 8-bit I/O Ports and can be configuredonabit basis under software control to provide timing, status signals, an address/data bus for interfacing to the external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O. Two memory spaces are available to support this wide range of configurations: a combined Program/Data Memory

Space and the internal Register File, which includes the control and status registers of the onchip peripherals.

1.1.2 External Memory Interface

PQFP100 devices have a 16-bit external address bus allowing them to address up to 64K bytes of external memory. TQFP64 devices have an 11-bit external address bus for addressing up to 2K bytes.

1.1.3 On-chip Peripherals

Two 16-bit MultiFunction Timers, each with an 8 bit Prescaler and 12 operating modes allow simple use for complex waveform generation and measurement, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer.

On PQFP100 devices, two Extended Function Timers provide further timing and signal generation capabilities.

A Standard Timer can be used to generate a stable time base independent from the PLL.

An I2C interface provides fast I2C and Access Bus support.

The SPI is a synchronous serial interface for Master and Slave device communication. It supports single master and multimaster systems.

A J1850 Byte Level Protocol Decoder is available (on some devices only) for communicating with a J1850 network.

In addition, there is an16 channel Analog to Digital Converters with integral sample and hold, fast conversion time and 8-bit resolution. In the TQFP64 version only 8 input channels are available.

Completing the device are two or one full duplex Serial Communications Interfaces with an integral generator, asynchronous and synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels.

Finally, a programmable PLL Clock Generator allows the usage of standard 3 to 5 MHz crystals to obtain a large range of internal frequencies up to 24MHz. Low power Run (SLOW), Wait For Interrupt, low power Wait For Interrupt, STOP and HALT modes are also available.

Page 8

8/320

ST92F120 - GENERAL DESCRIPTION

Figure 1. ST92F120JR: Architectural Block Diagram (TQFP64 version)

256 bytes

RAM

1.5/2/4 Kbytes

ST9 CORE

8/16 bits

CPU

Interrupt

Management

MEMORY BUS

RCCU

Ext.

MEM.

ADDRESS

DATA

Ext. MEM.

AD-

DRESS

WATCHDOG

AS DS

WAIT

NMI

DS2

MISO MOSI SCK SS

A[10:8]

A[7:0] D[7:0]

ST. TIMER

SPI

SDAI SDAO SCLI SCLO

I2C BUS

SCI 0

FLASH

36/60/128

Kbytes

TXCLK0 RXCLK0 SIN0 DCD0 SOUT0 CLKOUT0 RTS0

WDOUT

HW0SW1

STOUT

All alternate functions (

Italic characters

) are mapped on Port2, Port3, Port4, Port5, Port6,and Port7

Fully Prog.

I/Os

P0[7:0] P1[2:0] P2[7:0] P3[7:4] P4[7:4] P5[7:0] P6[5:2,0] P7[7:0]

MF TIMER0

TINPA0

TOUTA0

TINPB0

TOUTB0

TINPA1

TOUTA1

TINPB1

TOUTB1

INT[6:0]

WKUP[15:0]

MF TIMER1

EEPROM

512 /1K bytes

OSCIN

OSCOUT

RESET

CLOCK2/8

INTCLK

A/D CONV. 0

A0IN[7:0] EXTRG

VPWI

VPWO

J1850

JBLPD

(optional)

Page 9

9/320

ST92F120 - GENERAL DESCRIPTION

Figure 2. ST92F120JV: Architectural Block Diagram (PQFP100 version)

256 bytes

ST9 CORE

8/16 bits

CPU

Interrupt

Management

MEMORY BUS

RCCU

WATCHDOG

AS DS

WAIT

NMI

DS2

MISO MOSI SCK SS

EF TIMER0

ST. TIMER

SPI

SCI 0

TXCLK0 RXCLK0 SIN0 DCD0 SOUT0 CLKOUT0 RTS0

WDOUT

HW0SW1

STOUT

ICAPA0

OCMPA0

ICAPB0

OCMPB0

EXTCLK0

Fully Prog.

I/Os

P0[7:0] P1[7:0] P2[7:0] P3[7:1] P4[7:0] P5[7:0] P6[5:0] P7[7:0] P8[7:0] P9[7:0]

TXCLK1 RXCLK1 SIN1 DCD1 SOUT1 CLKOUT1 RTS1

MF TIMER0

TINPA0

TOUTA0

TINPB0

TOUTB0

ICAPA1

OCMPA1

ICAPB1

OCMPB1

EXTCLK1

TINPA1

TOUTA1

TINPB1

TOUTB1

INT[6:0]

WKUP[15:0]

EF TIMER1

MF TIMER1

SCI 1

OSCIN

OSCOUT

RESET

CLOCK2/8

CLOCK2

INTCLK

A/D CONV. 0

A0IN[7:0] EXTRG

A/D CONV. 1

A1IN[7:0]

SDAI SDAO SCLI SCLO

I2C BUS

VPWI

VPWO

J1850

JBLPD

A[7:0] D[7:0]

A[15:8]

Ext.

MEM.

ADDRESS

DATA

Ext. MEM.

AD-

DRESS

RAM

1.5/2/4 Kbytes

FLASH

36/60/128

Kbytes

EEPROM

512 /1K bytes

(optional)

All alternate functions (

Italic characters

) are mapped on Port2, Port3,Port4, Port5, Port6, Port7, Port8 and Port9

* Available on some versions only

Page 10

10/320

ST92F120 - GENERAL DESCRIPTION

1.2 PIN DESCRIPTION AS. Address Strobe (output, active low, 3-state).

Address Strobe is pulsed low once at the beginning of each memory cycle. The rising edge of AS indicates that address, Read/Write (RW), and Data signals are valid for memory transfers.

DS. Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS. During a read cycle, Data In must be valid prior to the trailing edge of DS. When the ST9 accesses on-chip memory, DS is held high during the whole memory cycle.

RESET. Reset (input, active low). The ST9 is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h.

RW. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for external memory transactions. RW is low when writing to external memory, and high for all other transactions.

OSCIN, OSCOUT. Oscillator (input and output). These pins connect a parallel-resonant crystal, or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter.

HW0SW1. When connected to VDDthrough a 1K pull-up resistor, the software watchdog option is selected. When connected to VSSthrough a 1K pull-down resistor, the hardware watchdog option is selected.

VPWO. This pin is the output line of the J1850 peripheral (JBLPD). It is available only on some devices. On devices without JBLPD peripheral, this pin must not be connected.

P0[7:0], P1[2:0] or P1[7:0]

(Input/Output, TTL or

CMOS compatible)

. 11 lines (TQFP64 devices) or 16 lines (PQFP100 devices) providing the external memory interface for addressing 2K or 64 K bytes of externalmemory.

P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4.[7:4], P5[7:0], P6[5:2,0], P7[7:0]

I/O Port Lines (Input/

Output, TTL or CMOS compatible)

. I/O lines grouped into I/O ports of 8 bits, bit programmable under software control as general purpose I/O or as alternate functions.

P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]

Additional I/O Port Lines available on PQFP100 versions only.

AVDD. Analog VDDof the Analog to Digital Con- verter (common for A/D 0 and A/D 1).

AVSS. Analog VSSof the Analog to Digital Con- verter (common for A/D 0 and A/D 1).

VDD. Main Power Supply Voltage. Four pins are available on PQFP100 versions, two on TQFP64 versions. The pins are internally connected.

VSS. Digital Circuit Ground. Four pins are available on PQFP100 versions, two on TQFP64 versions. The pins are internally connected.

VPP. Power Supply Voltage for Flash test purposes. This pin is bonded and must be kept to 0 in user mode.

REG

. 3V regulator output.

1.2.1 Electromagnetic Compatibility (EMC)

To reduce the electromagnetic interference thefollowing features have been implemented:

– A low power oscillator is included with a control-

led gain to reduce EMI and the power consumption in Halt mode.

– Two or Four pairs of digital power supply pins

(VDD,VSS) are located on each side of the PQFP100 package (2 pairs on TQFP64).

– Digital and analog power supplies are complete-

ly separated.

– Digital power supplies for internal logic and I/O

ports are separated internally.

– Internal decoupling capacitance is located be-

tween VDDand VSS.

Note: Each pair of digital VDD/VSSpins should be externally connected by a 10 µF chemical pulling capacitor and a 100 nF ceramic chip capacitor.

1.2.2 I/O Port Alternate Functions

Each pin of the I/O ports of the ST92F120 may assume software programmable Alternate Functions as shown in Section 1.3.

1.2.3 Termination of Unused Pins

The ST9 deviceis implemented using CMOS technology; therefore unused pins must be properly terminated in order to avoid application reliability problems. In fact, as shown in Figure 3, the standard input circuitry is based on the CMOS inverter structure.

Page 11

11/320

ST92F120 - GENERAL DESCRIPTION

Figure 3. CMOS basic inverter

When an input is kept at logic zero, the N-channel transistor is off, while the P-channel is on and can conduct. The opposite occurs when an input is kept at logic one. CMOS transistors are essentially linear devices with relatively broad switching points. During commutation, the input passes through midsupply, and there is a region of input voltage values where both P and N-channel transistors are on. Since normally the transitions are fast, there is a very short time in which a current can flow: once the switching is completed there is no longer current. This phenomenon explains why the overall current depends on the switching rate: the consumption is directly proportional to the number of transistors inside the device which are in the linear region during transitions, charging and discharging internal capacitances.

In order to avoid extra power supply current, it is important to bias input pins properly when not used. In fact, if the input impedance is very high, pins can float, when not connected, either to a midsupply level or can oscillate (injecting noise in the device).

Depending on the specific configuration of each I/O pin on different ST9 devices, it can be more or less critical to leave unused pins floating. For this reason, on most pins, the configuration after RESET enables an internal weak pull-up transistor in order to avoid floating conditions. For other pins this is intrinsically forbidden, like for the true opendrain pins. In any case, the application software must program the right state for unused pins to avoid conflicts with external circuitry (whichever it is: pull-up, pull-down, floating, etc.).

The suggested method of terminating unused I/O is to connect an external individual pull-up or pulldown for each pin, even though initialization software can force outputs to a specified and defined

value, during a particular phaseof the RESET routine there could be an undetermined status at the input section.

Usage of pull-ups and/or pull-downs is preferable in place of direct connection to VDDor VSS. If pullup or pull-down resistors are used, inputs can be forced for test purposes to a different value, and outputs can be programmed to both digital levels without generating high current drain due to the conflict.

Anyway, during system verification flow, attention must be paid to reviewing the connection of each pin, in order to avoid potential problems.

1.2.4 Avoidance of Pin Damage

Although integrated circuit data sheets provide the user with conservative limits and conditions in order to prevent damage, sometimes it is useful for the hardware system designer to know the internal failure mechanisms: the risk of exposure to illegal voltages and conditions can be reduced by smart protection design.

It is not possible to classify and to predict all the possible damage resulting from violating maximum ratings and conditions, due to the large number of variables that come into play in defining the failures: in fact, when an overvoltage condition is applied, the effects on the device can vary significantly depending on lot-to-lot process variations, operating temperature, external interfacing of the ST9 with other devices, etc.

In the following sections, background technical information is given in order to help system designers to reduce risk of damage to the ST9 device.

1.2.4.1 Electrostatic Discharge and Latchup

CMOS integrated circuits are generally sensitive to exposure to highvoltage static electricity, which can induce permanent damage to the device: a typical failure is the breakdown of thin oxides, which causeshigh leakage current and sometimes shorts.

Latchup is another typical phenomenon occurring in integrated circuits: unwanted turning on of parasitic bipolar structures, or silicon-controlled rectifiers (SCR), may overheat and rapidly destroy the device. These unintentional structures are composed of P and N regions which work as emitters, bases and collectors of parasitic bipolar transistors: the bulk resistance of the silicon in the wells and substrate act as resistors on the SCR structure. Applying voltages below VSSor above VDD, and when the level of current is able to generatea

INOUT

Page 12

12/320

ST92F120 - GENERAL DESCRIPTION

voltage drop across the SCR parasitic resistor, the SCR may be turned on; to turn off the SCR it is necessary to remove the power supply from the device.

The present ST9 design implements layout and process solutions to decrease the effects of electrostatic discharges (ESD) and latchup. Of course it is not possible to test all devices, due to the destructive nature of the mechanism; in order to guarantee product reliability, destructive tests are carried out on groups of devices, according to STMicroelectronics internal Quality Assurance standards and recommendations.

1.2.4.2 Protective Interface

Although ST9 input/output circuitry has been designed taking ESD and Latchup problems into ac-

count, for those applications and systems where ST9 pins are exposed to illegal voltages and high current injections, the user is strongly recommended to implement hardware solutions which reduce the risk ofdamage to the microcontroller: low-pass filters and clamp diodes are usually sufficient in preventing stress conditions.

The risk of having out-of-range voltages and currents is greater for those signals coming from outside the system, where noise effect or uncontrolled spikes could occur with higher probability than for the internal signals; it must be underlined that in somecases, adoption of filters or other dedicated interface circuitries might affect global microcontroller performance, inducingundesired timing delays, and impacting the global system speed.

Figure 4. Digital Input/Output - Push-Pull

OUTPUT BUFFER

INPUT

BUFFER

ESDPR O TE CT ION

CIRCUITRY

PORTCIRCUITRY

I/O CIRCUITRY

Page 13

13/320

ST92F120 - GENERAL DESCRIPTION

1.2.4.3 Internal Circuitry: Digital I/O pin

In Figure 4a schematic representation of an ST9 pin able to operate either as an input or as an output is shown. The circuitry implements a standard input buffer and a push-pull configuration for the output buffer. It is evident that although it is possible to disable the output buffer when the input section is used, the MOS transistors of the buffer itself can still affect the behaviour of the pin when exposed to illegal conditions. In fact, the P-channel transistor of the output buffer implements a direct diode toVDD(P-diffusionof the drain connected to the pin and N-well connected to VDD), while the Nchannel of the output buffer implements a diode to VSS(P-substrate connected to VSS and N-diffusion of the drain connected to the pin). In parallel to these diodes, dedicated circuitry is implemented to protect the logic from ESD events (MOS, diodes and input series resistor).

The most important characteristic of these extra devices is that they must not disturb normal operating modes, while acting during exposure to over

limit conditions, avoiding permanent damage to the logic circuitry.

All I/O pins can generally be programmed to work also as open-drain outputs, by simply writing in the corresponding register of the I/O Port. The gate of the P-channel of the output buffer is disabled: it is important tohighlight that physically the P-channel transistor is still present, so the diode to V

works. In some applications it can occur that the voltage applied to the pin is higher than the V

value (supposing the external line is kept high, while the ST9 power supply is turned off): this condition will inject current through the diode, risking permanent damages to the device.

In any case, programming I/O pins as open-drain can help when several pins in the system are tied to the same point: of course software must pay attention to program only one of them as output at any time, to avoid output driver contentions; it is advisable to configure these pins as output opendrain in order to reduce the risk of current contentions.

Figure 5. Digital Input/Output - True Open Drain Output

OUTPUT

BUFFER

INPUT

BUFFE R

ESDPROT EC T ION

CIRCUITRY

PORT CIRCUITRY

I/OCIRCUITRY

Page 14

14/320

ST92F120 - GENERAL DESCRIPTION

In Figure 6 a true open-drain pin schematic is shown. In this case all paths to VDDare removed (P-channel driver, ESD protection diode, internal weak pull-up) in order to allow the system to turn off the power supply of the microcontroller and keep the voltage level at the pin high without injecting current in the device. This is a typical condition which can occur when several devices interface a serial bus: if one device is not involved in the communication, it can be disabled by turning off its power supply to reduce the system current consumption.

When an illegal negative voltage level is applied to the ST9 I/O pins (both versions, push-pull and true open-drain output) the clamp diode is always present and active (see ESD protection circuitry and N-channel driver).

1.2.4.4 Internal Circuitry: Analog Input pin

Figure 6 shows the internal circuitry used for analog input. It is substantially a digital I/O with an added analog multiplexer for the A/D Converter input signal selection.

The presence of the multiplexer P-channel and Nchannel can affect the behaviour of the pin when exposed to illegal voltage conditions. These transistors are controlled by a low noise logic, biased through AVDDand AVSSincluding P-channel Nwell: it is important to always verify the input voltage value with respect to both analog power supply and digital power supply, in order to avoid unintended current injections which (if not limited) could destroy the device.

Figure 6. Digital Input/Output - Push-Pull Output - Analog Multiplexer Input

OUTPUT

BUFFER

IN P UT

BUFFER

ESDPRO T EC T ION

CIRCUITRY

PORTCIR CUIT RY

I/OCIRCUITRY

Page 15

15/320

ST92F120 - GENERAL DESCRIPTION

1.2.4.5 Power Supply and Ground

As already said for the I/O pins, in order to guarantee ST9 compliancy with respect to QualityAssurance recommendations concerning ESD and Latchup, dedicated circuits are added to the different power supply and ground pins (digital and analog). These structures create preferred paths for the high current injected during discharges, avoiding damage to active logic and circuitry. It is important for the system designer to take this added circuitry into account, which is not always transparent withrespect to the relative level of voltages applied to the different power supply and ground pins. Figure 7 shows schematically the protection net implemented on ST9 devices, composedof diodes and other special structures.

The clamp structure between the VDDand V

pins is designed to be active during very fast tran-

sitions (typical of electrostatic discharges). Other paths are implemented through diodes: they limit the possibility of positively differentiating AV

and VDD(i.e. AVDD>VDD); similar considerations are valid for AVSSand VSSdue to the back-toback diode structure implemented between the two pins. Anyway, it must be highlighted that, because VSSand AVSSare connected to the substrate of the silicon die (even though in different areas of the die itself), they represent the reference point from which all other voltages are measured, and it is recommended to never differentiate AV

from VSS. Note: If more than one pair of pins for VSSand

VDDisavailable on the device, they are connected internally and the protection net diagram remains the same as shown in Figure 7.

Figure 7. Power Supplyand Ground configuration

Page 16

16/320

ST92F120 - GENERAL DESCRIPTION

Figure 8. ST92F120: Pin configuration (top-view TQFP64)

* Alternate function forCAN interface, reserved for future use: P5.0/TXCAN0; P5.1/RXCAN0. ** On devices without JBPLD peripheral, this pin must notbe connected. *** V

must be keptlow in standard operating mode.

WAIT/WKUP5/P5.0*

WKUP6/WDOUT/P5.1*

SIN0/WKUP2/P5.2

SOUT0/P5.3

TXCLK0/CLKOUT0/P5.4

RXCLK0/WKUP7/P5.5

DCD0/WKUP8/P5.6

WKUP9/RTS0/P5.7

EXTCLK1/WKUP4/P4.4

EXTRG/STOUT/P4.5

SDA/P4.6

WKUP1/SCL/P4.7

EXTCLK0/SS/P3.4

MISO/P3.5 MOSI/P3.6

SCK/WKUP0/P3.7

HW0SW1

RESET

OSCOUT

OSCIN

VDDVSSP7.7/A0IN7/WKUP13

P7.6/A0IN6/WKUP12

P7.5/A0IN5/WKUP11

P7.4/A0IN4/WKUP3

P7.3/A0IN3

P7.2/A0IN2

P7.1/A0IN1

P7.0/A0IN0

AVSSAV

VPWO** P6.5/WKUP10/INTCLK/VPWI P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS

TINPA0/P2.0

TINPB0/P2.1

TOUTA0/P2.2

TOUTB0/P2.3

TINPA1/P2.4

TINPB1/P2.5

TOUTA1/P2.6

TOUTB1/P2.7

REG

***V

A8/P1.0

A9/P1.1

A10/P1.2

N.C. = Not connected (no physical bonding wire)

6463 6261 6059585756555453 52515049

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1718192021222324 29 30313225262728

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ST92 F12 0

Page 17

17/320

ST92F120 - GENERAL DESCRIPTION

Figure 9. ST92F120: Pin Configuration (top-view PQFP100)

* Alternate function forCAN interface, reserved for future use: P5.0/TXCAN0; P5.1/RXCAN0 ** Pin reserved forfuture use: 49- RXCAN1; 50 -TXCAN1 *** V

must be kept low in standard operating mode.

RXCLK1/P9.3

DCD1/P9.4

RTS1/P9.5

CLOCK2/P9.6

P9.7

WAIT/WKUP5/P5.0*

WKUP6/WDOUT/P5.1*

SIN0/WKUP2/P5.2

SOUT0/P5.3

TXCLK0/CLKOUT0/P5.4

RXCLK0/WKUP7/P5.5

DCD0/WKUP8/P5.6

WKUP9/RTS0/P5.7

ICAPA1/P4.0

P4.1

OCMPA1/P4.2

ICAPB1/OCMPB1/P4.3

EXTCLK1/WKUP4/P4.4

EXTRG/STOUT/P4.5

SDA/P4.6

WKUP1/SCL/P4.7

ICAPB0/P3.1

ICAPA0/OCMPA0/P3.2

OCMPB0/P3.3

EXTCLK0/SS/P3.4

MISO/P3.5 MOSI/P3.6

SCK/WKUP0/P3.7

P9.2/TXCLK1/CLKOUT1

P9.1/SOUT1

P9.0/SIN1

HW0SW1

RESET

OSCOUT

OSCIN

VDDVSSP7.7/A0IN7/WKUP13

P7.6/A0IN6/WKUP12

P7.5/A0IN5/WKUP11

P7.4/A0IN4/WKUP3

P7.3/A0IN3

P7.2/A0IN2

P7.1/A0IN1

P7.0/A0IN0

AVSSAVDDP8.7/A1IN0

P8.6/A1IN1 P8.5/A1IN2 P8.4/A1IN3 P8.3/A1IN4 P8.2/A1IN5 P8.1/A1IN6/WKUP15 P8.0/A1IN7/WKUP14 VPWO P6.5/WKUP10/INTCLK/VPWI P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 V

P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12

REG

TINPA0/P2.0

TINPB0/P2.1

TOUTA0/P2.2

TOUTB0/P2.3

TINPA1/P2.4

TINPB1/P2.5

TOUTA1/P2.6

TOUTB1/P2.7

REG

***V

A8/P1.0

A9/P1.1

A10/P1.2

A11/P1.3

**N.C.

ST92F120

N.C. = Not connected (no physical bonding wire)

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

49484746454443424140393837363534333231

81828384858687888990919293949596979899100

Page 18

18/320

ST92F120 - GENERAL DESCRIPTION

Table 1. ST92F120 Power Supply Pins Table 2. ST92F120 Primary Function Pins

Figure 10. Recommended connections for V

REG

Note : For future compatibility with shrinked versions, the V

REG

pins should be connected to a minimum of 600 nF (total). Special care should be taken to minimize the distance between the ST9 microcontroller and the capacitors.

Name Function

QFP64

QFP100

Main Power Supply Voltage

( pins internally connected)

-18

27 42

-65

60 93

Digital Circuit Ground

(pins internally connected)

-17

26 41

-64

59 92

Analog Circuit Supply Voltage 49 82

Analog Circuit Ground 50 83

Must be kept low in standard

operating mode

29 44

REG

3V regulator output 28

31 43

Name Function

QFP64

QFP100

AS Address Strobe 34 56 DS Data Strobe 33 55

RW Read/Write 17 32

OSCIN Oscillator Input 61 94

OSCOUT Oscillator Output 62 95

RESET

Reset to initialize theMicro-

controller

63 96

HW0SW1

Watchdog HW/SW enabling

selection

64 97

VPWO

J1850 JBLPD Output. On

devices without JBPLD pe-

ripheral, this pin must not be

connected.

48 73

300 nF 300 nF

QFP100 QFP 64

600 nF

Page 19

19/320

ST92F120 - GENERAL DESCRIPTION

1.3 I/O PORTS

Port 0 and Port 1 provide theexternal memory interface. All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trigger is present). Each bit can be programmed individually (Refer to the I/O ports chapter).

Internal Weak Pull-up

As shown in Table 3, not all input sections implement a Weak Pull-up. This means that the pull-up must be connected externally when the pin is not used or programmed as bidirectional.

TTL/CMOS Input

For all those port bits where no input schmitt trigger is implemented, it is always possible to program the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit. Refer I/O Ports Chapter to the section titled “Input/ Output Bit Configuration”.

Schmitt Trigger Input

Two different kind ofSchmitt Trigger circuitries are implemented: Standard and High Hysteresis. Standard Schmitt Trigger is widely used (see Table 3), while the High Hysteresis one is present on

the NMI and VPWI input function pins mapped on Port 6 [5:4] (see Table 4).

All inputs which can be used for detecting interrupt events have been configured with a “standard” Schmitt Trigger, apart from, as already said, the NMI pin which implements the “High Hysteresis” version. In this way, all interrupt lines are guaranteed as “level sensitive”.

Push-Pull/OD Output

The output buffer can be programmed as pushpull or open-drain: attention must be paid to the fact that the open-drain option corresponds only to a disabling of P-channel MOS transistor of the buffer itself: it is still present and physically connected to thepin. Consequentlyit is notpossible to increase the output voltage on the pin over VDD+0.3 Volt, to avoid direct junction biasing.

Pure Open-drain Output

The user can increase the voltage on an I/O pin over VDD+0.3 Volt where the P-channel MOS transistor is physically absent: this is allowed on all “Pure Open Drain” pins. Of course, in this case the push-pull option is not available and any weak pull-up must implemented externally.

Table 3. I/O Port Characteristics

Legend: WPU = Weak Pull-Up, OD = Open Drain

Input Output Weak Pull-Up Reset State

Port 0[7:0] TTL/CMOS Push-Pull/OD No Bidirectional Port 1[7:0] TTL/CMOS Push-Pull/OD No Bidirectional Port 2[1:0]

Port 2[3:2] Port 2[5:4] Port 2[7:6]

Schmitt trigger TTL/CMOS Schmitt trigger TTL/CMOS

Push-Pull/OD Pure OD Push-Pull/OD Push-Pull/OD

Yes No Yes Yes

Input Input CMOS Input Input CMOS

Port 3[2:1] Port 3.3 Port 3[7:4]

Schmitt trigger TTL/CMOS Schmitt trigger

Push-Pull/OD Push-Pull/OD Push-Pull/OD

Yes Yes Yes

Input Input CMOS Input

Port 4.0, Port 4.4 Port 4.1 Port 4.2, Port 4.5 Port 4.3 Port 4[7:6]

Schmitt trigger TTL/CMOS TTL/CMOS Schmitt trigger Schmitt trigger inside I/O cell

Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Pure OD

No Yes Yes Yes No

Input Bidirectional WPU Input CMOS Input Input

Port 5[2:0], Port [7:4] Port 5.3

Schmitt trigger TTL/CMOS

Push-Pull/OD Push-Pull/OD

No Yes

Input Input CMOS

Port 6[3:0] Port 6[5:4]

Schmitt trigger High hysteresis Schmitt trigger inside I/O cell

Push-Pull/OD Push-Pull/OD

Yes Yes (inside I/O cell)

Input Input

Port 7[7:0] Schmitt trigger Push-Pull/OD Yes Input Port 8[1:0]

Port 8[7:2]

Schmitt trigger Schmitt trigger

Push-Pull/OD Push-Pull/OD

Yes Yes

Input Bidirectional WPU

Port 9[7:0] Schmitt trigger Push-Pull/OD Yes Bidirectional WPU

Page 20

20/320

ST92F120 - GENERAL DESCRIPTION

How to Configure the I/O ports

To configure the I/O ports, use the information in Table 3, Table 4 andthe Port Bit Configuration Table in the I/O Ports Chapter (See page 125).

Input Note = the hardware characteristics fixed for each port line in Table3.

– If Input note = TTL/CMOS, either TTL or CMOS

input level can be selected by software.

– If Input note = Schmitt trigger, selecting CMOS

or TTL input by software has no effect, the input will always be Schmitt Trigger.

Alternate Functions (AF) = More than one AF cannot beassigned to an I/O pin at the same time:

An alternate function can be selected as follows. AF Inputs: – AF is selected implicitly by enabling the corre-

sponding peripheral. Exception to this areA/Dinputs which must be explicitly selected as AF by

software. AF Outputs or Bidirectional Lines: – In the case of Outputs or I/Os, AF is selected ex-

plicitly by software.

Example 1: SCI input

AF: SIN0, Port: P5.2, Input note: Schmitt Trigger. Write the port configuration bits: P5C2.2=1

P5C1.2=0 P5C0.2 =1

Enable the SCI peripheral by software as described in the SCI chapter.

Example 2: SCI output

AF: SOUT0, Port: P5.3, Output note: Push-Pull/OD.

Write the port configuration bits (for AF OUT PP): P5C2.3=0

P5C1.3=1 P5C0.3 =1

Example 3: External Memory I/O

AF: A0/D0, Port : P0.0, Input Note: TTL/CMOS Write the port configuration bits: P0C2.0=1

P0C1.0=1 P0C0.0 =1

Example 4: Analog input

AF: A0IN0, Port : 7.0, Input Note: does not apply to analog input

Write the port configuration bits: P7C2.0=1

P7C1.0=1 P7C0.0 =1

Page 21

21/320

ST92F120 - GENERAL DESCRIPTION

Table 4. I/O Port Alternate Functions

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

TQFP64 PQFP100

P0.0

All ports useable for general purpose I/O (input, output or bidirectional)

35 57 A0/D0 I/O Address/Data bit 0 P0.1 36 58 A1/D1 I/O Address/Data bit 1 P0.2 37 59 A2/D2 I/O Address/Data bit 2 P0.3 38 60 A3/D3 I/O Address/Data bit 3 P0.4 39 61 A4/D4 I/O Address/Data bit 4 P0.5 40 62 A5/D5 I/O Address/Data bit 5 P0.6 41 63 A6/D6 I/O Address/Data bit 6 P0.7 42 66 A7/D7 I/O Address/Data bit 7 P1.0 30 45 A8 I/O Address bit 8 P1.1 31 46 A9 I/O Address bit 9 P1.2 32 47 A10 I/O Address bit 10 P1.3 - 48 A11 I/O Address bit 11 P1.4 - 51 A12 I/O Address bit 12 P1.5 - 52 A13 I/O Address bit 13 P1.6 - 53 A14 I/O Address bit 14 P1.7 - 54 A15 I/O Address bit 15 P2.0 18 33 TINPA0 I Multifunction Timer 0 - Input A P2.1 19 34 TINPB0 I Multifunction Timer 0 - Input B P2.2 20 35 TOUTA0 O Multifunction Timer 0 - Output A P2.3 21 36 TOUTB0 O Multifunction Timer 0 - Output B P2.4 22 37 TINPA1 I Multifunction Timer 1 - Input A P2.5 23 38 TINPB1 I Multifunction Timer 1 - Input B P2.6 24 39 TOUTA1 O Multifunction Timer 1 - Output A P2.7 25 40 TOUTB1 O Multifunction Timer 1 - Output B P3.1 - 24 ICAPB0 I Ext. Timer 0 - Input Capture B

P3.2 - 25

ICAPA0 I Ext. Timer0 - Input Capture A OCMPA0 O Ext. Timer0 - Output Compare A

P3.3 - 26 OCMPB0 O Ext. Timer 0 - Output Compare B

P3.4 13 27

EXTCLK0 I Ext. Timer 0 - Input Clock

SS I SPI - Slave Select P3.5 14 28 MISO I/O SPI - Master Input/Slave Output Data P3.6 15 29 MOSI I/O SPI - Master Output/SlaveInput Data

P3.7 16 30

SCK I SPI - Serial Input Clock

WKUP0 I Wake-up Line 0

SCK O SPI - Serial Output Clock P4.0 - 14 ICAPA1 I Ext. Timer 1 - Input Capture A

Page 22

22/320

ST92F120 - GENERAL DESCRIPTION

P4.1

All ports useable for general purpose I/O (input, output or bidirectional)

- 15 I/O

P4.2 - 16 OCMPA1 O Ext. Timer1 - Output Compare A

P4.3 - 19

ICAPB1 I Ext. Timer1 - Input Capture B

OCMPB1 O Ext. Timer1 - Output Compare B

P4.4 9 20

EXTCLK1 I Ext. Timer 1 - Input Clock

WKUP4 I Wake-up Line 4

P4.5 10 21

EXTRG I A/D 0 and A/D 1 - Ext. Trigger

STOUT O Standard Timer Output P4.6 11 22 SDA I/O

CData

P4.7 12 23

WKUP1 I Wake-up Line 1

SCL I/O

C Clock

P5.0 1 6

WAIT I External Wait Request

WKUP5 I Wake-up Line 5

P5.1 2 7

WKUP6 I Wake-up Line 6

WDOUT O Watchdog Timer Output

P5.2 3 8

SIN0 I SCI0 - Serial Data Input

WKUP2 I Wake-up Line 2 P5.3 4 9 SOUT0 O SCI0 - Serial Data Output

P5.4 5 10

TXCLK0 I SCI0 - Transmit Clock Input

CLKOUT0 O SCI0 - Clock Output

P5.5 6 11

RXCLK0 I SCI0 - Receive Clock Input

WKUP7 I Wake-up Line 7

P5.6 7 12

DCD0 I SCI0 - Data Carrier Detect

WKUP8 I Wake-up Line 8

P5.7 8 13

WKUP9 I Wake-up Line 9

RTS0 O SCI0 - Request To Send

P6.0 43 67

INT0 I External Interrupt 0

INT1 I External Interrupt 1

CLOCK2/

O CLOCK2 divided by 8

P6.1 - 68

INT6 I External Interrupt 6

RW O Read/Write

P6.2 44 69

INT2 I External Interrupt 2

INT4 I External Interrupt 4

DS2 O Data Strobe 2

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

TQFP64 PQFP100

Page 23

23/320

ST92F120 - GENERAL DESCRIPTION

P6.3

All ports useable for general purpose I/O (input, output or bidirectional)

45 70

INT3 I External Interrupt 3

INT5 I External Interrupt 5 P6.4 46 71 NMI I Non Maskable Interrupt

P6.5 47 72

WKUP10 I Wake-up Line 10

VPWI I JBLPD input

INTCLK O Internal Main Clock P7.0 51 84 A0IN0 I A/D 0 - Analog Data Input0 P7.1 52 85 A0IN1 I A/D 0 - Analog Data Input1 P7.2 53 86 A0IN2 I A/D 0 - Analog Data Input2 P7.3 54 87 A0IN3 I A/D 0 - Analog Data Input3

P7.4 55 88

WKUP3 I Wake-up Line 3

A0IN4 I A/D 0 - Analog Data Input 4

P7.5 56 89

A0IN5 I A/D 0 - Analog Data Input 5

WKUP11 I Wake-up Line 11

P7.6 57 90

A0IN6 I A/D 0 - Analog Data Input 6

WKUP12 I Wake-up Line 12

P7.7 58 91

A0IN7 I A/D 0 - Analog Data Input 7

WKUP13 I Wake-up Line 13

P8.0 - 74

A1IN7 I A/D 1 - Analog Data Input 7

WKUP14 I Wake-up Line 14

P8.1 - 75

A1IN6 I A/D 1 - Analog Data Input 6

WKUP15 I Wake-up Line 15 P8.2 - 76 A1IN5 I A/D 1 - Analog Data Input 5 P8.3 - 77 A1IN4 I A/D 1 - Analog Data Input 4 P8.4 - 78 A1IN3 I A/D 1 - Analog Data Input 3 P8.5 - 79 A1IN2 I A/D 1 - Analog Data Input 2 P8.6 - 80 A1IN1 I A/D 1 - Analog Data Input 1 P8.7 - 81 A1IN0 I A/D 1 - Analog Data Input 0 P9.0 - 98 SIN1 I SCI1 - SerialData Input P9.1 - 99 SOUT1 O SCI1 - Serial Data Output

P9.2 - 100

TXCLK1 I SCI1 - Transmit Clock input

CLKOUT1 O SCI1 - Clock Input P9.3 - 1 RXCLK1 I SCI1 - Receive Clock Input P9.4 - 2 DCD1 I SCI1 - Data Carrier Detect P9.5 - 3 RTS1 O SCI1 - Request To Send P9.6 - 4 CLOCK2 O CLOCK2 internal signal P9.7 - 5 I/O

Port

Name

General

Purpose I/O

Pin No.

Alternate Functions

TQFP64 PQFP100

Page 24

24/320

ST92F120 - GENERAL DESCRIPTION

1.4 OPERATING MODES

To optimize the performance versus the power consumption of the device, the ST92F120 supports different operating modes that can be dynamically selected depending on the performance and functionality requirements of the application at a given moment.

RUN MODE: This is the full speed execution mode with CPU and peripherals running atthemaximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU).

SLOW MODE: Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and CCU Clock Divider.

WAIT FOR INTERRUPT MODE: The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequency depending on the CCU programming.

LOW POWER WAIT FOR INTERRUPT MODE: Combining SLOW mode and Wait For Interrupt mode it is possible to reduce the power consumption by more than 80%.

STOP MODE: When the STOP is requested by executing the STOP bit writing sequence (see dedicated section on Wake-up Management Unit paragraph), and if NMI is kept low, the CPU and the peripheralsstop operating. Operations resume

after a wake-up line is activated (16 wake-up lines plus NMI pin). See the RCCU and Wake-up Management Unit paragraphs in the following for the details. The difference with the HALT mode consists in the way the CPU exits this state: when the STOP is executed, the status of the registers is recorded, and when the system exits from the STOP mode the CPU continues the execution with the same status, without a system reset.

When the MCU enters STOP mode the Watchdog stops counting. After the MCU exits from STOP mode, the Watchdog resumes counting from where it left off.

When the MCU exits from STOP mode, the oscillator, which was sleeping too, requires about 5 ms to restart working properly (at a 4 MHz oscillator frequency). An internal counter is present to guarantee that all operations after exiting STOP Mode, take place with the clock stabilised.

The counter is active only when the oscillationhas already taken place. This means that 1-2 ms must be added to takeinto account the first phase of the oscillator restart.

HALT MODE: When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode.

Page 25

25/320

ST92F120 - DEVICE ARCHITECTURE

2 DEVICE ARCHITECTURE

2.1 CORE ARCHITECTURE

The ST9+ Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available.

Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and DMA controllersin the on-chip peripherals with the Core.

This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9+ family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources.

2.2 MEMORY SPACES

There are two separate memory spaces: – The Register File, which comprises 240 8-bit

registers, arranged as 15 groups (Group 0 to E), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in Group F,

which hold data and control bits for the on-chip peripherals and I/Os.

– A single linear memory space accommodating

both program and data. All of the physically separate memoryareas, including the internal ROM, internal RAM and external memory are mapped in this common address space. The total addressable memory space of 4 Mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further subdivided into four pages of 16 Kbytes, as illustrated in Figure 11.A Memory Management Unit uses aset of pointer registers to address a22-bit memory field using 16-bit address-based instructions.

2.2.1 Register File

The Register File consists of (see Figure 12): – 224 general purpose registers (Group 0 to D,

registers R0 to R223)

– 6 system registers in the System Group (Group

E, registers R224 to R239)

– Up to 64 pages, depending on device configura-

tion, each containing up to 16 registers, mapped to Group F (R240 to R255), see Figure 13.

Figure 11. Single Program and Data Memory Address Space

3FFFFFh

3F0000h 3EFFFFh

3E0000h

20FFFFh

02FFFFh 020000h

01FFFFh 010000h

00FFFFh 000000h

8 7 6

5 4 3 2 1 0

Address 16K Pages 64K Segments

up to 4 Mbytes

Data

Code

255 254 253 252 251

250 249 248 247

21FFFFh 210000h

133

134

135

Reserved

132

Page 26

26/320

ST92F120 - DEVICE ARCHITECTURE

MEMORY SPACES (Cont’d) Figure 12. Register Groups Figure 13. Page Pointer for Group F mapping

Figure 14. Addressing the Register File

F E D C B A

9 8 7 6 5 4 3

PAGED REGISTERS

SYSTEM REGISTERS

2 1 0

255 240

239 224 223

VA00432

UP TO

64 PAGES

GENERAL

REGISTERS

PURPOSE

224

PAGE 63

PAGE 5

PAGE 0

PAGE POINTER

R255

R240

R224

R0 VA00433

R234

REGISTERFILE

SYSTEM REGISTERS

GROUP D

GROUP B

GROUP C

(1100)

(0011)

R192

R207

255

240 239 224 223

F E

D C B A

9 8 7 6 5 4

3 2

1 0

VR000118

R195

(R0C3h)

PAGED REGISTERS

Page 27

27/320

ST92F120 - DEVICE ARCHITECTURE

MEMORY SPACES (Cont’d)

2.2.2 Register Addressing

Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 14). Group D registers can only be addressed in Working Register mode.

Note that an upper case “R” is used to denote this direct addressing mode.

Working Registers

Certain types of instruction require that registers be specified in the form “rx”, where x is in the range 0 to 15:these are known as Working Registers.

Note thata lower case “r” isusedto denote thisindirect addressing mode.

Two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups,each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 2.3.3 Register Pointing Techniques, and illustrated in Figure 15 and in Figure16.

System Registers

The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. These registers are described in greater detail in Section 2.3 SYSTEM REGISTERS.

Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These are addressed using any register addressing mode, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.

Therefore if the PagePointer, R234, is set to 5,the instructions:

spp #5 ld R242, r4

will load the contents of working register r4 into the third register of page 5 (R242).

These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9+ devices. The number of these registers therefore depends on the peripherals which are present in the specific ST9+ family device. In other words, pages only exist if the relevant peripheral is present.

Table 5. Register File Organization

Hex.

Address

Decimal

Address

Function

File Group

F0-FF 240-255

Paged

Registers

Group F

E0-EF 224-239

System

Registers

Group E

D0-DF 208-223

General

Purpose

Registers

Group D

C0-CF 192-207 Group C

B0-BF 176-191 Group B A0-AF 160-175 Group A

90-9F 144-159 Group 9 80-8F 128-143 Group 8 70-7F 112-127 Group 7 60-6F 96-111 Group 6 50-5F 80-95 Group 5 40-4F 64-79 Group 4 30-3F 48-63 Group 3 20-2F 32-47 Group 2 10-1F 16-31 Group 1 00-0F 00-15 Group 0

Page 28

28/320

ST92F120 - DEVICE ARCHITECTURE

2.3 SYSTEM REGISTERS

The System registers are listed in Table 6. They are used to perform all the important system settings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers.

Table 6. System Registers (Group E)

2.3.1 Central Interrupt Control Register

Please referto the ”INTERRUPT” chapter for a detailed description of the ST9 interrupt philosophy.

CENTRAL INTERRUPT CONTROL REGISTER (CICR)

R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h)

Bit 7 = GCEN:

Global Counter Enable

. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in theTCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timerswhenboth bits are set. This bit is set after the Reset cycle.

Note: Ifan MFT is not included in the ST9 device, then this bit has no effect.

Bit 6 = TLIP:

Top Level Interrupt Pending

. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending

Bit 5 = TLI:

Top Level Interrupt bit

0: Top Level Interrupt is acknowledged depending

on the TLNM bit in the NICR Register.

1: Top Level Interrupt is acknowledged depending

on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter).

Bit 4 = IEN:

Interrupt Enable .

This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the CICR register. 0: DisableallinterruptsexceptTop Level Interrupt. 1: Enable Interrupts

Bit 3 = IAM:

Interrupt Arbitration Mode

. This bit is set and clearedby software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode.

Bit 2:0 = CPL[2:0]:

Current Priority Level

. These three bits record the priority level of the routine currently running (i.e. the Current PriorityLevel, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are eitherleft pending or are allowed to interrupt the current interruptservice routine. When the current interrupt is replacedby one of a higher priority, the current priority value is automatically stored until required in the NICR register.

R239 (EFh) SSPLR R238 (EEh) SSPHR R237 (EDh) USPLR R236 (ECh) USPHR R235 (EBh) MODE REGISTER R234 (EAh) PAGE POINTER REGISTER R233 (E9h) REGISTER POINTER 1 R232 (E8h) REGISTER POINTER 0 R231 (E7h) FLAG REGISTER R230 (E6h) CENTRAL INT. CNTL REG R229 (E5h) PORT5 DATAREG. R228 (E4h) PORT4 DATAREG. R227 (E3h) PORT3 DATAREG. R226 (E2h) PORT2 DATAREG. R225 (E1h) PORT1 DATAREG. R224 (E0h) PORT0 DATAREG.

GCE

TLIP TLI IEN IAM CPL2 CPL1 CPL0

Page 29

29/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d)

2.3.2 Flag Register

The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the systemstack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status.

This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored.

FLAG REGISTER (FLAGR)

R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h)

Bit 7 = C:

Carry Flag

The carry flag is affected by:

Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws).

When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations).

The carry flag can be set by the Set Carry Flag (scf) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Complement Carry Flag (ccf) instruction.

Bit 6 = Z:

Zero Flag

. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec,

decw),

Test (tm, tmw, tcm, tcmw, btset). Inmostcases, theZeroflagissetwhenthecontents

of the register being used as an accumulator become zero, following one of the above operations.

Bit 5 = S:

Sign Flag

. The Sign flag is affected by the same instructions as the Zero flag.

The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one.

Bit 4 = V:

Overflow Flag

. The Overflow flag is affected by the same instructions as the Zero and Sign flags.

When set, the Overflow flag indicates that a two’scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two’s-complement notation.

Bit 3 = DA:

Decimal Adjust Flag

. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condition by the programmer.

Bit 2 = H:

Half Carry Flag.

The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCDdigits. The H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user.

Bit 1 = Reserved bit (must be 0).

Bit 0 = DP:

Data/Program Memory Flag

. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details.

C Z S V DA H - DP

Page 30

30/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d)

If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR).

Note: In the ST9+, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at the beginning of the program toensure a normal use of the different memory pointers.

2.3.3 Register Pointing Techniques

Two registers within the System register group, are usedas pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces.

For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointedto in twin 8-register mode, or to the lower 8-register block location in single 16-register mode.

The Set Register Pointer instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and

specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block.

There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16register mode.

The block number should always be an even number in single 16-register mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected.

Thus: srp #3 will be interpreted as srp #2 and will al-

low using R16 ..R31 as r0 .. r15. In single 16-register mode, the working registers

are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction).

Caution:

Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form “Rxxx”.

Page 31

31/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0)

R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)

Bit 7:3 = RG[4:0]:

These bits contain the number (in the range 0 to

31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped.

Bit 2 = RPS:

. This bit is set by the instructions srp0 andsrp1 to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode

Bit 1:0: Reserved. Forced by hardware to zero.

POINTER 1 REGISTER (RP1)

R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)

This register is only used in the twin register pointing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register.

Bit 7:3 = RG[4:0]:

These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped.

Bit 2 = RPS:

. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is selected. Thebit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode

Bit 1:0: Reserved. Forced by hardware to zero.

RG4 RG3 RG2 RG1 RG0 RPS 0 0

Page 32

32/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d) Figure 15. Pointing to a single group of 16

registers

Figure 16. Pointing to two groups of 8 registers

BLOCK

NUMBER

GROUP

FILE

POINTER 0

srp #2

set by:

instruction

points to:

GROUP 1

addressed by

BLOCK 2

r15

BLOCK

NUMBER

GROUP

FILE

POINTER 0

srp0 #2

set by:

instructions

point to:

GROUP 1

addressed by

BLOCK 2

POINTER 1

srp1 #7

GROUP 3

addressed by

BLOCK 7

r15

Page 33

33/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d)

2.3.4 Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9+ devices. The number of theseregisters depends on the peripherals present in the specific ST9 device. In other words, pagesonly exist ifthe relevant peripheral is present.

The paged registers are addressed using the normal register addressingmodes, inconjunctionwith the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession.

Thus the instructions:

spp #5 ld R242, r4

will load the contents of working register r4 into the third register of page 5 (R242).

Warning:

During an interrupt, the PPR registeris not saved automatically in the stack. If needed, it should be saved/restored by the user withinthe interrupt routine.

PAGE POINTER REGISTER (PPR)

R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh)

Bit 7:2 = PP[5:0]:

Page Pointer

These bits contain the number (in the range 0 to

63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is required.

Bit 1:0: Reserved. Forced by hardware to 0.

2.3.5 Mode Register

The Mode Register allows control of the following operating parameters:

– Selection ofinternalorexternal SystemandUser

Stack areas, – Management of the clock frequency, – Enabling of Bus request and Wait signals when

interfacing to external memory.

MODE REGISTER (MODER)

R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h)

Bit 7 = SSP:

System Stack Pointer

. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File

(reset state).

Bit 6 = USP:

User Stack Pointer

. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (re-

set state).

Bit 5 = DIV2:

OSCIN Clock Divided by 2

. This bit controls the divide-by-2 circuit operating on OSCIN. 0: Clock divided by 1 1: Clock divided by 2

Bit 4:2 = PRS[2:0]:

CPUCLK Prescaler

. These bits load the prescalerdivision factorfor the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information.

Bit 1 = BRQEN:

Bus Request Enable

. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on the

BREQ pin (where available).

Bit 0 = HIMP:

High Impedance Enable

. When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS,

PP5 PP4 PP3 PP2 PP1 PP0 0 0

SSP USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP

Page 34

34/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d)

DS, R/W) can be forced into the High Impedance state by setting the HIMP bit. When this bit is reset, it has no effect.

Setting the HIMP bit is recommended for noise reduction when only internal Memory is used.

If Port 1 and/or 2 are declared as an address AND as an I/O port (for example:P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines.

2.3.6 Stack Pointers

Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory.

The stack pointers point to the “bottom” of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is “pushed” in and post-incremented when data is “popped” out.

The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix “u”. To use a stack instruction for a word, thesuffix “w” is added. These suffixes may be combined.

When bytes (or words) are “popped” out from a stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when data is “popped” from a stackarea, the stack contents remain unchanged.

Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238

& R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value.

System Stack

The System Stack is used for the temporary storage of system and/or control data, such as the Flag register and the Program counter.

The following automatically push data onto the System Stack:

– Interrupts When entering an interrupt, the PC and the Flag

Code Segment Register is also pushed onto the System Stack.

– Subroutine Calls When a call instruction is executed, only the PC

is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack.

– Link Instruction The link or linku instructions create a C lan-

guage stack frame of user-defined length in the System or User Stack.

All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack.

User Stack

The User Stack provides a totally user-controlled stacking area.

The User Stack Pointer consists of two registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved.

Stack Pointers

Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as reserved and mustnot be used as ageneral purpose register.

The stack pointer registers are located in the System Group of the Register File, this is illustrated in Table 6.

Stack location

Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as astacking area.

Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks).

Note. Stacks must not be located in the Paged Register Group or in the System RegisterGroup.

Page 35

35/320

ST92F120 - DEVICE ARCHITECTURE

SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER

(USPHR)

R236 - Read/Write Register Group: E (System) Reset value: undefined

USER STACK POINTER LOW REGISTER (USPLR)

R237 - Read/Write Register Group: E (System) Reset value: undefined

Figure 17. InternalStack Mode

SYSTEM STACK POINTER HIGH REGISTER (SSPHR)

R238 - Read/Write Register Group: E (System) Reset value: undefined

SYSTEM STACK POINTER LOW REGISTER (SSPLR)

R239 - Read/Write Register Group: E (System) Reset value: undefined

Figure 18. External Stack Mode

USP15USP14USP13USP12USP11USP1

USP9 USP8

USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0

FILE

STACKPOINTER (LOW)

points to:

STACK

SSP15SSP14SSP13SSP12SSP11SSP1

SSP9 SSP8

SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0

FILE

STACK POINTER (LOW)

point to:

STACK

MEMORY

STACKPOINTER (HIGH)

Page 36

36/320

ST92F120 - DEVICE ARCHITECTURE

2.4 MEMORY ORGANIZATION

Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space.

The ST9+ provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdividedinto four 16 Kbyte pages.

The mapping of the variousmemory areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved).

Refer to the Register and Memory Map Chapter for more details on the memory map.

Page 37

37/320

ST92F120 - DEVICE ARCHITECTURE

2.5 MEMORY MANAGEMENT UNIT

The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used).

The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be

sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).

Figure 19. Page 21 Registers

DMASR ISR

EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0

R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240

FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h

MMU

Page 21

MMU

Bit DPRREM=0

SSPLR SSPHR USPLR USPHR

MODER

PPR

RP1 RP0

FLAGR

CICR P5DR P4DR P3DR P2DR P1DR P0DR

DMASR

ISR

EMR2 EMR1

CSR DPR3 DPR2

DPR0

Bit DPRREM=1

SSPLR

SSPHR

USPLR

USPHR

MODER

PPR RP1 RP0

FLAGR

CICR P5DR P4DR

P3DR P2DR P1DR P0DR

DMASR

ISR

EMR2 EMR1

CSR DPR3 DPR2 DPR1 DPR0

Relocation of P[3:0] and DPR[3:0] Registers

(default setting)

Page 38

38/320

ST92F120 - DEVICE ARCHITECTURE

2.6 ADDRESS SPACE EXTENSION

To manage 4 Mbytes of addressing space it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed.

2.6.1 Addressing 16-Kbyte Pages

This extension mode is implicitly used to address Data memoryspace if no DMA is being performed.

The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains 256 pages of 16 Kbytes.

Data pagingis performed byextending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted asthe identificationnumber of the DPR register to be used. Therefore, the DPR registers

are involved in the following virtual address ranges:

DPR0: from 0000h to 3FFFh; DPR1: from 4000h to 7FFFh; DPR2: from 8000h to BFFFh; DPR3: from C000h to FFFFh.

The contents of the selected DPR register specify one of the 256 possible data memory pages. This 8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical 22-bit address (see Figure 20).

A DPRregister cannot be modified via an addressing mode that uses the same DPRregister. For instance, the instruction “POPW DPR0” is legal only if the stack is kept either in the register file or in a memory location above 8000h, where DPR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the instruction, unpredictable behaviour could result.

Figure 20. Addressing via DPR[3:0]

DPR0 DPR1 DPR2 DPR3

01 10 11

16-bit virtual address

22-bit physical address

8 bits

MMU registers

14 LSB

Page 39

39/320

ST92F120 - DEVICE ARCHITECTURE

ADDRESS SPACE EXTENSION (Cont’d)

2.6.2 Addressing 64-Kbyte Segments

This extension mode is used to address Data memory space during a DMA and Program memory space during any code execution (normal code and interrupt routines).

Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 21).

2.7 MMU REGISTERS

The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register.

Most of these registers do not have a default value after reset.

2.7.1 DPR[3:0]: Data Page Registers

The DPR[3:0] registersallow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes.

2.7.1.1 Data Page Register Relocation

If these registers are to be used frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR’s locations: R240-243 page 21.

Data Page Register relocation is illustrated in Figure 19.

Figure 21. Addressing via CSR, ISR, and DMASR

Fetching program

Data Memory

Fetching interrupt

instruction

accessed in DMA

instruction or DMA access to Program

Memory

16-bit virtual address

22-bit physicaladdress

6 bits

MMU registers

CSR

ISR

DMASR

123

Page 40

40/320

ST92F120 - DEVICE ARCHITECTURE

MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0)

R240 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R224 if EMR2.5 is set.

Bit 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh.

DATA PAGE REGISTER 1 (DPR1)

R241 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R225 if EMR2.5 is set.

Bit 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh.

DATA PAGE REGISTER 2 (DPR2)

R242 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R226if EMR2.5 is set.

Bit 7:0 = DPR2_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh.

DATA PAGE REGISTER 3 (DPR3)

R243 - Read/Write Register Page: 21 Reset value: undefined

This register is relocated to R227if EMR2.5 is set.

Bit 7:0 = DPR3_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh.

DPR0_7DPR0_6DPR0_5DPR0_4DPR0_3DPR0_2DPR0_1DPR0

DPR1_7DPR1_6DPR1_5DPR1_4DPR1_3DPR1_2DPR1_1DPR1

DPR2_7DPR2_6DPR2_5DPR2_4DPR2_3DPR2_2DPR2_1DPR2

DPR3_7DPR3_6DPR3_5DPR3_4DPR3_3DPR3_2DPR3_1DPR3

Page 41

41/320

ST92F120 - DEVICE ARCHITECTURE

MMU REGISTERS (Cont’d)

2.7.2 CSR: Code Segment Register

This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segmentsof 64 Kbytes.

To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs.

Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets instruction.

CODE SEGMENT REGISTER (CSR)

R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h)

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16).

2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR)

R248 - Read/Write Register Page: 21 Reset value: undefined

ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details.

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = ISR_[5:0]: These bits define the 64-Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits(A21-16). The ISR is used to extend the address space in two cases:

– Whenever an interrupt occurs: ISR points to the

64-Kbyte memory segment containing the interrupt vectortable andthe interrupt service routine code. See also the Interrupts chapter.

– DuringDMA transactions betweenthe peripheral

and memory whenthe PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction.

2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGISTER (DMASR)

R249 - Read/Write Register Page: 21 Reset value: undefined

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral’s data register and Memory, withthe PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the address.

CSR_5CSR_4CSR_3CSR_2CSR_1CSR_

0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0

DMA

SR_5

DMA

SR_4

DMA

SR_3

DMA

SR_2

DMA

SR_1

DMA

SR_0

Page 42

42/320

ST92F120 - DEVICE ARCHITECTURE

MMU REGISTERS (Cont’d) Figure 22. Memory Addressing Scheme (example)

3FFFFFh

294000h

240000h 23FFFFh

20C000h

200000h

1FFFFFh

040000h 03FFFFh

030000h 020000h

010000h

00C000h

000000h

DMASR

ISR

CSR

DPR3

DPR2

DPR1

DPR0

4M bytes

16K

16K 16K

64K

16K

Page 43

43/320

ST92F120 - DEVICE ARCHITECTURE

2.8 MMU USAGE

2.8.1 Normal Program Execution

Program memory is organized as a set of 64Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from another. Writing tothe CSR is allowed when it is not being used, i.e during an interrupt service routine if ENCSR is reset.

Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means thatifthe routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used.

In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR[3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc.

If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 0-

3. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused.

2.8.2 Interrupts

The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call.

When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21).

If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is

used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes.

If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vectortable and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, becausethe interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs.

Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion.

2.8.3 DMA

Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created.Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).

Page 44

44/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3 SINGLE VOLTAGE FLASH & EEPROM

3.1 INTRODUCTION

The Flash circuitry contains one array divided in two main parts that can each be read independently. The first part contains the main Flash array for code storage, a reserved array (TestFlash) for system routines and a 128-byte area available as one time programmable memory (OTP). The second part contains the two dedicated Flash sectors used for EEPROM Hardware Emulation.

The write operationsof the two parts are managed by an embedded Program/Erase Controller, that uses a dedicated ROM (256 words of 12 bits each). Through a dedicated RAM buffer the Flash and the EEPROM can be written in blocks of 16 bytes.

Figure 23. Flash Memory structure (Example for 128K Flash device)

230000h

000000h

010000h

01C000h 01E000h

228000h

22C000h

Sector F0

64 Kbytes

Sector F1

48 Kbytes

Sector F2

8 Kbytes

Sector F3

8 Kbytes

Sector F4/E0

4 Kbytes

Sector F5/E1

4 Kbytes

TestFlash

8 Kbytes

Program / Erase

Controller

RAM buffer 16 bytes

Interface

Address Data

231F80h

User OTP and Protection registers

8 sense +

8 program load

8 sense +

8 program load

Page 45

45/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.2 FUNCTIONAL DESCRIPTION

3.2.1 Structure

The Flash memory is composed of three parts (see following table):

– 1 reservedsectorforsystemroutines(TestFlash

including user OTP area) – 4 main sectors for code – 2 sectors of the same size for EEPROM emula-

tion The last 128 bytes of the TestFlash are available

to the user as an OTP area. The user can program these bytes, but cannot erase them. The last 4 bytes of this OTP area (231FFCh to 231FFFh for 128K Flash device and 230FFCh to 230FFFh for 60K/36K Flash devices) are reserved for the NonVolatile Protection registers and cannot be used as a storage area (see Section 3.6 PROTECTION STRATEGY for more details).

3.2.2 Software or Hardware EEPROM Emulation (Device dependent option)

The MCU can be factory-configured to allow the user to manage the EEPROM emulation by software (using for example the Intel algorithm), by directly addressing the two dedicated sectors F4 and F5. In this case the Hardware EEPROM emulation will not be available.

Hardware EEPROM emulation

By default, a hardware EEPROM emulation is implemented using special flash sectors F4/E0 and F5/E1 to emulate an EEPROM memory whose size is 1/4 of a sector (1 Kbytes max). This EEPROM can be directly addressed from 220000h to 2203FFh for 128K Flash device and 220000h to 2201FFh for 60K/36K Flash devices.

In this case, Flash sectors F4 and F5 are not directly accessible.

(see Section 3.5.1 Hardware EEPROM Emulation for more details).

Table 7. Memory Structure for 128K Flash device

Table 8. Memory Structure for 60K Flash device

Sector Addresses Max Size

TestFlash (TF) (Reserved) 230000h to 231F7Fh 8064 bytes

User OTP Area 231F80h to 231FFFh 128 bytes

Flash 0 (F0) 000000h to 00FFFFh 64 Kbytes Flash 1 (F1) 010000h to 01BFFFh 48 Kbytes Flash 2 (F2) 01C000h to 01DFFFh 8 Kbytes

Flash 3 (F3) 01E000h to 01FFFFh 8 Kbytes Flash 4 / EEPROM 0 (F4/E0) 228000h to 228FFFh 4 Kbytes Flash 5 / EEPROM 1 (F5/E1) 22C000h to 22CFFFh 4 Kbytes

Emulated EEPROM 220000h to 2203FFh 1 Kbyte

Sector Addresses Max Size

TestFlash (TF) (Reserved) 230000h to 230F7Fh 3968 bytes

User OTP Area 230F80h to 230FFFh 128 bytes

Flash 0 (F0) 000000h to 000FFFh 4 Kbytes

Flash 1 (F1) 010000h to 017FFFh 32 Kbytes

Flash 2 (F2) 018000h to 01BFFFh 16 Kbytes

Flash 3 (F3) 01C000h to 01DFFFh 8 Kbytes Flash 4 / EEPROM 0 (F4/E0) 228000h to 2287FFh 2 Kbytes Flash 5 / EEPROM 1 (F5/E1) 22C000h to 22C7FFh 2 Kbytes

Emulated EEPROM 220000h to 2201FFh 512 bytes

Page 46

46/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

FUNCTIONAL DESCRIPTION (Cont’d) Table 9. Memory Structure for 36K Flash device

3.2.3 Operation

The memory has a register interface mapped in memory space (segment 22h). All operations are enabled through the FCR (Flash Control Register) ECR (EEPROM Control Register).

All operations on theFlash must be executed from another memory (internal RAM, EEPROM, external memory).

Flash (including TestFlash) and EEPROM have duplicated sense amplifiers, so that one can be read whilethe other is written. However simultaneous Flash and EEPROM write operations are forbidden.

An interrupt can be generated at the end of a Flash or an EEPROM write operation: this interrupt is multiplexed with an external interrupt EXTINTx (device dependent) to generate an interrupt INTx.

The status of a write operation inside the Flash and the EEPROM memories can be monitored through the FESR[1:0] registers.

Control and Status registers are mapped in memory (segment 22h), as shown in the following figure.

Figure 24. Control and Status Register Map.

During awrite operation, if the power supply drops or the RESET pin is activated, the write operation is immediately interrupted. In this case the user must repeat the last write operation following power on or reset.

Sector Addresses Max Size

TestFlash (TF) (Reserved) 230000h to 230F7Fh 3968 bytes

User OTP Area 231F80h to 230FFFh 128 bytes

Flash 0 (F0) 000000h to 000FFFh 4 Kbytes

Flash 1 (F1) 010000h to 013FFFh 16 Kbytes

Flash 2 (F2) 014000h to 015FFFh 8 Kbytes

Flash 3 (F3) 016000h to 017FFFh 8 Kbytes Flash 4 / EEPROM 0 (F4/E0) 228000h to 2287FFh 2 Kbytes Flash 5 / EEPROM 1 (F5/E1) 22C000h to 22C7FFh 2 Kbytes

Emulated EEPROM 220000h to 2201FFh 512 bytes

224000h 224001h

224002h

FCR ECR

FESR0 FESR1224003h

Page 47

47/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.3 REGISTER DESCRIPTION

3.3.1 Control Registers FLASH CONTROL REGISTER (FCR)

Address: 224000h - Read/Write Reset value: 0000 0000 (00h)

The Flash Control Register is used to enable all the operations for the Flash and the TestFlash memories, but also for the two dedicated EEPROM sectors F4/E0 and F5/E1 if they are addressed directly when using software EEPROM emulation (the FCR register must be used in this case only to select operations, while the ECR register must still be used to start the operation with the EWMS bit). The write access to the TestFlash is possible only in test mode, except the OTP area of the TestFlash that can be programmed in user mode (but not erased).

Bit 7 = FWMS:

Flash Write Mode Start (Read/

Write).

This bit must be set to start every write/erase operation in Flash memory. At the end of the write/ erase operation or during a Sector Erase Suspend this bit is automatically reset. To resume a suspended Sector Erase operation, this bit must be set again. Resetting this bit by software does not stop the current write operation. 0: No effect 1: Start Flash write

Bit 6 =FPAGE:

Flash Pageprogram (Read/Write)

. This bit must be set to select the Page Program operation in Flash memory. The Page Program operation allows to program “0”s in place of “1”s. From 1 to 16 bytes can be entered (in any order, no need for an ordered address sequence) before starting the execution by setting the FWMS bit. All the addresses must belong tothe same page (only the 4 LSBs of address can change). Data to be programmed and addresses in which to program must be provided (through an LD instruction, for example). Data contained in page addresses that are not entered are left unchanged. This bit is automatically reset at the end of the Page Program operation. 0: Deselect page program 1: Select page program

Bit 5 = FCHIP:

Flash CHIP erase (Read/Write).

This bit must be set to select the Chip Erase operation in Flash memory. The Chip Erase operation allows to erase all the Flash locations to FFh. The operation is limited to Flash code (sectors F0-F3; TestFlash and EEPROM sectors excluded). The execution starts by setting the FWMS bit. It is not necessary to pre-program the sectors to 00h, because this is done automatically. This bit is automatically reset at the end of the Chip Erase operation. 0: Deselect chip erase 1: Select chip erase

Bit 4 = FBYTE:

Flash byte program (Read/Write).

This bit must be set to select the Byte Program operation in Flash memory. The Byte Program operation allows “0”s to be programmedin place of “1”s. Data to be programmed and an address in which to program must be provided (through an LD instruction, for example) before starting execution by setting bit FWMS. This bit is automatically reset at the end of the Byte Program operation. 0: Deselect byte program 1: Select byte program

Bit 3 = FSECT:

Flash sector erase (Read/Write).

This bit must be set to select the Sector Erase operation in Flash memory. The Sector Erase operation erases all the Flash locations to FFh. From 1 to 4 sectors (F0, ..,F3) can be simultaneously erased, while TF, F4, F5 must be individually erased. Sectors to be simultaneously erased can be entered before starting the execution by setting the FWMS bit. An address located in the sector to erase must be provided (through an LD instruction, for example), while the data to be provided is don’t care. It is not necessary to pre-program the sectors to 00h, because this is done automatically. This bit is automatically reset at the end of the Sector Erase operation. 0: Deselect sector erase 1: Select sector erase

Bit 2 = FSUSP:

Flash sector erase suspend

(Read/Write)

. This bit mustbe set to suspend the current Sector Erase operation in Flash memory in order to read data to or from program data to a sector not being erased. The Erase Suspend operation resets the Flash memory to normal read mode (automatically resetting bit FBUSY) in a maximumtime of 15µs.

76543210

FWMSFPAGEFCHIPFBYTEFSECTFSUS

PROT

FBUS

Page 48

48/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

When in Erase Suspend the memory accepts only the following operations: Read, Erase Resume and Byte Program. Updating the EEPROM memory is not possible during a Flash Erase Suspend.

The FSUSP bit must be reset (and FWMS must be set again) to resume a suspended Sector Erase operation. 0: Resume sector erase when FWMS is set again. 1: Suspend Sector erase

Bit 1 = PROT:

Set Protection (Read/Write).

This bit must be set to select the Set Protection operation. TheSetProtection operation allows“0”s in place of “1”s to be programmed in the four Non Volatile Protection registers. From 1 to 4 bytes can be entered (in any order, no need for an ordered address sequence) before starting the execution by setting the FWMS bit . Data to be programmed and addresses in which to program must be provided (through an LD instruction, for example). Protection contained in addresses that are not entered are left unchanged. This bit is automatically reset at the end of the Set Protection operation. 0: Deselect protection 1: Select protection

Bit 0 = FBUSY:

Flash Busy (Read Only).

This bit is automatically set during Page Program, Byte Program, Sector Erase or Set Protection operations when the first address to be modified is latched inFlash memory, or during Chip Erase operation when bit FWMS is set. When this bit is set every read access to the Flash memory will output invalid data (FFh equivalent to a NOP instruction), while every write access to the Flash memory will be ignored. At the end of the write operations or during a Sector Erase Suspend this bit is automatically reset and thememory returns to read mode. After an Erase Resume this bit is automatically set again. If the twoEEPROM sectors E0 and E1 are used instead of the embedded hardware emulation, FBUSY remains low during a modification in those sectors(whileEBUSY rises), so that reading in Flashmemory remainspossible. The FBUSY bit remains high for a maximum of 10µs after PowerUp and when exiting Power-Down mode, meaning that the Flash memory is not yet ready to be accessed. 0: Flash not busy 1: Flash busy

EEPROM CONTROL REGISTER (ECR)

Address: 224001h - Read/Write Reset value: 000x x000 (xxh)

The EEPROM Control Register is used to enable all the operations for the EEPROM memory in devices with EEPROM hardware emulation.

The ECR also contains two bits (WFIS and FEIEN) that are related to both Flash and EEPROM memories.

Bit 7 = EWMS:

EEPROM Write Mode Start

. This bit must be set to start every write/erase operation in the EEPROM memory. At the end of the write/erase operation this bit is automatically reset. Resetting by software this bit does not stop the current write operation. 0: No effect 1: Start EEPROM write

Bit 6 = EPAGE:

EEPROM page update.

This bit must be set to select the Page Update operation in EEPROM memory. The Page Update operation allows to write a new content: both “0”s in place of “1”s and “1”s in place of “0”s. From 1 to 16 bytes can be entered (in any order, no need for an ordered address sequence) before starting the execution by setting bit EWMS. All the addresses must belong to the same page (only the 4 LSBs of address can change). Data tobe programmed and addresses in which to program must be provided (through an LD instruction, for example). Data contained in page addresses that are not entered are left unchanged. This bit is automatically reset at the end of the Page Update operation. 0: Deselect page update 1: Select page update

Bit 5 = ECHIP:

EEPROM chip erase.

This bit must be set to select the Chip Erase operation in the EEPROM memory. The Chip Erase operation allows to erase all the EEPROM locations to (E0 and E1 sectors) FFh. The execution starts by setting bit EWMS. This bit is automatically reset at the end of the Chip Erase operation. 0: Deselect chip erase 1: Select chip erase

Bit 4:3 = Reserved.

76543210

EWMSEPAGEECHI

WFIS

FEIENEBUS

Page 49

49/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

Bit 2 = WFIS:

Wait For Interrupt Status.

If this bit is reset, the WFI instruction puts the Flash macrocell in Stand-by mode (immediate read possible, but higher consumption: 100 µA); if it is set, the WFI instruction puts theFlash macrocell in Power-Down mode (recovery time of 10µs needed before reading, but lower consumption: 10µA). The Stand-by mode or the Power-Down mode will be entered only at the end of any current Flash or EEPROM write operation.

In the same way following an HALT or a STOP instruction, the Memory enters Power-Down mode only after the completion of any current write operation. 0: Flash in Standby mode on WFI 1: Flash in Power-Down mode on WFI

Note: HALT or STOP mode can be exited without problems, but the user should take care when exiting WFI Power Down mode. If WFIS is set, the user code must reset the XT_DIV16 bit in the R242 register (page 55) before executing the WFI instruction. When exiting WFI mode, this gives the Flash enough time to wake up before the interrupt vector fetch.

Bit 1 = FEIEN:

Flash & EEPROM Interruptenable

. This bit selects the source of interrupt channel INTx between the external interrupt pin and the Flash/EEPROM End of Write interrupt. Refer to the Interrupt chapter for the channel number. 0: External interrupt enabled 1: Flash & EEPROM Interrupt enabled

Bit 0 = EBUSY:

EEPROM Busy(Read Only).

This bit is automatically set during a Page Update operation when the first address to be modified is latched in the EEPROM memory, or during Chip Erase operation when bit EWMS is set. At the end of the write operation or during a Sector Erase Suspend this bit is automatically reset and the memory returns to read mode. When this bit is set every read access to the EEPROM memory will output invalid data (FFh equivalent to a NOP instruction), while every write access to the EEPROM memory will be ignored. At the end of the write operation this bit is automatically reset and the memory returns to read mode. EBUSY rises also if a write operation is started in one of the two EEPROM sectors, used as Flash sectors. Bit EBUSY remains high fora maximum of 10ms after Power-Up and when exiting Power-Down mode, meaning that the EEPROM memory is not yet ready to be accessed. 0: EEPROM not busy 1: EEPROM busy

Page 50

50/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.3.2 Status Registers

During aFlash or an EEPROM write operation any attempt toreadthememoryunder modification will output invalid data (FFh equivalent to a NOP instruction). This means that the Flash memory is not fetchable when a write operation is active: the write operation commands must be givenfrom another memory (EEPROM, internal RAM, or external memory).

Two Status Registers (FESR[1:0] are available to check the status of the current write operation in Flash and EEPROM memories.

FLASH & EEPROM STATUS REGISTER 0 (FESR0)

Address: 224002h -Read/Write Reset value: 0000 0000 (00h)

Bit 7 = FEERR:

Flash or EEPROM write ERRor

(Read/Write).

This bit is set by hardware when an error occurs during a Flash or an EEPROM write operation. It must be cleared by software. 0: Write OK 1: Flash orEEPROM write error

Bit 6:0 = FESS[6:0].

Flash and EEPROM Status

Sector 6-0 (Read Only).

These bits are set by hardware and give the status of the 7 Flash and EEPROM sectors (TF, F5, F4, F3, F2,F1,F0).The meaning of FESSx bit for sector x is given by the following table:

FLASH & EEPROM STATUS REGISTER 1 (FESR1)

Address: 224003h -Read Only Reset value: 0000 0000 (00h)

Bit 7 = ERER.

Erase error (Read Only).

This bit isset by hardware whenan Erase error occurs during a Flash or an EEPROM write operation. This error is due to a real failure of a Flash cell, that can not be erased anymore. This kind of error is fatal and the sector where it occurred must be discarded (if it was in one of the EEPROM sectors, the hardware emulation can not be used anymore). This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by software. 0: Erase OK 1: Erase error

Bit 6 = PGER.

Program error (Read Only).

This bit is automatically set when a Program error occurs during a Flash oran EEPROM write operation. This error is due to a real failure of a Flash cell, that can not be programmed anymore. The byte where this error occurred must be discarded (if it was in the EEPROM memory, the byte must be reprogrammed to FFh and then discarded, to avoid the error occurring again when that byte is internally moved). This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by software. 0: Program OK 1: Flash or EEPROM Programming error

76543210

FEERRFESS6FESS5FESS4FESS3FESS2FESS1FESS

Table 10. FESSx bit Values

FEERR

FBUSY EBUSY

FSUSP

FESSx=1

meaning

1--

Write Error in

Sector x

01-

Write operation

on-going in sec-

tor x

001

Sector Erase

Suspended in

sector x

0 0 0 Don’t care

76543210

ERER PGER

SWE

Table 10. FESSx bit Values

FEERR

FBUSY

EBUSY

FSUSP

FESSx=1

meaning

Page 51

51/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

Bit 5 = SWER.

Swap or 1 over 0 Error (Read On-

ly).

This bit has two different meanings, depending on whether the current write operation is to Flash or EEPROM memory.

In Flash memory this bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the Protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written.

In the EEPROM memory this bit is automatically set when a Program error occurs during the swapping of the unselected pages to the new sector when the old sector is full (see Section 3.5.1 Hardware EEPROM Emulation for more details).

This error is due to a real failure of a Flash cell, that can not be programmed anymore. When this error is detected, the embedded algorithm automatically exits the Page Update operation at the end of the Swap phase, without performing the Erase Phase 0 on the full sector. In this way the old data are kept, and through predefined routines in TestFlash (Find Wrong Pages = 230029h and Find Wrong Bytes = 23002Ch), the user can compare theold and the new data to find where the error occurred.

Once the error has been discovered the user must take to end the stopped Erase Phase0 on the old sector (through another predefined routine in TestFlash: Complete Swap = 23002Fh). The byte where the error occurred must be reprogrammed to FFh and then discarded, to avoid the error occurring again when that byte is internally moved.

This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by software.

Bit 4:0 = Reserved.

Page 52

52/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.4 WRITE OPERATION EXAMPLE

Each operation (both Flash and EEPROM) is activated bya sequence of instructions like the following:

OR CR, #OPMASK ;Operation selection LD ADD1, #DATA1 ;1st Add and Data LD ADD2, #DATA2 ;2nd Add and Data

.. ...., ......

LD ADDn, #DATAn ;nth Add and Data

;n range = (1 to 16)

OR CR, #80h ;Operation start

The first instruction is used to select the desired operation by setting its corresponding selection bit in the Control Register (FCR for Flash operations, ECR for EEPROM operations).

The load instructions are used to set the addresses (in the Flash or in the EEPROM memory space) and the data to be modified.

The last instruction is used to start the write operation, by setting the start bit (FWMS for Flash operations, EWMS for EEPROM operation) in the Control register.

Once selected, but not yet started, one operation can be cancelledby resetting the operation selection bit. Any latched address and data willbe reset.

Warning: during the Flash Page Program or the EEPROM Page Update operation it is forbidden to change the page address: only the last page address is effectively kept and all programming will effect only that page.

A summary of the available Flash and EEPROM write operations (including the Flash Write Operations on the EEPROM sectors when the EEPROM Hardware Emulation is not used) are shown in the following tables:

Table 11. Flash Write Operations

Table 12. EEPROM Write Operations

Operation Selection bit Addresses and Data Start bit Typical Duration

Byte Program FBYTE 1 byte FWMS 10 µs

Page Program FPAGE From 1 to 16 bytes FWMS 160 µs (16 bytes)

Sector Erase FSECT From 1 to 4 sectors FWMS 1.5 s (1 sector)

Sector Erase Suspend FSUSP None None 15 µs

Chip Erase FCHIP None FWMS 3 s

Set Protection PROT From 1 to 4 bytes FWMS 40 µs (4 bytes)

Operation Selection bit Addresses and Data Start bit Typical Duration

Page Update EPAGE From 1 to 16 bytes EWMS 30 ms

Chip Erase ECHIP None EWMS 70 ms

Table 13. Flash Write Operations on EEPROM sectors

Operation Selection bit Addresses and Data Start bit Typical Duration

Byte Program FBYTE 1 byte EWMS 10 µs

Page Program FPAGE From 1 to 16 bytes EWMS 160 µs (16 bytes)

Sector Erase FSECT 1 sector EWMS 70 ms

Sector Erase Suspend FSUSP None None 15 µs

Page 53

53/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.5 EEPROM

3.5.1 Hardware EEPROM Emulation Note: This section provides general information

only. Users do not have to be concerned with the hardware EEPROM emulation.

The last 256 bytes of the two EEPROM dedicated sectors (229000h to 2290FFh for sector E0 and 22D000h to 22D0FFh for sector E1) are reserved for the Non Volatile pointers usedfor the hardware Emulation.

When the EEPROM is directly addressed through the addresses 220000h to 2203FFh, a Hardware Emulation mechanism is automatically activated, so avoiding the user having to manage the Non Volatile pointers that are used to map the EEP-

ROM inside the two dedicated Flash sectors E0 and E1.

The structure of the hardware emulation is shown in Figure 25.

Each one of the two EEPROM dedicated Flash sectors E0 and E1 is divided in 4 blocks of the same size of the EEPROM to emulate (1Kbyte max).

Each one of the 4 blocks is then divided inup to 64 pages of 16 bytes, the size of the available RAM buffer.

The RAM buffer is used internally to temporarily store the new content of the page to update, during the Page Program operation (both in Flash and in EEPROM).

Figure 25. Segment 22h structure (Example for 128K Flash device).

229000h

220000h

2203FFh

Page buffer - 16 byte

64 pages

Flash/EEPROM sector F4/E0 Flash/EEPROM sector F5/E1

RAM buffer

HW emulated EEPROM

1 Kbyte

FCR, ECR, FESR1-0 - 4 byte224000h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

228000h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

228400h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

228800h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

228C00h

Non VolatileStatus

256 byte

22D000h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

22C000h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

22C400h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

22C800h

Page 63 - 16 byte

Page 0 - 16 byte Page 1 - 16 byte

Page 62 - 16 byte

Page 2 to 61

22CC00h

Non VolatileStatus

256 byte

User Registers

Block 0

1 Kbyte

Block 1

1 Kbyte

Block 2

1 Kbyte

Block 3

1 Kbyte

Block 0

1 Kbyte

Block 1

1 Kbyte

Block 2

1 Kbyte

Block 3

1 Kbyte

Page 54

54/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

EEPROM (Cont’d)

3.5.2 EEPROM Update Operation

The update of the EEPROM content can be made by pages of 16 consecutive bytes. The Page Update operation allows up to 16 bytes to be loaded into the RAM buffer that replace the ones already contained in the specified address.

Each time a Page Update operation is executed in the EEPROM, the RAM buffer content is programmed in the next free block relative to the specified page (the RAM buffer is previously automatically filled with old data for all the page addresses not selected for updating). If all the 4 blocks of the specified page in the current EEPROM sector are full, the page content is copied to the complementary sector, that becomes the new current one.

After that the specified page has been copied to the next free block, one erase phase is executed

on the complementary sector, if the 4 erase phases have not yet been executed.When theselected page is copied to the complementary sector, the remaining 63 pages are also copied to the first block of the new sector; then the first erase phase is executed on the previous full sector. All this is executed in a hidden manner, and the End Page Update Interrupt is generated only after the end of the complete operation.

At Reset the two status pages are read in order to detect which is the sector that is currently mapping the EEPROM, and in which block each page is mapped. A system defined routine written in TestFlash is executed at reset, so that any previously aborted write operation is restarted and completed.

Figure 26. Hardware Emulation Flow

Emulation Flow

Reset

Read Status Pages

Map EEPROM

in current sector

Write operation

to complete ?

Complete

Write operation

Update

Status page

Yes

Wait for

Update commands

Page

Update

Command

End Page Update Interrupt (to Core)

Program selected

Page from RAM buffer

in next freeblock

Copy all other Pages

into RAM buffer; then program them in next free block

1/4 erase of

complementary sector

Update

Status Page

new

sector ?

Yes

Complementary

sector erased ?

Yes

Page 55

55/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.6 PROTECTION STRATEGY

The protection bits are stored in the last 4 locations of the TestFlash (from 231FFCh) (see Figure

27). All the available protections are forced active dur-

ing reset, then in the initialisation phase they are read from the TestFlash.

The protections are stored in 2 Non Volatile Registers. Other 2 Non Volatile Registers can be used as a password to re-enable test modes once they have been disabled.

The protections can be programmed using the Set Protection operation (see Control Registers paragraph), that can be executed from all the internal or external memories except the Flash or TestFlash itself.

Figure 27. Protection Map.

3.6.1 Non Volatile Registers

The 4 Non Volatile Registersused to storetheprotection bits for the different protection features are one time programmable by the user, but they are erasable in test mode (if not disabled).

Access to these registers is controlled by the protections related to the TestFlash where they are mapped. Since the code to program the Protection Registers cannot be fetched by the Flash or the TestFlash memories, this means that, once the APRO or APBR bits in the NVAPR register are programmed, it is no longer possible to modify any of the protection bits. For this reason the NV Password, if needed, must be set with the same Set Protection operation used to program these bits. For thesame reason it is strongly advised to never program the WPBR bit in the NVWPR register, as this will prevent any further write access to the TestFlash, and consequently to the Protection Registers.

NON VOLATILE ACCESS PROTECTION REGISTER (NVAPR)

Address: 231FFCh - Read/Write Delivery value: 1111 1111 (FFh)

Bit 7 = Reserved.

Bit 6 = APRO:

ROM access protection.

This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the Flash address space (EEPROM excluded), unless the current instruction is fetched from the TestFlash or from the Flash itself. 0: ROM protection on 1: ROM protection off

Bit 5 = APBR:

BootROM access protection.

This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the TestFlash address space, unless the current instruction is fetched from the TestFlash itself. 0: BootROM protection on 1: BootROM protection off

Bit 4 = APEE:

EEPROM access protection.

This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the EEPROM address space, unless the current instruction is fetched from the TestFlash or from the Flash, or from the EEPROM itself. 0: EEPROM protection on 1: EEPROM protection off

Bit 3 = APEX:

Access Protection from External

memory.

This bit, if programmed at 0, disables any access (read/write) to operands mapped inside the address space of one ofthe internalmemories (TestFlash, Flash, EEPROM, RAM), if the current instruction is fetched from an external memory. 0: Protection from external memory on 1: Protection from external memory off

NVAPR

NVWPR

231FFCh 231FFDh

Protection

231FFEh NVPWD0

NVPWD1231FFFh

76543210

1 APRO APBR APEE APEX PWT2 PWT1 PWT0

Page 56

56/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

PROTECTION STRATEGY (Cont’d)

Bit 2:0 = PWT[2:0]:

Password Attempt 2-0.

If the TMDIS bit in the NVWPR register (231FFDh) is programmed to 0, every time a Set Protection operation is executed with Program Addresses equal to NVPWD1-0 (231FFE-Fh), the two provided Program Data are compared with the NVPWD1-0 content; if there is not a match one of PWT2-0 bits is automatically programmed to 0: when these three bits are all programmed to 0 the test modes are disabled forever. In order to intentionally disable test modes forever, it is sufficient to set a random Password and then to make 3 wrong attempts to enter it.

NON VOLATILE WRITEPROTECTION REGISTER (NVWPR)

Address: 231FFDh - Read/Write Delivery value: 1111 1111 (FFh)

Bit 7 = TMDIS:

Test mode disable (Read Only).

This bit, if set to 1, allows to bypass all the protections intest mode. If programmed to 0, on the contrary, all the protections remain active also in test mode. The only way to enable the test modes if this bit is programmed to 0, is to execute the Set Protection operation with Program Addresses equal to NVPWD1-0 (231FFF-Eh) and Program Data matching with the content of NVPWD1-0. This bit is read only: it is automatically programmed to 0 when NVPWD1-0 are written. 0: Test mode disabled 1: Test mode enabled

Bit 6 = PWOK:

Password OK (Read Only).

If the TMDIS bit is programmed to 0, when the Set Protection operation is executed with Program Addresses equal to NVPWD[1:0] and Program Data matching with NVPWD[1:0] content, the PWOK bit is automatically programmed to 0. When this bit is programmed to 0 TMDIS protection is bypassed and the test modes are enabled. 0: Password OK 1: Password not OK

Bit 5 = WPBR:

BootROM Write Protection

. This bit, if programmed at 0, disables any write access to the TestFlash address space. This protection cannot be temporarily disabled. 0: BootROM write protection on 1: BootROM write protection off

Bit 4 = WPEE:

EEPROM Write Protection

. This bit, if programmed to 0, disables any write access to the EEPROM address space. This protection can be temporary disabled by executing the Set Protection operation and writing 1 into this bit. To restore the protection it needs to reset the micro or to execute another Set Protection operation and write 0 to this bit. 0: EEPROM write protection on 1: EEPROM write protection off

Bit 3:0 = WPRS[3:0]:

ROM Segments 3-0 Write

Protection.

These bits, if programmed to 0, disable any write access to the 4 Flash sectors address spaces. These protections can be temporary disabled by executing the Set Protection operation and writing 1 into these bits.To restore the protection it needs to reset the micro or to execute another Set Protection operation and write 0 into these bits. 0: ROM Segments 3-0 write protection on 1: ROM Segments 3-0 write protection off

NON VOLATILE PASSWORD (NVPWD1-0)

Address: 231FFF-231FFEh - Write Only Delivery value: 1111 1111 (FFh)

Bit 7:0 = PWD[7:0]:

Password bits 7:0 (Write On-

ly).

These bits must be programmed with the Non Volatile Password that must be provided with the Set Protection operation to reenable the test modes. These two registers can be accessed only in write mode and only once; when theyarewritten (simultaneously with the same Set Protection operation), bit TMDIS of NVWPR (231FFDh) is simultaneously programmed and test modes are disabled.

76543210

TMDISPWOKWPBRWPEEWPRS3WPRS2WPRS1WPRS

76543210

PWD7PWD6PWD5PWD4PWD3PWD2PWD1PWD

Page 57

57/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.6.2 Temporary Unprotection

On user request the memory can beconfigured so as to allow the temporary unprotection also of all access protections bits of NVAPR (write protection bits of NVWPR are always temporarily unprotectable).

Bit APEX can be temporarily disabled by executing the Set Protection operation and writing 1 into this bit, but only if this write instruction is executed from aninternal memory (Flash and Test Flash excluded).

Bit APEE can be temporarily disabled by executing the Set Protection operation and writing 1 into this bit, but only if this write instruction is executed from the memory itself to unprotect (EEPROM).

Bits APRO and APBR can be temporarily disabled through a direct write at NVAPR location, by overwriting at 1 these bits, but only if this write instruction is executed from the memory itself to unprotect.

To restore the accessprotection bits it needs to reset the micro or to execute a Set Protection operation and write 0 into the desired bits.

When an internal memory (Flash, TestFlash or EEPROM) is protected in access, also the data access through a DMA of a peripheral is forbidden (it returns FFh). To read data in DMA mode from a protected memory, first it is necessary to temporarily unprotect that memory.

The temporary unprotection allows also to update a protected code.

3.7 FLASH IN-SYSTEM PROGRAMMING

The Flash memory can be programmed in-system through a serial interface (SCI0).

Exiting from reset, the ST9 executes the initialization from the BootROM code (written in TestFlash), where it checks the value of the SOUT0 pin. If it is at 0, this means that the user wishes to update the Flash code, otherwise normal execution continues. In this second case, the BootROM code reads the first two locations of the Flash

memory (000000h-000001h) that represent the pointer to the start of the user code.

If the Flash is virgin (read content is always FFh), its first two locations contain FFFFh. This will represent the last location of segment0h, and itis interpreted by the BootROM code as a flag indicating that the Flash memory is virgin and needs to be programmed. If the value 1 is detected on the SOUT0 pin and the Flash is virgin, a HALT instruction is executed, waiting for a hardware Reset.

3.7.1 First Programming of a virgin Flash

After checking that the SOUT0 pin is at 0, the Boot

-ROM code enables the serial interface (typically an SCI) and writes in its Address Compare Register (ACR for SCI) a predefined address forrecognition. TheBootROM initializes the serial interface, including theinterrupt vector table in the TestFlash itself, the Interrupt Vector Register for the serial interface (IVR for SCI), the mask bit to enable the address match interrupt (bit RXA of IMR for SCI).

When the serial interface has received an address matching with the content of its Address Compare Register, an interrupt is generated and a predefined routine is executed located in TestFlash (Code Update Routine), that loads at a predefined address in the internal RAM a predefined number of bytes (the first datum sent) from the serial interface.

These bytes must represent a routine (the in-system programming routine) which is called at the end of the transfer.

This routine can, for example, load in the internal RAM (through the serial interface in DMA mode) a first table of data (256 bytes for example; depending on the available internal RAM size) to be programmed in Flash. Then the routine starts to program the Flash memory using the first table, while, in parallel, a second table of data are loaded in another location of the internal RAM, through the serial interface. When the slower of these two parallel operations is ended, a new cycle can start, till the whole Flash memory is programmed.

At the end of Flash programming the execution returns to the Code Update Routine in TestFlash that puts the ST9 in HALT mode, waiting for a hardware reset.

Page 58

58/320

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

Figure 28. Flash in-system Programming.

TestFlash Code

Start

Initialisation

Enable Serial

Interface

Jump to Flash

Main

Code

In-system

prog routine

Flash

virgin ?

Erase sectors

Yes

Load 1st table of data in RAM through S.I.

Prog 1st table of data from RAM in Flash

Load 2nd table

of data in RAM through SCI

Inc. Address

Last

Address ?

RET

Yes

Code Update

Routine

Enable DMA

Load in-system

prog routine

in internal RAM

through SCI.

Call in-system

prog routine

HALT

Address Match

Interrupt

(from SCI)

User

Test

Internal RAM (User Code Example)

SOUT0

=0?

YesNo

WFI

Flash

Page 59

59/320

ST92F120 - REGISTER AND MEMORY MAP

4 REGISTER AND MEMORY MAP

4.1 INTRODUCTION

The ST92F120 register map, memory map and peripheral options are documented in this section. Use this reference information to supplement the functional descriptions given elsewhere in this document.

4.2 MEMORY CONFIGURATION

The Program memory space of the ST92F120 up to 128K bytes of directly addressable on-chip memory, is fully available to the user.

The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap

Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predetermined function.

Table 14. First 6 Bytes of Program Space

0 Address high of Power on Reset routine 1 Address low of Power on Reset routine 2 Address high of Divide by zero trap Subroutine 3 Address low of Divide by zero trap Subroutine 4 Address high of Top Level Interrupt routine 5 Address low of Top Level Interrupt routine

Page 60

60/320

ST92F120 - REGISTER AND MEMORY MAP

Figure 29. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 1)

SEGMENT 1

64 Kbytes

FLASH - 128 Kbytes

SEGMENT 0

64 Kbytes

01FFFFh 01C000h

01BFFFh 018000h

017FFFh 014000h

010000h

013FFFh

00FFFFh 00C000h

00BFFFh 008000h

007FFFh 004000h

000000h

003FFFh

PAGE 7 - 16 Kbytes

PAGE 0 - 16 Kbytes

PAGE 1 - 16 Kbytes

PAGE 2 - 16 Kbytes

PAGE 3 - 16 Kbytes

PAGE 4 - 16 Kbytes

PAGE 5 - 16 Kbytes

PAGE 6 - 16 Kbytes

SECTOR F0

64 Kbytes

Emulated EEPROM - 1 Kbyte

SEGMENT 22

64 Kbytes

220000h

22FFFFh 22C000h

22BFFFh 228000h

227FFFh 224000h

223FFFh

PAGE 88 - 16 Kbytes

PAGE 89 - 16 Kbytes

PAGE 90 - 16 Kbytes

PAGE 91 - 16 Kbytes

220000h

2203FFh

1 Kbyte

FLASH / EEPROM - 4 + 4 Kbytes

SEGMENT 22

64 Kbytes

220000h

22FFFFh 22C000h

22BFFFh 228000h

227FFFh 224000h

223FFFh

PAGE 88 - 16 Kbytes

PAGE 89 - 16 Kbytes

PAGE 90 - 16 Kbytes

PAGE 91 - 16 Kbytes

22C000h

22CFFFh

4 Kbytes Sector F5/E1

228000h

228FFFh

4 Kbytes Sector F4/E0

Not Available

SECTOR F1

48 Kbytes

SECTOR F2

8 Kbytes

SECTOR F3

8 Kbytes

Page 61

61/320

ST92F120 - REGISTER AND MEMORY MAP

Figure 30. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 2)

TESTFLASH - 8 Kbytes

SEGMENT 23

64 Kbytes

230000h

23FFFFh 23C000h

23BFFFh 238000h

237FFFh 234000h

233FFFh

PAGE 92 - 16 Kbytes

PAGE 93 - 16 Kbytes

PAGE 94 - 16 Kbytes

PAGE 95 - 16 Kbytes

230000h

231FFFh

8 Kbytes

231F80h

231FFFh

FLASH OTP - 128 bytes

231FFCh

231FFFh

FLASH OTP Protection - 4 bytes

FLASH Registers - 4 bytes

SEGMENT 22

64 Kbytes

220000h

22FFFFh 22C000h

22BFFFh 228000h

227FFFh 224000h

223FFFh

PAGE 88 - 16 Kbytes

PAGE 89 - 16 Kbytes

PAGE 90 - 16 Kbytes

PAGE 91 - 16 Kbytes

224000h

224003h

4 bytes

128 bytes

4 bytes

Not Available

Page 62

62/320

ST92F120 - REGISTER AND MEMORY MAP

Figure 31. ST92F120 User Memory Map (part 3)

4.3 ST92F120 REGISTER MAP

Table 16 contain the map of thegroupF peripheral pages.

The common registers used by each peripheral are listed in Table 15.

Be very careful tocorrectly program both: – The set of registers dedicated to a particular

function or peripheral.

– Registers common to other functions. – In particular, double-check that any registers

with “undefined” resetvalues have been correctly initialised.

Warning: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entriesin theInterrupt Vector table do not overlap.

Table 15. Common Registers

RAM

SEGMENT 20

64 Kbytes

200000h

20FFFFh 20C000h

20BFFFh 208000h

207FFFh 204000h

203FFFh

PAGE 80 - 16 Kbytes

PAGE 81 - 16 Kbytes

PAGE 82 - 16 Kbytes

PAGE 83 - 16 Kbytes

200000h

200FFFh

Not Available

2005FFh

2007FFh

1.5 Kbytes

2 Kbytes

4 Kbytes

Function or Peripheral Common Registers

SCI, MFT CICR + NICR + DMA REGISTERS + I/O PORT REGISTERS

A/D CICR + NICR + I/O PORT REGISTERS

SPI, WDT, STIM

CICR + NICR + EXTERNAL INTERRUPT REGISTERS + I/O PORT REGISTERS

I/O PORTS I/O PORT REGISTERS + MODER

EXTERNAL INTERRUPT INTERRUPT REGISTERS + I/O PORT REGISTERS

RCCU INTERRUPT REGISTERS + MODER

Page 63

63/320

ST92F120 - REGISTER AND MEMORY MAP

Table 16. GroupF Pages Register Map

Resources available on the ST92F120 device:

Reg. Page

0237891011202123242528294355576163

R255

Res.

Res

Port 7

Res.

MFT1

Res.

MFT0

Res.

I2C

MMU

JBLPD

SCI0

SCI1

EFT0

EFT1

Port 9

Res.

WUIMU

A/D 1

A/D 0

R254

Port 3

R253

R252

WCR

R251

WDT

Res

Port 6

Port 8

R250

Port 2

R249

R248

Res.

R247

EXT INT

Res. Res.

MFT1

Res.

R246

Port 1

Port 5

RCCU

R245

R244

R243 Res. Res.

SPI

MFT0

STIM

R242

Port 0

Port 4

R241

Res.

R240

MFT1

MFT0

Page 64

64/320

ST92F120 - REGISTER AND MEMORY MAP

Table 17. Detailed Register Map

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

N/A

Core

R230 CICR Central Interrupt Control Register 87 28 R231 FLAGR Flag Register 00 29 R232 RP0 Pointer 0 Register xx 31 R233 RP1 Pointer 1 Register xx 31 R234 PPR Page Pointer Register xx 33 R235 MODER Mode Register E0 33 R236 USPHR User Stack Pointer High Register xx 35 R237 USPLR User Stack Pointer Low Register xx 35 R238 SSPHR System Stack Pointer High Reg. xx 35 R239 SSPLR System Stack Pointer Low Reg. xx 35

I/O

Port

0:5

R224 P0DR Port 0 Data Register FF

123

R225 P1DR Port 1 Data Register FF R226 P2DR Port 2 Data Register FF R227 P3DR Port 3 Data Register FF R228 P4DR Port 4 Data Register FF R229 P5DR Port 5 Data Register FF

INT

R242 EITR External Interrupt Trigger Register 00 83 R243 EIPR External Interrupt Pending Reg. 00 84 R244 EIMR External Interrupt Mask-bit Reg. 00 84 R245 EIPLR External Interrupt Priority Level Reg. FF 84 R246 EIVR External Interrupt Vector Register x6 135 R247 NICR Nested Interrupt Control 00 85

WDT

R248 WDTHR Watchdog Timer High Register FF 134 R249 WDTLR Watchdog Timer Low Register FF 134 R250 WDTPR Watchdog Timer Prescaler Reg. FF 134 R251 WDTCR Watchdog Timer Control Register 12 134 R252 WCR Wait Control Register 7F 135

I/O

Port

R240 P0C0 Port 0 Configuration Register 0 00

123

R241 P0C1 Port 0 Configuration Register 1 00 R242 P0C2 Port 0 Configuration Register 2 00

I/O

Port

R244 P1C0 Port 1 Configuration Register 0 00 R245 P1C1 Port 1 Configuration Register 1 00 R246 P1C2 Port 1 Configuration Register 2 00

I/O

Port

R248 P2C0 Port 2 Configuration Register 0 FF R249 P2C1 Port 2 Configuration Register 1 00 R250 P2C2 Port 2 Configuration Register 2 00

I/O

Port

R252 P3C0 Port 3 Configuration Register 0 FE R253 P3C1 Port 3 Configuration Register 1 00 R254 P3C2 Port 3 Configuration Register 2 00

Page 65

65/320

ST92F120 - REGISTER AND MEMORY MAP

I/O

Port

R240 P4C0 Port 4 Configuration Register 0 FD

123

R241 P4C1 Port 4 Configuration Register 1 00 R242 P4C2 Port 4 Configuration Register 2 00

I/O

Port

R244 P5C0 Port 5 Configuration Register 0 FF R245 P5C1 Port 5 Configuration Register 1 00 R246 P5C2 Port 5 Configuration Register 2 00

I/O

Port

R248 P6C0 Port 6 Configuration Register 0 3F R249 P6C1 Port 6 Configuration Register 1 00 R250 P6C2 Port 6 Configuration Register 2 00 R251 P6DR Port 6 Data Register FF

I/O

Port

R252 P7C0 Port 7 Configuration Register 0 FF R253 P7C1 Port 7 Configuration Register 1 00 R254 P7C2 Port 7 Configuration Register 2 00 R255 P7DR Port 7 Data Register FF

7 SPI

R240 SPDR0 SPI0 Data Register 00 219 R241 SPCR0 SPI0 Control Register 00 219 R242 SPSR0 SPI0 Status Register 00 220 R243 SPPR0 SPI0 Prescaler Register 00 220

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 66

66/320

ST92F120 - REGISTER AND MEMORY MAP

MFT1

R240 REG0HR1 Capture Load Register 0 High xx 174 R241 REG0LR1 Capture Load Register 0 Low xx 174 R242 REG1HR1 Capture Load Register 1 High xx 174 R243 REG1LR1 Capture Load Register 1 Low xx 174 R244 CMP0HR1 Compare 0 Register High 00 174 R245 CMP0LR1 Compare 0 Register Low 00 174 R246 CMP1HR1 Compare 1 Register High 00 174 R247 CMP1LR1 Compare 1 Register Low 00 174 R248 TCR1 Timer Control Register 00 175 R249 TMR1 Timer Mode Register 00 176 R250 T_ICR1 External Input Control Register 00 177 R251 PRSR1 Prescaler Register 00 177 R252 OACR1 Output A Control Register 00 178 R253 OBCR1 Output B Control Register 00 179 R254 T_FLAGR1 Flags Register 00 179 R255 IDMR1 Interrupt/DMA Mask Register 00 181

R244 DCPR1 DMA Counter Pointer Register xx 174 R245 DAPR1 DMA Address Pointer Register xx 174 R246 T_IVR1 Interrupt Vector Register xx 174 R247 IDCR1 Interrupt/DMA Control Register C7 174

MFT0,1 R248 IOCR I/O Connection Register FC 183

MFT0

R240 DCPR0 DMA Counter Pointer Register xx 181 R241 DAPR0 DMA Address Pointer Register xx 182 R242 T_IVR0 Interrupt Vector Register xx 182 R243 IDCR0 Interrupt/DMA Control Register C7 183

R240 REG0HR0 Capture Load Register 0 High xx 174 R241 REG0LR0 Capture Load Register 0 Low xx 174 R242 REG1HR0 Capture Load Register 1 High xx 174 R243 REG1LR0 Capture Load Register 1 Low xx 174 R244 CMP0HR0 Compare 0 Register High 00 174 R245 CMP0LR0 Compare 0 Register Low 00 174 R246 CMP1HR0 Compare 1 Register High 00 174 R247 CMP1LR0 Compare 1 Register Low 00 174 R248 TCR0 Timer Control Register 00 175 R249 TMR0 Timer Mode Register 00 176 R250 T_ICR0 External Input Control Register 00 177 R251 PRSR0 Prescaler Register 00 177 R252 OACR0 Output A Control Register 00 178 R253 OBCR0 Output B Control Register 00 179 R254 T_FLAGR0 Flags Register 00 179 R255 IDMR0 Interrupt/DMA Mask Register 00 181

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 67

67/320

ST92F120 - REGISTER AND MEMORY MAP

11 STIM

R240 STH Counter High Byte Register FF 139 R241 STL Counter Low Byte Register FF 139 R242 STP Standard Timer Prescaler Register FF 139 R243 STC Standard Timer Control Register 14 139

20 I2C

R240 I2DCCR I

C Control Register 00 232

R241 I2CSR1 I

C Status Register 1 00 233

R242 I2CSR2 I

C Status Register 2 00 235

R243 I2CCCR I

C Clock Control Register 00 236

R244 I2COAR1 I

C Own Address Register 1 00 236

R245 I2COAR2 I

C Own Address Register 2 00 237

R246 I2CDR I

C DataRegister 00 237

R247 I2CADR I

C General Call Address A0 237

R248 I2CISR I

C Interrupt Status Register xx 238

R249 I2CIVR I

C Interrupt Vector Register xx 239 R250 I2CRDAP Receiver DMA Source Addr. Pointer xx 239 R251 I2CRDC Receiver DMA Transaction Counter xx 239 R252 I2CTDAP Transmitter DMA Source Addr. Pointer xx 240 R253 I2CTDC Transmitter DMA Transaction Counter xx 240 R254 I2CECCR Extended Clock Control Register 00 240 R255 I2CIMR I

C Interrupt Mask Register x0 241

MMU

R240 DPR0 Data Page Register 0 xx 40 R241 DPR1 Data Page Register 1 xx 40 R242 DPR2 Data Page Register 2 xx 40 R243 DPR3 Data Page Register 3 xx 40 R244 CSR Code Segment Register 00 41 R248 ISR Interrupt Segment Register xx 41 R249 DMASR DMA Segment Register xx 41

EXTMI

R245 EMR1 External Memory Register 1 80 120 R246 EMR2 External Memory Register 2 1F 121

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 68

68/320

ST92F120 - REGISTER AND MEMORY MAP

23 JBLPD

R240 STATUS Status Register 40 264 R241 TXDATA Transmit Data Register xx 265 R242 RXDATA Receive Data Register xx 266 R243 TXOP Transmit Opcode Register 00 266 R244 CLKSEL System Frequency Selection Register 00 271 R245 CONTROL Control Register 40 271 R246 PADDR Physiscal Address Register xx 272 R247 ERROR Error Register 00 273 R248 IVR Interrupt Vector Register xx 275 R249 PRLR Priority Level Register 10 275 R250 IMR Interrupt Mask Register 00 275 R251 OPTIONS Options and Register Group Selection 00 277 R252 CREG0 Current Register 0 xx 279 R253 CREG1 Current Register 1 xx 279 R254 CREG2 Current Register 2 xx 279 R255 CREG3 Current Register 4 xx 279

24 SCI0

R240 RDCPR0 Receiver DMA Transaction Counter Pointer xx 199 R241 RDAPR0 Receiver DMA Source Address Pointer xx 199 R242 TDCPR0 Transmitter DMA Transaction Counter Pointer xx 199 R243 TDAPR0 Transmitter DMA Destination Address Pointer xx 199 R244 S_IVR0 Interrupt Vector Register xx 201 R245 ACR0 Address/Data Compare Register xx 201 R246 IMR0 Interrupt Mask Register x0 201 R247 S_ISR0 Interrupt Status Register xx 201 R248 RXBR0 Receive Buffer Register xx 203 R248 TXBR0 Transmitter Buffer Register xx 203 R249 IDPR0 Interrupt/DMA Priority Register xx 204 R250 CHCR0 Character Configuration Register xx 205 R251 CCR0 Clock Configuration Register 00 206 R252 BRGHR0 Baud Rate Generator High Reg. xx 207 R253 BRGLR0 Baud Rate Generator Low Register xx 207 R254 SICR0 Synchronous Input Control 03 207 R255 SOCR0 Synchronous Output Control 01 208

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 69

69/320

ST92F120 - REGISTER AND MEMORY MAP

25 SCI1

R240 RDCPR1 Receiver DMA Transaction Counter Pointer xx 199 R241 RDAPR1 Receiver DMA Source Address Pointer xx 199 R242 TDCPR1 Transmitter DMA Transaction Counter Pointer xx 199 R243 TDAPR1 Transmitter DMA Destination Address Pointer xx 199 R244 S_IVR1 Interrupt Vector Register xx 201 R245 ACR1 Address/Data Compare Register xx 201 R246 IMR1 Interrupt Mask Register x0 201 R247 S_ISR1 Interrupt Status Register xx 201 R248 RXBR1 Receive Buffer Register xx 203 R248 TXBR1 Transmitter Buffer Register xx 203 R249 IDPR1 Interrupt/DMA Priority Register xx 204 R250 CHCR1 Character Configuration Register xx 205 R251 CCR1 Clock Configuration Register 00 206 R252 BRGHR1 Baud Rate Generator High Reg. xx 207 R253 BRGLR1 Baud Rate Generator Low Register xx 207 R254 SICR1 Synchronous Input Control 03 207 R255 SOCR1 Synchronous Output Control 01 208

28 EFT0

R240 IC1HR0 Input Capture 1 High Register xx 152 R241 IC1LR0 Input Capture 1 Low Register xx 152 R242 IC2HR0 Input Capture 2 High Register xx 152 R243 IC2LR0 Input Capture 2 Low Register xx 152 R244 CHR0 Counter High Register FF 153 R245 CLR0 Counter Low Register FC 153 R246 ACHR0 Alternate Counter High Register FF 153 R247 ACLR0 Alternate Counter Low Register FC 153 R248 OC1HR0 OutputCompare 1 High Register 80 154 R249 OC1LR0 Output Compare 1 Low Register 00 154 R250 OC2HR0 OutputCompare 2 High Register 80 154 R251 OC2LR0 Output Compare 2 Low Register 00 154 R252 CR1_0 Control Register 1 00 156 R253 CR2_0 Control Register 2 00 156 R254 SR0 Status Register 00 156 R255 CR3_0 Control Register 3 00 156

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 70

70/320

ST92F120 - REGISTER AND MEMORY MAP

29 EFT1

R240 IC1HR1 Input Capture 1 High Register xx 152 R241 IC1LR1 Input Capture 1 Low Register xx 152 R242 IC2HR1 Input Capture 2 High Register xx 152 R243 IC2LR1 Input Capture 2 Low Register xx 152 R244 CHR1 Counter High Register FF 153 R245 CLR1 Counter Low Register FC 153 R246 ACHR1 Alternate Counter High Register FF 153 R247 ACLR1 Alternate Counter Low Register FC 153 R248 OC1HR1 OutputCompare 1 High Register 80 154 R249 OC1LR1 Output Compare 1 Low Register 00 154 R250 OC2HR1 OutputCompare 2 High Register 80 154 R251 OC2LR1 Output Compare 2 Low Register 00 154 R252 CR1_1 Control Register 1 00 156 R253 CR2_1 Control Register 2 00 156 R254 SR1 Status Register 00 156 R255 CR3_1 Control Register 3 00 156

I/O

Port

R248 P8C0 Port 8 Configuration Register 0 03

123

R249 P8C1 Port 8 Configuration Register 1 00 R250 P8C2 Port 8 Configuration Register 2 00 R251 P8DR Port 8 Data Register FF

I/O

Port

R252 P9C0 Port 9 Configuration Register 0 00 R253 P9C1 Port 9 Configuration Register 1 00 R254 P9C2 Port 9 Configuration Register 2 00 R255 P9DR Port 9 Data Register FF

55 RCCU

R240 CLKCTL Clock Control Register 00 106 R242 CLK_FLAG Clock Flag Register 48, 28 or 08 107 R246 PLLCONF PLL Configuration Register xx 107

57 WUIMU

R249 WUCTRL Wake-Up Control Register 00 91 R250 WUMRH Wake-Up MaskRegister High 00 92 R251 WUMRL Wake-Up Mask Register Low 00 92 R252 WUTRH Wake-Up Trigger Register High 00 93 R253 WUTRL Wake-Up Trigger Register Low 00 93 R254 WUPRH Wake-Up Pending Register High 00 93 R255 WUPRL Wake-Up Pending Register Low 00 93

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 71

71/320

ST92F120 - REGISTER AND MEMORY MAP

Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register

description for details.

61 A/D 1

R240 D0R1 Channel 0 Data Register xx 288 R241 D1R1 Channel 1 Data Register xx 288 R242 D2R1 Channel 2 Data Register xx 288 R243 D3R1 Channel 3 Data Register xx 288 R244 D4R1 Channel 4 Data Register xx 288 R245 D5R1 Channel 5 Data Register xx 288 R246 D6R1 Channel 6 Data Register xx 288 R247 D7R1 Channel 7 Data Register xx 288 R248 LT6R1 Channel 6 Lower Threshold Reg. xx 289 R249 LT7R1 Channel 7 Lower Threshold Reg. xx 289 R250 UT6R1 Channel 6 Upper Threshold Reg. xx 289 R251 UT7R1 Channel 7 Upper Threshold Reg. xx 289 R252 CRR1 Compare Result Register 0F 289 R253 CLR1 Control Logic Register 00 290 R254 AD_ICR1 Interrupt Control Register 0F 291 R255 AD_IVR1 Interrupt Vector Register x2 291

63 A/D 0

R240 D0R0 Channel 0 Data Register xx 288 R241 D1R0 Channel 1 Data Register xx 288 R242 D2R0 Channel 2 Data Register xx 288 R243 D3R0 Channel 3 Data Register xx 288 R244 D4R0 Channel 4 Data Register xx 288 R245 D5R0 Channel 5 Data Register xx 288 R246 D6R0 Channel 6 Data Register xx 288 R247 D7R0 Channel 7 Data Register xx 288 R248 LT6R0 Channel 6 Lower Threshold Reg. xx 289 R249 LT7R0 Channel 7 Lower Threshold Reg. xx 289 R250 UT6R0 Channel 6 Upper Threshold Reg. xx 289 R251 UT7R0 Channel 7 Upper Threshold Reg. xx 289 R252 CRR0 Compare Result Register 0F 289 R253 CLR0 Control Logic Register 00 290 R254 AD_ICR0 Interrupt Control Register 0F 291 R255 AD_IVR0 Interrupt Vector Register x2 291

Page (Dec)

Block

Reg.

No.

Name

Description

Reset

Value

Hex.

Doc.

Page

Page 72

72/320

ST92F120 - INTERRUPTS

5 INTERRUPTS

5.1 INTRODUCTION

The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate Interrupt Service Routine.

The ST9 CPU can receive requests from the following sources:

– On-chip peripherals – External pins – Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an

event occurrence can generate an Interrupt request which depends on the selected mode.

Up to eight external interrupt channels, with programmable inputtrigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt,or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory.

Figure 32. Interrupt Response

5.2 INTERRUPT VECTORING

The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically.

When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer).

Each peripheral has a specific IVR mapped within its Register File pages.

The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thusallowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU.

The user Power on Reset vector is stored in the first two physical bytes in memory, 000000h and 000001h.

The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR).

With one Interrupt Vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled bythe interrupt module, in hardware, to select the appropriate vector.

Note: The first 256 locations of the memory segment pointed toby ISR can contain program code.

5.2.1 Divide by Zero trap

The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required.

Warning.Although the Divide by Zero Trap oper-

ates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET ).

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE ROUTINE

IRET

INSTRUCTION

INTERRUPT

VR001833

CLEAR

PENDING BIT

Page 73

73/320

ST92F120 - INTERRUPTS

5.2.2 Segment Paging During Interrupt Routines

The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compatibility mode and ST9+ interrupt management mode.

ST9 backward compatibility mode(ENCSR =0)

If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed.

This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time.

It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes.

ST9+ mode (ENCSR = 1)

If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR ispushedonto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR.

In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. Thedrawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack.

Full compatibilitywiththe original ST9 is lost in this case, because the interrupt stack frame is different.

5.3 INTERRUPT PRIORITY LEVELS

The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships:

– The on-chip peripheral channels and the eight

external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority).

– The 9th level (Top Level Priority) is reserved for

the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask canbebothmaskable (TLI) or non-maskable (TLNM).

5.4 PRIORITY LEVEL ARBITRATION

The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware according to the selected Arbitration Mode.

During every instruction, an arbitration phase takes place, during which,for every channel capable of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA).

If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) thanthe CPL value stored in the CICR register (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority.

5.4.1 Priority level 7 (Lowest)

Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL value. This can be of usein a fully polled interrupt environment.

5.4.2 Maximum depth of nesting

No more than 8 routinescan be nested. If an interrupt routine at level N is being serviced, no other Interrupts located at level N can interrupt it. This guarantees a maximum numberof 8 nested levels including the Top Level Interrupt request.

5.4.3 Simultaneous Interrupts

If two or more requests occurat the sametime and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel

ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped

Registers

PC, FLAGR

PC, FLAGR,

CSR

Max. Code Size for interrupt service routine

64KB

Within 1 segment

No limit

Across segments

Page 74

74/320

ST92F120 - INTERRUPTS

with thehighest position in the chain, as shown in Table 18

Table 18. Daisy Chain Priority

5.4.4 Dynamic Priority Level Modification

The main program androutines can be specifically prioritized. Since the CPL is represented by 3 bits in a read/write register, it is possible to modify dynamically the current priority value during program execution. This means that a critical section can have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by modifying the CPL during its execution. See Figure 33.

Figure 33. Example of Dynamic priority level modification in Nested Mode

5.5 ARBITRATION MODES

The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested mode. Concurrent mode is the standard interrupt arbitration mode.

Nested mode improves the effective interrupt response time when service routine nesting is required, depending on the request priority levels.

The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested Arbitration Mode.

5.5.1 Concurrent Mode

This mode is selected when the IAM bit is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode.

Start of Interrupt Routine

The interrupt cycle performs the following steps: – All maskable interrupt requests are disabled by

clearing CICR.IEN. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – If ENCSR is set, CSR is pushed onto system

stack. – The Flag register is pushed onto system stack. – The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR. – If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR isused in placeof CSRuntil

iret instruction.

End of Interrupt Routine

The Interrupt Service Routine must be ended with the iret instruction. The iret instruction executes the following operations:

– The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system

stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – All unmasked Interrupts are enabled by setting

the CICR.IEN bit. – If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumesat the in-

terrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine).

Note:In Concurrentmode, the sourcepriority level is only useful during thearbitration phase,where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is

Highest Position

Lowest Position

INTA0 / Watchdog Timer INTA1 / Standard Timer INTB0 / Extended Function Timer 0 INTB1 / Extended Function Timer 1 INTC0 / EEPROM/Flash INTC1 / SPI INTD0 / RCCU INTD1 / WKUP MGT Multifunction Timer 0 JBLPD I

C bus Interface A/D Converter 0 A/D Converter 1 Multifunction Timer 1 Serial Communication Interface 0

Serial Communication Interface 1

Priority Level

MAIN

CPL is set to 5

CPL=7

MAIN

INT 6

CPL=6

INT6

CPL is set to 7

CPL6 > CPL5: INT6 pending

INTERRUPT 6 HAS PRIORITY LEVEL 6

by MAIN program

Page 75

75/320

ST92F120 - INTERRUPTS

ARBITRATION MODES (Cont’d)

re-enabled, they will be acknowledged regardless of the interrupt service routine’s priority. This may cause undesirable interrupt response sequences.

Examples

In the following two examples, three interrupt requests with different priority levels (2, 3& 4) occur simultaneously during the interrupt 5 service routine.

Example 1

In the first example, (simplest case, Figure 34) the ei instruction is not used within the interrupt service routines. This means that no new interrupt can be serviced in the middle of the current one. The interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes.

Figure 34. Simple Example of a Sequence of Interrupt Requests with:

- Concurrent mode selected and

- IEN unchanged by the interrupt routines

Priority Level of

MAIN

INT 5

INT 2

INT 3

INT 4

MAIN

INT 5

INT4

INT3

INT2

CPL is set to 7

CPL = 7

INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5

Interrupt Request

Page 76

76/320

ST92F120 - INTERRUPTS

ARBITRATION MODES (Cont’d) Example 2

In the second example, (more complex, Figure

35), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than the one being serviced.

The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-

ice routines being executed in the opposite order of their priority.

It is therefore recommended to avoid inserting the ei instruction in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode.

WARNING: If, in Concurrent Mode, interrupts are

nested (by executing ei in an interrupt service routine), make sure that either ENCSR is set or CSR=ISR, otherwise the iret of the innermost interrupt will make the CPU use CSR instead of ISR before the outermost interrupt service routine is terminated, thus making the outermost routine fail.

Figure 35. Complex Example of a Sequence of Interrupt Requests with:

- Concurrent mode selected

- IEN set to 1 during interrupt service routine execution

MAIN

INT 5

INT 2

INT 3

INT 4

INT 5

INT4

INT3

INT2

CPL is set to 7

CPL = 7

INTERRUPT2 HAS PRIORITY LEVEL 2 INTERRUPT3 HAS PRIORITY LEVEL 3 INTERRUPT4 HAS PRIORITY LEVEL 4 INTERRUPT5 HAS PRIORITY LEVEL 5

INT 2

INT 3

CPL = 7

INT 5

CPL = 7

MAIN

Priority Level of Interrupt Request

Page 77

77/320

ST92F120 - INTERRUPTS

ARBITRATION MODES (Cont’d)

5.5.2 Nested Mode

The difference between Nested mode and Concurrent mode, lies in the modification of the Current Priority Level (CPL) during interrupt processing.

The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in theNested Interrupt Control Register (NICR) by setting the NICR bit corresponding to the CPL value (i.e. if the CPL is 3, the bit 3 will be set).

The CPL isthen loaded with the priority of the request justacknowledged;thenext arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being executed.

Start of Interrupt Routine

The interrupt cycle performs the following steps:

– All maskable interrupt requests are disabled by

clearing CICR.IEN.

– CPL is saved in the special NICR stack to hold

the priority level of the suspended routine.

– Priority level of the acknowledged routine is

stored in CPL, so that the next request priority will be compared with the one of the routine cur-

rently being serviced. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – If ENCSR is set, CSR is pushed onto system

stack. – The Flag register is pushed onto system stack. – The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR. – If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR isused in placeof CSRuntil

iret instruction.

Figure 36. Simple Example of a Sequence of Interrupt Requests with:

- Nested mode

- IEN unchanged by the interrupt routines

MAIN

INT 2

INT0

INT4

INT3

INT2

CPL is set to 7

CPL=2

CPL=7

INTERRUPT2 HAS PRIORITY LEVEL 2 INTERRUPT3 HAS PRIORITY LEVEL 3 INTERRUPT4 HAS PRIORITY LEVEL 4 INTERRUPT5 HAS PRIORITY LEVEL 5

MAIN

INT 3

CPL=3

INT6

CPL=6

INT5

INT 0

CPL=0

INT6

INT2

INTERRUPT6 HAS PRIORITY LEVEL 6

INTERRUPT0 HAS PRIORITY LEVEL 0

CPL6 > CPL3: INT6 pending

CPL2 < CPL4: Serviced next

INT 2

CPL=2

INT 4

CPL=4

INT 5

CPL=5

Priority Level of Interrupt Request

Page 78

78/320

ST92F120 - INTERRUPTS

ARBITRATION MODES (Cont’d) End of Interrupt Routine

The iret Interrupt Return instruction executes the following steps:

– The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system

stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – All unmasked Interrupts are enabled by setting

the CICR.IEN bit. – The priority level of the interrupted routine is

popped from the special register (NICR) and

copied into CPL.

– If ENCSR is reset, CSR is used instead of ISR,

unless the program returns to another nested routine.

The suspended routine thus resumes at the interrupted instruction.

Figure 36containsa simpleexample, showingthat if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent.

Figure 37 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routinesi using the ei instruction) according to their priority level.

Figure 37. Complex Example of a Sequence of Interrupt Requests with:

- Nested mode

- IEN set to 1 during the interrupt routineexecution

INT 2

INT 3

CPL=3

INT 0

CPL=0

INT6

MAIN

INT5

INT 4

INT0

INT4

INT3

INT2

CPL is set to 7

CPL=5

CPL=4

CPL=2

CPL=7

INTERRUPT 2 HAS PRIORITYLEVEL 2 INTERRUPT 3 HAS PRIORITYLEVEL 3 INTERRUPT 4 HAS PRIORITYLEVEL 4 INTERRUPT 5 HAS PRIORITYLEVEL 5

INT 2

INT 4

CPL=2

CPL=4

INT 5

CPL=5

MAIN

INT 2

CPL=2

INT 6

CPL=6

INT5

INT2

INTERRUPT 6 HAS PRIORITYLEVEL 6

INTERRUPT 0 HAS PRIORITYLEVEL 0

CPL6 > CPL3: INT6 pending

CPL2 < CPL4: Serviced just after ei

Priority Level of Interrupt Request

Page 79

79/320

ST92F120 - INTERRUPTS

5.6 EXTERNAL INTERRUPTS

5.6.1 Standard External Interrupts

The standard ST9 core contains 8 external interrupts sources grouped into four pairs.

Table 19. External Interrupt Channel Grouping

Each source has a trigger control bit TEA0,..TED1 (R242,EITR.0,..,7 Page 0) to select triggering on the rising or falling edge of the external pin. If the Trigger control bit is set to “1”, the corresponding pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page

0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the input pin. Each source can be individually masked through the corresponding control bit IMA0,..,IMD1 (EIMR.7,..,0). See Figure 39.

Figure 38. Priority Level Examples

The priority level of the external interrupt sources can be programmed among the eight priority levels with the control register EIPLR (R245). The priority level of each pair is software defined using the bitsPRL2,PRL1.For each pair, the even channel (A0,B0,C0,D0) of the group has the even priority level and the odd channel (A1,B1,C1,D1) has the odd (lower) priority level.

Figure 38 shows an example of priority levels. Figure 39 gives an overview of the external inter-

rupts and vectors.

– The source of interrupt channel A0 can be se-

lected between the external pin INT0 or the Timer/Watchdog peripheral usingtheIA0S bit in the EIVR register (R246 Page 0).

– The source of interrupt channel A1 can be se-

lected between the external pin INT1 or the Standard Timer using the INTS bit in the STC register (R232 Page 11).

– The source of the interrupt channel B0 can be

selected between the external pin INT2 or the on-chip Extended Function Timer 0 using the EFTIS bit in the CR3 register (R255 Page 28).

– The source of interrupt channel B1 can be se-

lected between external pin INT3 or the on-chip Extended Function Timer 1 using the EFTIS bit in the CR3 register (R255 Page 29).

– The source of the interrupt channel C0 can be

selected between external pin INT4 or the Onchip EEPROM/Flash Memory using bit FEIEN in the ECR register (Address 224001h).

– The source of interrupt channel C1 can be se-

lected between external pin INT5 or the on-chip SPI using the SPIS bit in the SPCR0 register (R241 Page 7).

– The source of interrupt channel D0 can be se-

lected between external pin INT6 or the Reset and Clock Unit RCCU using the INT_SEL bit in the CLKCTL register (R240 Page 55).

– The source of interrupt channel D1 selected be-

tween the NMI pin and the WUIMU Wakeup/Interrupt Lines usingthe ID1S bit in the WUCRTL register (R248 Page 9).

Warning: When using external interrupt channels shared by both external interrupts and peripherals, special care must be taken to configure control registers both for peripheral and interrupts.

External

Interrupt

Channel I/O Port Pin

WKUP[0:15] INTD1

P8[1:0] P7[7:5]

P6[7,5] P5[7:5, 2:0] P4[7,4]

INT6 INT5 INT4 INT3 INT2 INT1 INT0

INTD0 INTC1 INTC0 INTB1 INTB0 INTA1 INTA0

P6.1 P6.3 P6.2 P6.3 P6.2 P6.0 P6.0

1 001001

PL2D PL1D PL2CPL1C PL2B PL1B PL2APL1A

INT.D1:

INT.C1: 001=1

INT.D0:

SOURCE PRIORITY PRIORITYSOURCE

INT.A0: 010=2 INT.A1: 011=3

INT.B1: 101=5

INT.B0: 100=4INT.C0: 000=0

EIPLR

VR000151

100=4

101=5

Channel Internal Interrupt Source

External

Interrupt

Source

INTA0 Timer/Watchdog INT0 INTA1 Standard Timer INT1 INTB0 Extended Function Timer 0 INT2 INTB1 Extended Function Timer 1 INT3 INTC0 EEPROM/Flash INT4 INTC1 SPI Interrupt INT5 INTD0 RCCU INT6 INTD1 Wake-up Management Unit

Page 80

80/320

ST92F120 - INTERRUPTS

EXTERNAL INTERRUPTS (Cont’d) Figure 39. External Interrupts Control Bits and Vectors

* Only four interrupt pins are available at the same time. Refer to Table 19 for I/O pin mapping.

INT A0 request

VECTOR

Priority level Mask bit Pending bitIMA0 IPA0

V7 V6 V5 V4 0

00X

“0”

“1”

IA0S

Watchdog/Timer

End of count

INT 0 pin*

INT A1 request

INT 6 pin

INT B0 request

INT 2 pin*

INT B1 request

TEB1

INT 3 pin*

INT C0

request

INT C1 request

INT D0 request

INT D1 request

VECTOR

Priority level

Mask bit Pending bit

IMA1

IPA1

V7V6V5 V4 0 01X

V7V6V5 V4 0 10X

V7 V6 V5 V4 0

11X

V7V6V5 V4 1

00X

V6 V5 V4

01X

V7V6V5 V4 1 10X

XX0

V6 V5 V4 1

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

VECTOR

Priority level

Mask bit

IMB0

Pending bit IPB0

Pending bit IPB1

Pending bit IPC0

Pending bit IPC1

Pending bit IPD0

Pending bit IPD1

Mask bit

IMB1

Mask bit

IMC0

Mask bit IMC1

Mask bit

IMD0

Mask bit

IMD1

SPIS

SPI Interrupt

“1”

“0”

INTS

STD Timer

“1”

“0”

INT_SEL

RCCU

“0”

“1”

TEA0

TEB0

“0”

“1”

TED0

EFTIS

EFT1 Timer

“0”

“1”

“0”

EFTIS

EFT0Timer

“1”

“0”

ID1S

NMI

Wake-up

Controller

WKUP (0:15)

EEPROM/Flash

FEIEN

INT 4 pin*

INT 5 pin*

INT 1 pin*

TEA1

TEC0

TEC1

Page 81

81/320

ST92F120 - INTERRUPTS

5.7 TOP LEVEL INTERRUPT

The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to thestatus of the control bit EIVR.TLIS (R246.2, Page 0). If thisbit is high (the reset condition)the sourceis the external pin NMI. If it is low, the source is the Timer/ Watchdog End Of Count. When the source is the NMI external pin, the control bit EIVR.TLTEV (R246.3; Page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. When the selected event occurs, the CICR.TLIP bit (R230.6) is set. Depending on the mask situation, a Top Level Interrupt request may be generated. Two kinds of masks are available, a Maskable mask and a Non-Maskable mask. The first mask is the CICR.TLI bit (R230.5): it can be set or cleared to enable or disable respectively the Top Level Interrupt request. If it is enabled, the global Enable Interrupt bit, CICR.IEN (R230.4) must also be enabled in order to allow a Top Level Request.

The second mask NICR.TLNM (R247.7) is a setonly mask. Once set, it enables the Top Level Interrupt request independently of the value of CICR.IEN and it cannot be cleared by the program. Only the processor RESET cycle can clear this bit. This does not prevent the user from ignoring some sources due to a change in TLIS.

The Top Level Interrupt Service Routine cannot be interrupted by any other interrupt orDMA request, in any arbitration mode, not even by a subsequent Top Level Interrupt request.

Warning. The interrupt machine cycle of the Top Level Interrupt does not clear the CICR.IEN bit, and the corresponding iret does not set it. Furthermore the TLI never modifies the CPL bits and the NICR register.

5.8 ON-CHIPPERIPHERAL INTERRUPTS

The general structure of the peripheral interrupt unit is described here, however each on-chip peripheral has its own specific interrupt unit containing one or more interrupt channels, or DMA channels. Please refer to the specific peripheral chapter for the description of its interrupt features and control registers.

The on-chip peripheral interrupt channels provide the following control bits:

– Interrupt Pending bit (IP). Set by hardware

when the Trigger Event occurs. Can be set/ cleared by software to generate/cancel pending interrupts and give the status for Interrupt polling.

– Interrupt Mask bit (IM). If IM = “0”, no interrupt

request is generated. If IM =“1” an interrupt request is generated whenever IP = “1” and CICR.IEN = “1”.

– Priority Level (PRL, 3 bits). These bits define

the current priority level, PRL=0: the highest priority, PRL=7: the lowest priority (the interrupt cannot be acknowledged)

– Interrupt Vector Register (IVR, up to 7 bits).

The IVR points to the vector table which itself contains the interrupt routine start address.

Figure 40. Top Level Interrupt Structure

WATCHDOG ENABLE

WDGEN

WATCHDOG TIMER

END OF COUNT

NMI OR

TLTEV

MUX

TLIS

TLIP

TLNM

TLI

IEN

PENDING

MASK

TOP LEVEL

INTERRUPT

VA00294

CORE

RESET

REQUEST

Page 82

82/320

ST92F120 - INTERRUPTS

5.9 INTERRUPT RESPONSE TIME

The interrupt arbitration protocol functions completely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles.

If the interrupt request comes from an external pin, the trigger event must occur a minimum of one INTCLK cycle before the sampling time.

When an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immediately and the interrupt request is serviced; if not, the CPU waits until the current instruction is terminated and then services the request. Instruction execution can normally be aborted provided no write operation has been performed.

For an interruptderiving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cyclesto a maximum of 55 clock cycles (DIV instruction), 53 clock

cycles (DIVWS and MUL instructions) or 49 for other instructions.

For a non-maskable Top Level interrupt, the response time between a user event and the start of the interrupt service routine can range from a minimum of 22 clock cycles to a maximum of 51 clock cycles (DIV instruction), 49 clock cycles (DIVWS and MUL instructions) or 45 for other instructions.

In order to guarantee edge detection, input signals must be kept low/high for a minimum of one INTCLK cycle.

An interrupt machine cycle requires a basic 18 internal clock cycles (CPUCLK), to which must be added a further 2 clock cycles if the stack is in the Register File. 2 more clock cycles must further be added if the CSR is pushed (ENCSR =1).

The interrupt machine cycle duration forms part of the two examples of interrupt response time previously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling.

In Wait for Interrupt mode, a further cycle is required as wake-up delay.

Page 83

83/320

ST92F120 - INTERRUPTS

5.10 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER

(CICR)

R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h)

Bit 7 = GCEN:

Global Counter Enable.

This bit enables the 16-bit Multifunction Timer peripheral. 0: MFT disabled 1: MFT enabled

Bit 6 = TLIP:

Top Level Interrupt Pending

. This bit is set by hardware when Top Level Interrupt (TLI) trigger event occurs. It is cleared by hardware when a TLI is acknowledged. It can also be set by softwareto implement a software TLI. 0: No TLI pending 1: TLI pending

Bit 5 = TLI:

Top Level Interrupt.

This bit is set and cleared by software. 0: A Top Level Interrupt is generared when TLIP is

set, only if TLNM=1 in the NICR register (independently of the value of the IEN bit).

1: ATopLevel Interrupt request isgenerated when

IEN=1 and the TLIP bit are set.

Bit 4 = IEN:

Interrupt Enable

. This bit is cleared by the interrupt machine cycle (except for a TLI). It isset by the iret instruction (except for a return from TLI). It is set by the EI instruction. It is cleared by the DI instruction. 0: Maskable interrupts disabled 1: Maskable Interrupts enabled

Note: The IEN bit can also be changed by software using any instruction that operates on register CICR, however in this case, take care toavoid spurious interrupts,sinceIEN cannot be cleared in the middle of an interrupt arbitration. Only modify

the IEN bit when interrupts are disabled or when no peripheral can generate interrupts. For example, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequence DI; POP CICR to make sure that no interrupts are being arbitrated when CICR is modified.

Bit 3 = IAM:

Interrupt Arbitration Mode

. This bit is set and cleared by software. 0: Concurrent Mode 1: Nested Mode

Bit 2:0 = CPL[2:0]:

Current Priority Level

. These bits define the Current Priority Level. CPL=0 is the highest priority. CPL=7 is the lowest priority. These bits maybe modified directly by the interrupt hardware when Nested Interrupt Mode is used.

EXTERNAL INTERRUPT TRIGGER REGISTER (EITR)

R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = TED1:

INTD1 Trigger Event

Bit 6 = TED0:

INTD0 Trigger Event

Bit 5 = TEC1:

INTC1 Trigger Event

Bit 4 = TEC0:

INTC0 Trigger Event

Bit 3 = TEB1:

INTB1 Trigger Event

Bit 2 = TEB0:

INTB0 Trigger Event

Bit 1 = TEA1:

INTA1 Trigger Event

Bit 0 = TEA0:

INTA0 Trigger Event

These bits are set and cleared by software. 0: Select falling edge as interrupt trigger event 1: Select rising edge as interrupt trigger event

GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0

TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

Page 84

84/320

ST92F120 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER

(EIPR)

R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = IPD1:

INTD1 Interrupt Pending bit

Bit 6 = IPD0:

INTD0 Interrupt Pending bit

Bit 5 = IPC1:

INTC1 Interrupt Pending bit

Bit 4 = IPC0:

INTC0 Interrupt Pending bit

Bit 3 = IPB1:

INTB1 Interrupt Pending bit

Bit 2 = IPB0:

INTB0 Interrupt Pending bit

Bit 1 = IPA1:

INTA1 Interrupt Pending bit

Bit 0 = IPA0:

INTA0 Interrupt Pending bit

These bits are set by hardware on occurrence of a trigger event (as specified in the EITR register) and are cleared by hardware on interrupt acknowledge. They can also be set by software to implement a software interrupt. 0: No interrupt pending 1: Interrupt pending

EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR)

R244 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = IMD1:

INTD1 Interrupt Mask

Bit 6 = IMD0:

INTD0 Interrupt Mask

Bit 5 = IMC1:

INTC1 Interrupt Mask

Bit 4 = IMC0:

INTC0 Interrupt Mask

Bit 3 = IMB1:

INTB1 Interrupt Mask

Bit 2 = IMB0:

INTB0 Interrupt Mask

Bit 1 = IMA1:

INTA1 Interrupt Mask

Bit 0 = IMA0:

INTA0 Interrupt Mask

These bits are set and cleared by software. 0: Interrupt masked 1: Interruptnotmasked (aninterruptisgenerated if

the IPxx and IEN bits = 1)

EXTERNAL INTERRUPT PRIORITY LEVEL REGISTER (EIPLR)

R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh)

Bit 7:6 = PL2D, PL1D:

INTD0, D1 Priority Level.

Bit 5:4 = PL2C, PL1C:

INTC0, C1 Priority Level.

Bit 3:2 = PL2B, PL1B:

INTB0, B1 Priority Level.

Bit 1:0 = PL2A, PL1A:

INTA0, A1 Priority Level.

These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by

hardware at 0 for Channels A0, B0, C0and D0 and at 1 for Channels A1, B1, C1 and D1.

IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0

IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0

PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A

PL2x PL1x

Hardware

bit

Priority

0 1

0 (Highest) 1

0 1

2 3

0 1

4 5

0 1

6 7 (Lowest)

Page 85

85/320

ST92F120 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER

(EIVR)

R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h)

Bit 7:4 = V[7:4]:

Most significant nibble of External

Interrupt Vector

. These bits are not initialized by reset. For a representation of how the full vector is generated from V[7:4] and the selected external interrupt channel, refer to Figure 39.

Bit 3 = TLTEV:

Top Level Trigger Event bit.

This bit is set and cleared by software. 0: Select falling edge as NMI trigger event 1: Select rising edge as NMI triggerevent

Bit 2 = TLIS:

Top Level Input Selection

. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source

Bit 1 = IA0S:

Interrupt Channel A0 Selection.

This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source

Bit 0 = EWEN:

External Wait Enable.

This bit is set and cleared by software.

0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external

memory access cycle).

Note: For more details on Wait mode refer to the section describing the WAITN pin in the External Memory Chapter.

NESTED INTERRUPT CONTROL (NICR)

R247 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h)

Bit 7 = TLNM:

Top Level Not Maskable

. This bit is set by software and cleared only by a hardware reset. 0: Top Level Interrupt Maskable. A top level re-

quest is generated if the IEN, TLI and TLIP bits =1

1: Top Level Interrupt Not Maskable. A top level

request is generated if the TLIP bit =1

Bit 6:0 = HL[6:0]:

Hold Level

x These bits are set by hardware when, in Nested Mode, an interrupt service routine at level x is interrupted from a request with higher priority (other than the Top Level interrupt request). They are cleared by hardware at the iret execution when the routine at level x is recovered.

V7 V6 V5 V4 TLTEV TLIS IAOS EWEN

TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0

Page 86

86/320

ST92F120 - INTERRUPTS

5.11 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)

5.11.1 Introduction

The Wake-up/Interrupt Management Unit extends the number of external interrupt lines from 8 to 23 (depending on the number of external interrupt lines mappedon external pins of the device). It allows the source of the INTD1 external interrupt channel to be selected between the INT7 pin (when available) and up to 16 additional external Wake-up/interrupt pins.

These 16 WKUP pins can be programmed as external interrupt lines or as wake-up lines, able to exit the microcontroller from low power mode (STOP mode) (see Figure 41).

5.11.2 Main Features

■ Supports up to 16 additional external wake-up

or interrupt lines

■ Wake-Up lines can be used to wake-up the ST9

from STOP mode.

■ Programmable selection of wake-up or interrupt

■ Programmable wake-up trigger edge polarity

■ All Wake-Up Lines maskable

Note: The number of available pins is device dependent. Refer to the device pinout description.

Figure 41. Wake-Up Lines / Interrupt Management Unit Block Diagram

WUTRH

WUTRL

WUPRH

WUPRL

WUMRH

WUMRL

TRIGGERING LEVEL REGISTERS

PENDING REQUEST REGISTERS

MASK REGISTERS

WKUP[7:0]

WKUP[15:8]

Set

NMI

WUCTRL

SW SETTING

WKUP-INT

ID1S

STOP

TO CPU

Reset

TO RCCU - Stop Mode Control

TO CPU

INTD1 - External Interrupt Channel

INT7

Note 1: The reset signal on the Stop bit is stronger than the set signal.

Page 87

87/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.11.3 Functional Description

5.11.3.1 Interrupt Mode

To configure the 16 wake-up lines as interrupt sources, use the following procedure:

1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH)

2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH)

3. Set bit 7 of EIMR (R244 Page 0) and EITR (R242 Page 0) registers of the CPU: so an interrupt coming from one of the 16 lines can be correctly acknowledged

4. Reset the WKUP-INT bit in the WUCTRL register to disable Wake-up Mode

5. Set the ID1S bit in the WUCTRL register to disable the INT7 external interrupt source and enable the 16 wake-up lines as external interrupt source lines.

To return to standard mode (INT7 external interrupt source enabled and 16 wake-up lines disabled) it is sufficient to reset the ID1S bit.

5.11.3.2 Wake-up Mode Selection

To configure the 16 lines as wake-up sources, use the following procedure:

1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH).

2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH).

3. Set, as for Interrupt Mode selection, bit 7 of EIMR and EITR registers only if an interrupt routine is to be executedafter a wake-up event. Otherwise, if the wake-up event only restarts the execution of the code from where it was stopped, the INTD1 interrupt channel must be masked or the external source must be selected by resetting the ID1S bit.

4. Since the RCCU can generate an interrupt request when exiting from STOP mode, take care to mask it even if the wake-up event is only to restart codeexecution.

5. Set the WKUP-INT bit in the WUCTRL register to select Wake-up Mode

6. Set the ID1S bit in the WUCTRL register to dis-

able the INT7 external interrupt source and enable the 16 wake-up lines as external interrupt source lines. This is not mandatory if the wake-up event does not require an interrupt response.

7.Write the sequence 1,0,1 to the STOP bit of the WUCTRL register with three consecutive write operations. This is the STOP bit setting sequence.

To detect if STOP Mode was entered or not, immediately after the STOP bit setting sequence, poll the RCCU EX_STP bit (R242.7, Page 55) and the STOP bit itself.

5.11.3.3 STOP Mode Entry Conditions

Assuming the ST9 is in Run mode: during the STOP bit setting sequence the following cases may occur:

Case 1: NMI = 0, wrong STOP bit setting sequence

This can happen if an Interrupt/DMA request is acknowledged during the STOP bit setting sequence. In this case polling the STOP and EX_STP bits will give:

STOP = 0, EX_STP = 0 This means that the ST9 did not enter STOP mode

due to a bad STOP bit setting sequence: the user must retry the sequence.

Case 2: NMI = 0, correct STOP bit setting sequence

In this case theST9 enters STOP mode. There are two ways to exit STOP mode:

1.A wake-up interrupt (not an NMI interrupt) is acknowledged. That implies:

STOP = 0, EX_STP = 1

This means that the ST9 entered and exited STOP mode due to an external wake-up line event.

2.A NMI rising edge woke up the ST9. This implies:

STOP = 1, EX_STP = 1

This means that the ST9 entered and exited STOP mode due to an NMI (rising edge) event. The user should clear the STOP bit via software.

Page 88

88/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) Case 3: NMI = 1 (NMI kept high during the 3rd

write instruction of the sequence), bad STOP bit setting sequence

The result is the same as Case 1:

STOP = 0, EX_STP = 0

This means that the ST9 did not enter STOP mode due to a bad STOP bit setting sequence: the user must retry the sequence.

Case 4: NMI = 1 (NMI kept high during the 3rd write instruction of the sequence), correct STOP bit setting sequence

In this case:

STOP = 1, EX_STP = 0

This means that the ST9 did not enter STOP mode due to NMIbeing kept high. The user should clear the STOP bit via software.

Note: If NMI goes to 0 before resetting the STOP bit, the ST9 will not enter STOP mode.

Case 5: A rising edge on the NMI pin occurs during the STOP bit setting sequence.

The NMI interrupt will be acknowledged and the ST9 will not enter STOP mode. This implies:

STOP = 0, EX_STP = 0

This means that the ST9 did not enter STOP mode due to an NMI interrupt serviced during the STOP bit setting sequence. At the endof NMI routine, the user must re-enter the sequence: if NMI is still high at the end of the sequence, the ST9 can not enter STOP mode (See “NMI Pin Management” on page 89.).

Case 6: A wake-up event on the external wakeup lines occurs during the STOP bit setting sequence

There are two possible cases:

1. Interrupt requests to the CPU are disabled: in this case the ST9 will not enter STOP mode, no interrupt service routine will be executed and the program execution continues from the instruction following the STOP bit setting sequence. The status of STOP and EX_STP bits will be again:

STOP = 0, EX_STP = 0

The application can determine why the ST9 did not enter STOP mode by polling the pending bits ofthe external lines (at least one must be at

1).

2.Interrupt requests to CPU are enabled: in this case the ST9 will not enter STOP mode and the interrupt service routine will be executed. The status of STOP and EX_STP bits will be again:

STOP = 0, EX_STP = 0

The interrupt service routine can determine why the ST9 did not enter STOP mode by polling the pending bits of the external lines (at least one must be at 1).

If the MCU really exits from STOP Mode, the RCCU EX_STP bit is still set and must be reset by software. Otherwise, if NMI was high or an Interrupt/DMA request was acknowledged during the STOP bit setting sequence, the RCCU EX_STP bit is reset. This means that the MCU has filtered the STOP Mode entry request.

The WKUP-INT bit can be used by an interrupt routine to detect and to distinguish events coming from Interrupt Modeor from Wake-up Mode, allowing the code to execute different procedures.

To exit STOP mode, it is sufficient that one of the 16 wake-up lines (not masked) generates an event: the clock restartsafter the delay needed for the oscillator to restart.

The same effect is obtained when a rising edge is detected on the NMI pin, which works as a 17th wake-up line.

Note: After exiting from STOP Mode, the software can successfully reset the pending bits (edge sensitive), even though the corresponding wake-up line is still active (high or low, depending on the Trigger Event register programming); the user must poll the external pin status to detect and distinguish ashort event from a long one (for example keyboard input with keystrokes of varying length).

Page 89

89/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.11.3.4 NMI Pin Management

On the CPU side, if TLTEV=1 (Top Level Trigger Event, bit 3 of register R246, page 0) then a rising edge ontheNMI pinwill setthe TLIP bit(Top Level Interrupt Pending bit, R230.6). At this point an interrupt request to the CPU is given either if TLNM=1 (Top Level Not Maskable bit, R247.7 - once set it can only be cleared by RESET) or if TLI=1 and IEN=1 (bits R230.5, R230.4).

Assuming that the application uses a non-maskable Top Level Interrupt (TLNM=1): in this case, whenever a rising edge occurs on the NMI pin, the related serviceroutine willbe executed. To service further Top Level Interrupt Requests, it is necessary to generate a new rising edge on the external NMI pin.

The following summarizes some typical cases: – If the ST9 is in STOP mode and a rising edge on

the NMI pin occurs, the ST9 will exit STOP mode and the NMI service routine will be executed.

– If the ST9 is in Run mode and a rising edge oc-

curs on the NMI pin: the NMI service routine is executed and then the ST9 restarts the execution of the main program. Now, suppose that

the userwants to enterSTOP mode with NMI still at 1. The ST9 will not enter STOP mode and it will not execute an NMI routine because therewereno transitions onthe external NMI line.

– If the ST9 is in run mode and a rising edge on

NMI pin occurs during the STOP bit setting sequence: the NMI interrupt will be acknowledged and the ST9 will not enter STOP mode. At the end of the NMI routine, the user must re-enter the sequence:if NMIis still high at theend ofthe sequence, the ST9 can not enter STOP mode (see previous case).

– If the ST9 is in run mode and the NMIpin is high:

if NMI is forced low just before the third write instruction of the STOP bit setting sequence then the ST9 will enter STOP mode.

Page 90

90/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.11.4 Programming Considerations

The following paragraphs give some guidelines for designing an application program.

5.11.4.1 Procedure for Entering/Exiting STOP mode

1. Program the polarity of the trigger event of external wake-up lines by writing registers WUTRH and WUTRL.

2. Check that at least one mask bit (registers WUMRH, WUMRL) is equal to 1 (so at least one external wake-up line is not masked).

3. Reset at least the unmasked pending bits: this allows a rising edge to be generated on the INTD1 channel when the trigger event occurs (an interrupt on channel INTD1 is recognized when a rising edge occurs).

4. Select the interrupt source of the INTD1 channel (see description of ID1S bit in the WUCTRL register) and set the WKUP-INT bit.

5. To generate an interrupt on channel INTD1,bits EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7, Page 0) must be set and bit EIPR.7 must be reset. Bits 7 and 6 of register R245, Page 0 must be written with the desired priority level for interrupt channel INTD1.

6. Reset the STOP bit in register WUCTRL and the EX_STP bit in the CLK_FLAG register (R242.7, Page 55). Refer to the RCCU chapter.

7. To enter STOP mode, write the sequence 1, 0, 1 to the STOP bit in the WUCTRL register with three consecutive write operations.

8. The code to be executed just after the STOP sequence must check the status of the STOP and RCCU EX_STP bits to determine if the ST9 entered STOP mode or not (See “Wake-up Mode Selection” on page 87. for details). If the ST9 did not enter in STOP mode it is necessary to reloop the procedure from the beginning, otherwise the procedure continues from next point.

9.Poll the wake-up pending bits to determine which wake-up line caused the exit from STOP mode.

10.Clear the wake-up pending bit that was set.

5.11.4.2 SimultaneousSetting of Pending Bits

It is possible that several simultaneous events set different pending bits. In order to accept subsequent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this operation allows a rising edge to be generated on the INTD1 line (if there is at least one more pending bit set and not masked) and so to set EIPR.7 bit again. A further interrupt on channel INTD1 will be serviced depending on the status of bit EIMR.7. Two possible situations may arise:

1.The user chooses to reset all pending bits: no further interrupt requests will be generated on channel INTD1. In this case the user has to:

– Reset EIMR.7bit (to avoid generating aspuri-

ous interrupt request during the next reset operation on the WUPRH register)

– Reset WUPRH register using a read-modify-

write instruction(AND, BRES, BAND) – Clear the EIPR.7 bit – Reset the WUPRL register using a read-mod-

ify-write instruction (AND, BRES, BAND)

2.The user chooses to keep at least one pending bit active: at least one additional interrupt request will be generated on the INTD1 channel. In this case the user has to reset the desired pending bits with a read-modify-write instruction (AND, BRES, BAND). This operation will generate a rising edge on the INTD1 channel and the EIPR.7 bit will be set again. An interrupt on the INTD1 channel will be serviced depending on the status of EIMR.7 bit.

Page 91

91/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.11.5 Register Description WAKE-UP CONTROL REGISTER (WUCTRL)

R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 2 = STOP:

Stop bit.

To enter STOP Mode, write the sequence 1,0,1 to this bit with three consecutive write operations. When a correct sequence is recognized, the STOP bit is set and the RCCU puts the MCU in STOP Mode. The software sequence succeeds only if the following conditions are true:

– The NMI pin is kept low, – The WKUP-INT bit is 1, – All unmasked pending bits are reset – At least one mask bit is equal to 1 (at least one

external wake-up line is not masked).

Otherwise the MCU cannot enter STOP mode, the program code continues executing and the STOP bit remains cleared.

The bit is reset by hardware if, while the MCU is in STOP mode, a wake-up interrupt comes from any of the unmasked wake-up lines. The bit is kept high if, during STOP mode, a rising edge on NMI pin wakes up the ST9. In this case the user should reset itbysoftware.The STOP bit is at 1 in the four following cases (See “Wake-up Mode Selection” on page 87. for details):

– After the first write instruction of the sequence (a

1 is written to the STOP bit)

– At the end of a successful sequence (i.e. after

the third write instruction of the sequence)

– The ST9 entered and exited STOP mode due to

a rising edge on the NMI pin. In this case the EX_STP bit in the CLK_FLAG is at 1 (see RCCU chapter).

– The ST9 did not enter STOP mode due to the

NMI pin being kepthigh. In this case RCCU bit EX_STP is at 0

Note: The STOP request generated by the WUIMU (that allows the ST9 to enter STOP mode) is ORed with the external STOP pin (active low). This means that if theexternal STOPpin is forced

low, the ST9 will enter STOP mode independently of the status of the STOP bit.

WARNINGS: – Writing the sequence 1,0,1 to the STOP bit will

enter STOP mode only if no other register write instructions are executedduringthe sequence.If Interrupt orDMA requests(whichalwaysperform register write operations) are acknowledged during the sequence, the ST9 will not enter STOP mode: the user must re-enter the sequence to set the STOP bit.

– WheneveraSTOPrequest isissued to theMCU,

a few clock cycles are needed to enter STOP mode (see RCCU chapter for further details). Hence the execution of the instruction following the STOP bitsettingsequencemight start before entering STOP mode: if such instruction performs a register write operation, the ST9 will not enter in STOP mode. In order toavoidto execute register write instructions after a correct STOP bit setting sequenceand before entering the STOP mode, it is mandatory to execute 3 NOP instructions after the STOP bit setting sequence.

Bit 1 = ID1S:

Interrupt Channel INTD1 Source.

This bit is set and cleared by software. 0: INT7 external interrupt source selected, exclud-

ing wake-up line interrupt requests

1: The 16 external wake-up lines enabled as inter-

rupt sources, replacing the INT7 external pin function

WARNING: To avoid spurious interrupt requests on the INTD1 channel due to changing the interrupt source, use this procedure to modify the ID1S bit:

1.Mask the INTD1 interrupt channel (bit 7 of register EIMR - R244, Page 0 - reset to 0).

2. Program the ID1S bit as needed.

3.Clear the IPD1 interrupt pending bit (bit 7 of register EIPR - R243, Page 0)

4.Remove the mask on INTD1 (bit EIMR.7=1).

Bit 0 = WKUP-INT:

Wakeup Interrupt.

This bit is set and cleared by software. 0: The 16 external wakeup lines can be used to

generate interrupt requests

1: The 16 external wake-up lines to work as wake-

up sources for exiting from STOP mode

-----STOPID1S WKUP-INT

Page 92

92/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH)

R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUM[15:8]:

Wake-Up Maskbits.

If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the corresponding WUPx pending bit is set. More precisely, if WUMx=1 and WUPx=1 then:

– If ID1S=1and WKUP-INT=1then an interrupton

channel INTD1 and a wake-up event are generated.

– If ID1S=1and WKUP-INT=0 onlyaninterrupt on

channel INTD1 is generated.

– If ID1S=0 and WKUP-INT=1 only a wake-up

event is generated.

– If ID1S=0 and WKUP-INT=0 neither interrupts

on channel INTD1 nor wake-up events are generated.Interruptrequests onchannel INTD1 may be generated only from external interrupt source INT7.

If WUMx is reset, no wake-up events can be generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0).

WAKE-UP MASK REGISTER LOW (WUMRL) R251 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUM[7:0]:

Wake-Up Mask bits.

– If ID1S=1and WKUP-INT=1 then an interrupt on

channel INTD1 and a wake-up event are generated.

– If ID1S=1and WKUP-INT=0onlyan interrupt on

channel INTD1 is generated.

– If ID1S=0 and WKUP-INT=1 only a wake-up

event is generated.

– If ID1S=0 and WKUP-INT=0 neither interrupts

on channel INTD1 nor wake-up events are generated. Interruptrequests onchannel INTD1may be generated only from external interruptsource INT7.

If WUMx is reset, no wake-up events can be generated. Interrupt requests on channel INTD1 may be generated only from external interrupt source INT7 (resetting ID1S bit to 0).

WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8

WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0

Page 93

93/320

ST92F120 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER HIGH

(WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUT[15:8]:

Wake-Up Trigger Polarity

Bits

These bits are set and cleared bysoftware. 0: The corresponding WUPxpending bit willbeset

on the falling edge of the input wake-up line .

1: The corresponding WUPxpending bit willbeset

on the rising edge of the input wake-up line.

WAKE-UP TRIGGER REGISTER LOW (WUTRL) R253 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0= WUT[7:0]:

Wake-Up Trigger Polarity Bits

These bits are set and cleared bysoftware. 0: The corresponding WUPxpending bit willbeset

on the falling edge of the input wake-up line.

1: The corresponding WUPxpending bit willbeset

on the rising edge of the input wake-up line.

WARNING

1. As the external wake-up lines are edge triggered, no glitches must be generated on these lines.

2. If either a risingor a falling edgeon the external wake-up lines occurs while writing the WUTRLH or WUTRL registers, the pending bit will not be set.

WAKE-UP PENDING REGISTER HIGH

(WUPRH) R254 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUP[15:8]:

Wake-Up Pending Bits

These bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. They must be cleared by software. They can be set by software to implement a software interrupt. 0: No Wake-up Trigger event occurred 1: Wake-up Trigger event occured

WAKE-UP PENDING REGISTER LOW (WUPRL) R255 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h)

Bit 7:0 = WUP[7:0]:

Wake-Up Pending Bits

Note: To avoid losing a trigger event while clearing the pending bits, it is recommended to use read-modify-write instructions (AND, BRES, BAND) to clear them.

WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8

WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0

WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8

WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0

Page 94

94/320

ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6 ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.1 INTRODUCTION

The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is fully supported by peripherals having their own controller and DMA channel(s). Each DMA channel transfers data to or from contiguouslocations intheRegisterFile, or in Memory. The maximum number of bytes that can be transferred per transaction by each DMA channel is 222 with the Register File, or 65536 with Memory.

The DMA controller in the Peripheral uses an indirect addressing mechanism to DMA Pointers and Counter Registers stored in the Register File. This is the reason why the maximum number of transactions for the Register File is 222, since two Registers are allocated for the Pointer and Counter. Register pairs are used for memory pointers and counters in order to offer the full 65536 byte and count capability.

6.2 DMA PRIORITY LEVELS

The 8 priority levels used for interrupts are also used to prioritize the DMA requests, which are arbitrated in the same arbitration phase as interrupt requests. If the event occurrence requires a DMA transaction, this will take place at the end of the current instruction execution. When an interrupt and a DMA request occur simultaneously, on the same priority level, the DMA request is serviced before the interrupt.

An interrupt priority request must be strictlyhigher than the CPL value in order to be acknowledged, whereas, for a DMA transaction request, it must be equal to or higher than the CPL value in order to be executed. Thus only DMA transaction requests can be acknowledged when the CPL=0.

DMA requests do not modify the CPL value, since the DMA transaction is not interruptable.

Figure 42. DMA Data Transfer

PERIPHERAL

VR001834

DATA

ADDRESS

COUNTER

TRANSFERRED

MEMORY

START ADDRESS

COUNTER VALUE

DATA

GROUP F PERIPHERAL PAGED REGISTERS

Page 95

95/320

ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.3 DMA TRANSACTIONS

The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations:

– A load from/to the peripheral data register to/

from a location of Register File (or Memory) addressed through the DMA Address Register (or Register pair)

– A post-increment of the DMA Address Register

(or Register pair)

– A post-decrement of the DMA transaction coun-

ter, which contains the number of transactions that have still to be performed.

If the DMA transaction is carried out between the peripheral and the Register File (Figure 43), one register is required to hold the DMA Address, and one to hold the DMA transaction counter. These two registers must be located in the Register File: the DMA Address Register in the even address

register, and the DMA Transaction Counter in the next register (odd address). They are pointed to by the DMA Transaction Counter Pointer Register (DCPR), located in the peripheral’s paged registers. In order to select a DMA transaction with the Register File, the control bit DCPR.RM (bit 0 of DCPR) must be set.

If the transaction is made between the peripheral and Memory, a register pair (16 bits) is required for the DMA Address and the DMA Transaction Counter (Figure 44). Thus, two register pairs must be located in the Register File.

The DMA Transaction Counter is pointed to by the DMA Transaction Counter Pointer Register (DCPR), the DMA Address is pointed to by the DMA Address Pointer Register (DAPR),both DCPR and DAPR are located in the paged registers of the peripheral.

Figure 43. DMA Between Register File and Peripheral

IDCR

IVR

DAPR

DCPR

DATA

PAGED

REGISTERS

SYSTEM

DMA

COUNTER

DMA

ADDRESS

FFh

F0h

E0h DFh

EFh

MEMORY

0000h

DATA

ALREADY

TRANSFERRED

END OF BLOCK

INTERRUPT

SERVICE ROUTINE

DMA

TABLE

DMA TRANSACTION

ISR ADDRESS

0100h

VECTOR

TABLE

PERIPHERAL

PAGED REGISTERS

Page 96

96/320

ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

DMA TRANSACTIONS (Cont’d)

When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared.

ToselectbetweenusingtheISRortheDMASRregister to extend the address, (see Memory Management Unit chapter), the control bit DAPR.PS (bit 0 of DAPR) must be cleared or set respectively.

The DMA transaction Counter must be initialized with the number of transactions to perform and will be decremented after each transaction. The DMA Address must be initialized with the starting address of the DMA table and is increased after each transaction. These two registers must be located between addresses 00h and DFh of the Register File.

Once a DMA channel is initialized, a transfer can start. The direction of the transfer is automatically defined by the type of peripheral and programming mode.

Once the DMA table is completed (the transaction counter reaches 0 value), an Interrupt request to the CPU is generated.

When the Interrupt Pending (IP) bit is set by a hardware event (or by software), and the DMA Mask bit (DM) is set, a DMA request is generated. If the Priority Level of the DMA source is higher than, or equalto, the Current PriorityLevel (CPL), the DMA transfer is executed at the end of the current instruction. DMA transfers read/write data from/to the location pointed to by the DMA Address Register, the DMA Address register is incremented and the Transaction Counter Register is decremented. When the contents of the Transaction Counter are decremented to zero, the DMA Mask bit (DM) is cleared and an interrupt request is generated, according to the Interrupt Mask bit (End of Block interrupt). This End-of-Block interrupt request is taken into account, depending on the PRL value.

WARNING. DMA requests are not acknowledged if the top level interrupt service is in progress.

Figure 44. DMA Between Memory and Peripheral

IDCR

IVR DAPR DCPR

DATA

PAGED

REGISTERS

SYSTEM

DMA

TRANSACTION

COUNTER

DMA

ADDRESS

FFh

F0h

E0h DFh

EFh

MEMORY

0000h

DATA

ALREADY

TRANSFERRED

END OF BLOCK

INTERRUPT

SERVICE ROUTINE

DMA

TABLE

DMA TRANSACTION

ISR ADDRESS

0100h

VECTOR

TABLE

PERIPHERAL

PAGED REGISTERS

Page 97

97/320

ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

DMA TRANSACTIONS (Cont’d)

6.4 DMA CYCLE TIME

The interrupt and DMA arbitration protocol functions completely asynchronously from instruction flow.

Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al-

lows it. A DMA transfer with the Register file requires 8

CPUCLK cycles. A DMA transfer with memory requires 16 CPUCLK

cycles, plus any required wait states.

6.5 SWAP MODE

An extra feature which may be found on the DMA channels of some peripherals (e.g. theMultiFunction Timer) is the Swap mode. This feature allows

transfer from two DMA tables alternatively. All the DMA descriptorsin the Register File are thus doubled. Two DMA transaction counters and two DMA address pointers allow the definition of twofully independent tables (they only have to belong to the same space, Register File or Memory). The DMA transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the DMA controller automatically swaps to the other table (table 1) by pointing to the other DMA descriptors.In this case,the DMA mask (DM bit) control bit is not cleared, but the End Of Block interrupt request is generated to allow the optional updating of the first data table (table 0).

Until the swap mode is disabled, the DMA controller will continue to swap between DMA Table 0 and DMA Table 1.

Page 98

98/320

ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.6 DMA REGISTERS

As each peripheral DMA channel has its own specific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may be different from those found in the peripheral chapters.

DMA COUNTER POINTER REGISTER (DCPR)

Read/Write Address set by Peripheral Reset value: undefined

Bit 7:1 = C[7:1]:

DMA Transaction Counter Point-

er.

Software should write the pointer to the DMA Transaction Counter in these bits.

Bit 0 = RM:

This bit is set and cleared by software. 0: DMA transactions are with memory (see also

DAPR.DP)

1: DMA transactions are with the Register File

GENERIC EXTERNAL PERIPHERAL INTERRUPT AND DMA CONTROL (IDCR)

Read/Write Address set by Peripheral Reset value: undefined

Bit 5 = IP:

Interrupt Pending

This bit is set by hardware when the TriggerEvent occurs. It iscleared by hardware when the request is acknowledged.It can beset/cleared by software in order to generate/cancel a pending request. 0: No interrupt pending 1: Interrupt pending

Bit 4 = DM:

DMA Request Mask

This bit is set and cleared by software. It is also cleared when the transaction counter reaches zero (unless SWAP mode is active). 0: No DMA request is generated when IP is set. 1: DMA request is generated when IP is set

Bit 3 = IM:

End of block Interrupt Mask

. This bit is set and cleared by software. 0: No End of block interrupt request is generated

when IP is set

1: End of Block interrupt is generated when IP is

set. DMA requests depend on the DM bit value as shown in the table below.

Bit 2:0 = PRL[2:0]:

Source Priority Level

. These bits are set and cleared by software. Refer to Section 6.2 DMA PRIORITY LEVELS for a description of priority levels.

DMA ADDRESS POINTER REGISTER (DAPR)

Read/Write Address set by Peripheral Reset value: undefined

Bit 7:1 = A[7:1]:

DMA Address Register(s) Pointer

Software should write the pointer to the DMA Address Register(s) in these bits.

Bit 0 = PS:

Memory Segment Pointer Selector

: This bit is set and cleared by software. It is only meaningful if DAPR.RM=0. 0: The ISR register is used to extend the address

of data transferred by DMA (see MMUchapter).

1: The DMASR register is used to extend the ad-

dress of data transferred by DMA (see MMU chapter).

C7 C6 C5 C4 C3 C2 C1 RM

IP DM IM PRL2 PRL1 PRL0

DM IM Meaning

A DMA requestgenerated withoutEnd of Block interrupt when IP=1

A DMA request generated with End ofBlock interrupt when IP=1

No End of block interrupt or DMA request is generated when IP=1

An End of block Interrupt is generated without associated DMA request (not used)

PRL2 PRL1 PRL0 Source Priority Level

0000Highest 0011 0102 0113 1004 1015 1106 1117Lowest

A7 A6 A5 A4 A3 A2 A1 PS

Page 99

99/320

ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

7 RESET AND CLOCK CONTROL UNIT (RCCU)

7.1 INTRODUCTION

The Reset and Clock Control Unit (RCCU) comprises two distinct sections:

– the Clock Control Unit, which generates and

manages the internal clock signals.

– the Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog generated resets.

On ST9 devices where the external Stop pin is available, this circuit also detects and manages the externally triggered Stop mode, during which all oscillators are frozen in order to achieve the lowest possible power consumption.

7.2 CLOCK CONTROL UNIT

The Clock Control Unit generates the internal clocks for the CPU core (CPUCLK) and for the onchip peripherals (INTCLK). The Clock Control Unit may be driven by an external crystal circuit, connected to the OSCIN and OSCOUT pins, or by an external pulse generator, connected to OSCIN (see Figure 51andFigure 53). A low frequency external clock may be connected to theCK_AF pin, and this clock source may be selected when low power operation is required.

7.2.1 Clock Control Unit Overview

As shown in Figure 45 a programmable divider can divide the CLOCK1 input clock signal by two. In practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the PLL multiplier circuit. The resulting signal,

CLOCK2, is the reference input clock to the programmable Phase Locked Loop frequency multiplier, which is capable of multiplying the clock frequency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a programmable divider, by a factor of 1 to 7. By this means, the ST9 can operate with cheaper, medium frequency (3-5 MHz) crystals, while still providing a high frequency internal clock for maximum system performance; the range of available multiplication and division factors allow a great number of operating clock frequencies to be derived from a single crystal frequency.

For low power operation, especially in Wait for Interrupt mode, the Clock Multiplier unit may be turned off, whereupon the output clock signal may be programmed as CLOCK2 divided by 16. For further power reduction, a low frequency external clock connected to the CK_AF pin may be selected, whereupon the crystal controlled main oscillator may be turned off.

The internal system clock, INTCLK, is routed to all on-chip peripherals, as well as to the programmable Clock PrescalerUnit which generates the clock for the CPU core (CPUCLK). (See Figure 45)

The Clock Prescaler is programmable and can slow the CPU clock by afactor of up to 8, allowing the programmer to reduce CPU processing speed, and thus power consumption, while maintaining a high speed clock to the peripherals. This is particularly useful when little actual processing is being done by the CPU and the peripherals are doing most of the work.

Page 100

100/320

ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

Figure 45. ST92F120 Clock Distribution Diagram

Quartz

PLL

1/16

1/2

DIV2

1/ N

Oscillator

MX(1:0)

CSU_CKSEL

6/8/10/14

XT_DIV16

DX(2:0)

1/4

CK_128

0 1

RCCU

INTCLK

CLOCK2

STIM

1/4

8-bit Prescaler

16-bit Down

Counter

1...256

3-bit Prescaler

CPU

MFTx

1/3

8-bit Prescaler

16-bit Up/Down

Counter

1...256

TxINA/TxINB

(Max INTCLK/3)

EFTx

1/N

16-bit Up

Counter

EXTCLKx

(Max INTCLK/4)

N=2,4,8

Baud Rate

Generator

1/N

N=2...(2

-1)

SCIx

3-bit Prescaler

1...8

Baud Rate Generator

1/N

N=2,4,16,32

SCK

Master

SCK

Slave

(Max INTCLK/2)

SPI

LOGIC

JBLPD

CPUCLK

EMBEDDED MEMORY

RAM

EPROM

FLASH

EEPROM

I2C

STD

FAST

1/N

N=4,6,8...258

N=6,9,12...387

Fscl ≤100 kHz

Fscl ≤ 400 kHz

Fscl > 100 kHz

1...8

A/Dx

6-bit Prescaler

1...64

P6.5

1/2

1/16

P6.0

1/8

Conversion time

138 * INTCLK

P9.6

16-bit Down

Counter

1/4

WDG

8-bit Prescaler

1...256

J1850 Kernel

Datasheet ST92F120V9, ST92F120V9Q, ST92F120V6Q, ST92F120V1Q, ST92F120R9T Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual