The ST755 is an adjustable inverting switch-mode
DC-DC regulator with internal Power MOSFET
that generators an adjustable negative output
from a voltage input of 2.7V to 11V , output current
guaranteed at 200mA (for V
>4.5V,VO=-5Vand
I
ST755
DIP-8SO-8
T
= 0°C to 70°C) and 275mA (typical value at T
A
=25°C,VO=-5V).
A logic controlled shut down pin that interfaces
directly with microprocessor reduces supply
current to only 10mA. Input to Output differential
voltage is limited to V
supply current is 1. 2mA.
+|VO|<12.7V. No load
I
A
SCHEMATIC DIAGRAM
1/10June 2003
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ST755
ABSOLUTE MAXIMUM RATINGS
SymbolParameter²ValueUnit
V
V
SHDN
V
V
I
LX
P
TOT
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Note 1: The input to output differential voltage is limited to V
THERMAL DATA
SymbolParameterSO-8DIP-8Unit
R
thj-amb
(*) This value depends from thermal design of PCB on which the device is mounted.
DC Input Voltage to GND (Note1)
CC
-0.3 to 12V
Shutdown Voltage, SS Voltage, CC Voltage-0.3 to (VCC+ 0.3)
Switch Voltage (LX to VCC)
LX
Feedback Voltage (VOto GND)
FB
Peak Switch Current
Continuous Power Dissipation at TA= 70°C (DIP-8)
(SO-8)
Operating Junction Temperature Range (C series)-40 to 185°C
op
Storage Temperature Range
stg
+|VO|<12.7V
CC
Thermal Resistance Junction-ambient (*)
-12.5 to + 0.3V
-11 to + 0.9V
2A
725
470
-55 to +150°C
160100°C/W
V
mW
CONNECTION DIAGRAM (top view)
PIN DESCRIPTION
Pin N°SymbolName and Function
1SHDN
2V
REF
3SSSoft Start
4CCCompensation Input
5V
O
6GNDGround
7LXSwitch Output
8V
CC
SHUT-DOWN control (VCC= ON, GND = Shutdown)
Reference Output Voltage: (1.25V)
Negative Output Voltage
Supply Voltage Input.
ORDERING CODES
TYPEDIP8SO-8SO-8 (T&R)
ST755ST755CNST755CDST755CD-TR
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ST755
ELECTRICAL CHARACTERISTICS (Refer to the test circuits , VCC=5V,VO= -5.25 to -4.75V,
I
=0mA,TA=T
LOAD
SymbolParameterTest ConditionsMin.Typ.Max.Unit
VIInput Voltage411V
Output VoltageVCC= 4.5 to 6.2V IO=0 to 200mA4.7555.25V
V
O
Output CurrentVCC= 4.5 to 6.2V TA= 0 to 70°C200275mA
Do not overload or short the Output to Ground. If the above conditions are observed, the device may be damaged.
MIN
to T
, unless otherwise s pec ified. Typical value are referred at TA= 25°C)
MAX
= 4.5 to 6.2V TA= -40 to 85°C175
V
CC
=4VVO= -5V175
V
CC
V
= 2.7VVO= -5V125
CC
No LoadV
to T
MIN
=100mA68%
O
MAX
SHDN=VCC
=0V10100µA
SHDN
1.23.5mA
50ppm/°C
7.5KΩ
APPLICATION INFORMATION
The ST755 is a n IC developed for voltage conversion from an input volt age ranging from +2.4V to 11V to
a regulated adjustable negative output limite d by |V
| ≤ 12 .7V-VI. The circuit adopts a current-mode PWM
O
control scheme to achieve good efficiency, high stability and low noise performance. The figure in the first
page shown the detailed b lock diagram of the device.
ST755 is realized in a BCD technology in order to achieve high temperature stability, the best
REFERENCE precision, a very low quiescent current and jitter free operat ions. The f inal stage is built
around a 0.7Ω - 2 A P-Channel Power MOS. A f raction of the output curren t is splitted o ut for current
detection.Internal clock frequency is fixed to 160KHz. Error amplifier drives the PWM comparator in order
to keep 0V on the CC input. So R
V
)*R3(see fig 1). For R3can be choose any value between 2KΩ and 20KΩ. Soft-Start (SS) input is a
REF
and R4resistors are calculated by t he following formulae R4= (|VO|/
3
voltage dependent-output current limit (see figure 9, Switch Current Limit vs. SS Input V oltage). SS pin is
internally pulled to V
through a 1.2 MΩ resistor. Applying an appropriate capacitor at SS input is
REF
possible to obtain a s of t-start current imitation during power up. F orcing Soft -Start (SS) input to a lower
voltage through a resistive voltage driver (R
and R2), the maximum LX current limit can be lowered
1
according the diagram showed in figure 9. When SHDN input is l ow, the total current c ons umption is
reduced to 10µA.
APPLICATION CIRCUIT
To achieve the best performances from switch ing power supply topology, particular care to layout drawing
is needed, in order to minimize EMI and obtain low noise, jitter free operati on moreover, it ensures the full
device functionality. Layou t design proposed on demoboard (see pict ure 2) helps to lower the developing
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ST755
time. Wire lengths must be minimized, filter and by-pass capacitors C1,C2and C3must be low ESR type,
placed as close possible to the integrated circuit. The 10µH inductor m us t be chosen built on a core,
taking care that saturation c urrent should be higher than t he peak LX switch current. See the PEAK
INDUCTOR CURRENT vs. LOAD CURRENT graph (figure 6 ).
Figure1 : TYPICAL APPLICATION CIRCUIT
(*) R1 and R2 can be omitted for Iout<200mA.
(**) C6: Very low noise but poor transient and load response speed.
(***) C3 (alternative to C6): faster transient and load response.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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