Datasheet ST72311R, ST72511R, ST72532R Datasheet (ST)

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查询ST631K供应商

ST72311R, ST72511R, ST72532R

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,

16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

■ Memories

– 16K to 60K bytes Program memory

(ROM,OTP and EPROM) with read-out protection

– 256 bytes E

(only on ST72532R4)

– 1024 to 2048 bytes RAM

■ Clock, Re set and Supp ly M ana g e m ent

– Enhanced reset system – Low voltage supply supervisor – Clock sources: crystal/ceramic resonat or os-

cillator or ext er na l c loc k – Beep and Clock-out capability – 4 Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– Nested interrupt controller – 13 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) – TLI dedicated top level interrupt pin

■ 48 I/ O P o rts

– 48 multifunctional bidirectional I/O lines – 32 alternate function lines – 12 high sink outputs

■ 5 Timers

– Configurable watchdog timer – Real time clock timer – One 8-bit auto-reload timer with 4 independ-

ent PWM output channels, 2 output compares

and external clock with event detector (except

on ST725x2R4)

Device Summary

Features ST72T511R9 ST72T511R7 ST72T511R6 ST72T311R9 ST72T311R7 ST72T311R6 ST72T532R4

Program memory - bytes 60K 48K 32K 60K 48K 32K 16K RAM (stac k) - bytes 2048 (256) 1536 (256 ) 1024 (256) 2048 (256) 1536 (256) 1024 (25 6) 1024 (256) EEPROM - bytes - - -

Peripherals

Operati ng Supply 3.0V to 5.5V 3.0 to 5.5V CPU Frequency 2 to 8 MHz (with 4 to 16 MHz oscillator) 2 to 4 MHz Operati ng T em perature -40°C to +85°C (-40°C to +105/125°C optional)

Packages TQFP64

Note 1. See Section 12.3.1 on page 119 for more information on VDD versus f

PROM Data memory

Watchdog, two 16-bit timers, 8-bi t PWM ART,

SPI, SCI, CAN, ADC

TQFP64

14 x 14

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one timer, PWM and Pulse generator modes

■ 3 Communications Interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface – CAN interface (except on ST72311Rx)

■ 1 Analog peripheral

– 8-bit ADC with 8 input channels

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation

■ Development Tools

– Full hardware/software development package

---

Watchdog, two 16-bit timers, 8-bi t PWM ART,

SPI, SCI, ADC

OSC

Watchdog, two

16-bit timers,

SPI, SCI, CAN ,

256

ADC

Rev. 2.7

April 2003 1/152

Page 2

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

152

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8.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.5.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.6.4 LIN Protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.6.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

10.6.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.6.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 120

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.4.5 On-Chip Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

152

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Table of Contents

12.5.3 Crystal and Ceramic Resonator Osc illa tors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.6.2 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.6.3 EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.28-Bit PWM-ART Auto -Reload Time r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 135

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.11.3CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144

14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 145

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

14.3.1 Package/socket Footprint Propos al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

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Page 6

ST72311R, ST72511R, ST72532R

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72311R, ST72511R, and ST72532R devices are members of the ST7 microcontroller family. They can be grouped as follows:

– ST725xxR devices are designed for mid-range

applications with a CAN bus interface (Controller Area Network). These devices are available in OTP and EPROM versions only.

– ST72311R devices target the same range of ap-

plications but without the CAN interface. These devices are available in ROM, OTP and EPROM versions.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

RESET

TLI

OSC1 OSC2

PF7:0

(8-BIT)

CONTROL

LVD

OSC

MCC/RTC

PORT F

TIMER A

BEEP

Under software control, all devices can be p laced in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

PROGRAM

MEMORY

(16K - 60K By tes)

RAM

(1024, 2048 Bytes)

EEPROM

(256 Bytes)

ADDRESS AND DATA BUS

WATCHDOG

PORT A

PORT B

PWM ART

PA7:0

(8-BIT)

PB7:0

(8-BIT)

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PE7:0

(8-BIT)

PD7:0

(8-BIT)

DDA

SSA

PORT E

CAN

SCI

PORT D

8-BIT ADC

PORT C

TIMER B

SPI

PC7:0

(8-BIT)

Page 7

1.2 PIN DESCRIPTI ON Figure 2. 64-Pin TQFP Package Pinout

ST72311R, ST72511R, ST72532R

(HS) PE4 (HS) PE5 (HS) PE6

(HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3

ARTCLK / PB4

PB5 PB6

PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3

PE3 / CANRX

PE2 / CANTX

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PE1 / RDI

PE0 / TDO

OSC1

TLIncRESET

OSC2

PA7 (HS)

PA6 (HS)

2 3 4 5 6

ei2

ei0

8 9 10

ei3

11 12 13 14 15 16

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

SSA

DDA

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

ei1

MCO / PF0

PF2

BEEP / PF1

ICAP2_A / PF5

OCMP2_A / PF3

OCMP1_A / PF4

SS_3

DD_3

PA5 (HS)

PA4 (HS)

SS_1

DD_1

PA3

PA2

PA1

PA0

PC7 / SS

PC6 / SCK

PC5 / MOSI

PC4 / MISO

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B

PC0 / OCMP2_B

SS_0

DD_0

ICAP1_A / (HS) PF6

EXTCLK_A / (HS ) PF7

(HS) 20mA h igh sink capability eix associated external interrupt vector

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Page 8

ST72311R, ST72511R, ST72532R

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 12 "ELECTRICAL CHARACTERISTICS" on page

117.

Legend / Abbreviations for Table 1 :

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

– Output : OD = open drain Refer to Section 8 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configur at i on of each pin is shown in bold. This configuratio n is va li d as l o ng as the device is

in reset state.

Table 1. Device Pin Description

/0.7VDD,

, PP = push-pull

, ana = analog

Pin n°

Pin Name

Level Port

Input Output

Type

Input

TQFP64

Output

float

wpu

int

ana

1 PE4 (HS) I/O CTHS X X X X Port E4 2 PE5 (HS) I/O C 3 PE6 (HS) I/O C 4 PE7 (HS) I/O C 5 PB0/PWM3 I/O C 6 PB1/PWM2 I/O C 7 PB2/PWM1 I/O C 8 PB3/PWM0 I/O C

9 PB4/ARTCLK I/O C 10 PB5 I/O C 11 PB6 I/O C 12 PB7 I/O C 13 PD0/AIN0 I/O C 14 PD1/AIN1 I/O C 15 PD2/AIN2 I/O C 16 PD3/AIN3 I/O C 17 PD4/AIN4 I/O C 18 PD5/AIN5 I/O C 19 PD6/AIN6 I/O C 20 PD7/AIN7 I/O C 21 V 22 V 23 V

DDA SSA DD_3

S Analog Power Supply Voltage S Analog Ground Voltage S Digital Main Supply Voltage

HS X X X X Port E5

HS X X X X Port E6

HS X X X X Port E7

X ei2 X X Port B0 PWM Output 3

X ei2 X X Port B1 PWM Output 2

X ei2 X X Port B2 PWM Output 1

X ei2 X X Port B3 PWM Output 0

X ei3 X X Port B4 PWM-ART External Clock

X ei3 X X Port B5

X ei3 X X Port B6

X ei3 X X Port B7

X X X X X Port D0 ADC Analog Input 0

X X X X X Port D1 ADC Analog Input 1

X X X X X Port D2 ADC Analog Input 2

X X X X X Port D3 ADC Analog Input 3

X X X X X Port D4 ADC Analog Input 4

X X X X X Port D5 ADC Analog Input 5

X X X X X Port D6 ADC Analog Input 6

X X X X X Port D7 ADC Analog Input 7

Main

function

(after

reset)

Alternate function

8/152

Page 9

ST72311R, ST72511R, ST72532R

Pin n°

Level Port

Pin Name

Type

TQFP64

24 V

SS_3

25 PF0/MCO I/O C 26 PF1/BEEP I/O C 27 PF2 I/O C 28 PF3/OCMP2_A I/O C 29 PF4/OCMP1_A I/O C 30 PF5/ICAP2_A I/O C 31 PF6 (HS)/ICAP1_A I/O C 32 PF7 (HS)/EXTCLK_A I/O C 33 V

DD_0

34 V

SS_0

35 PC0/OCMP2_B I/O C 36 PC1/OCMP1_B I/O C 37 PC2 (HS)/ICAP2_B I/O C 38 PC3 (HS)/ICAP1_B I/O C 39 PC4/MISO I/O C 40 PC5/MOSI I/O C 41 PC6/SCK I/O C 42 PC7/SS 43 PA0 I/O C 44 PA1 I/O C 45 PA2 I/O C 46 PA3 I/O C 47 V

DD_1

48 V

SS_1

49 PA4 (HS) I/O C 50 PA5 (HS) I/O C 51 PA6 (HS) I/O C 52 PA7 (HS) I/O C

53 V

54 RESET

Input

S Digital Ground Voltage

T T T T T

T T T

S Digital Main Supply Voltage S Digital Ground Voltage

T T T

I/O C

S Digital Main Supply Voltage S Digital Ground Voltage

T T T T

I/O C X X Top priority non maskable interrupt (active low) 55 NC Not Connected 56 NMI I C 57 V

SS_3

58 OSC2

59 OSC1 60 V

DD_3

S Digital Ground Voltage

I/O

S Digital Main Supply Voltage

Main

function

(after

reset)

Alternate function

/2)

OSC

Input Output

Output

float

wpu

int

ana

X ei1 X X Port F0 Main clock output (f X ei1 X X Port F1 Beep signal output X ei1 X X Port F2 X X X X Port F3 Timer A Output Compare 2 X X X X Port F4 Timer A Output Compare 1 X X X X Port F5 Timer A Input Capture 2

HS X X X X Port F6 Timer A Input Capture 1 HS X X X X Port F7 Timer A External Clock Source

X X X X Port C0 Timer B Output Compare 2 X X X X Port C1 Timer B Output Compare 1

HS X X X X Port C2 Timer B Input Capture 2 HS X X X X Port C3 Timer B Input Capture 1

X X X X Port C4 SPI Master In / Slave Out Data X X X X Port C5 SPI Master Out / Slave In Data X X X X Port C6 SPI Serial Clock X X X X Port C7 SPI Slave Select (active low) X ei0 X X Port A0 X ei0 X X Port A1 X ei0 X X Port A2 X ei0 X X Port A3

HS X X X X Port A4 HS X X X X Port A5 HS X T Port A6 HS X T Port A7

Must be tied low in user mode. In programming mode when available, this pin acts as the programming voltage input V

X Non maskable interrupt input pin

External clock mode input pull-up or crystal/ceramic resonator oscillator inverter output

External clock input or crystal/ceramic resonator oscillator inverter input

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Page 10

ST72311R, ST72511R, ST72532R

Pin n°

Pin Name

TQFP64

61 PE0/TDO I/O C 62 PE1/RDI I/O C 63 PE2/CANTX I/O C 64 PE3/CANRX I/O C

Level Port

Input Output

Type

Input

Output

float

X X X X Port E0 SCI Transmit Data Out

X X X X Port E1 SCI Receive Data In

T T T

X Port E2 CAN Transmit Data Output

X X X X Port E3 CAN Receive Data Input

wpu

int

ana

Main

function

(after

reset)

Alternate function

Notes:

1. In the interrupt input column, “eiX” define s the asso ciated exte rnal interrupt vec tor. If the weak pul l-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See Section 8 "I/O PORT S" o n page 38 and Section 12.8 "I /O PORT PIN CHAR-

ACTERISTICS" on page 131 for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator see Section 1.2 "PIN DESCRIPTION" on page 7 and Section 12.5 "CLOCK AND TIMING CHARACTER-

ISTICS" on page 124 for more details.

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Page 11

1.3 REGISTER & MEMORY MAP

ST72311R, ST72511R, ST72532R

As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, up to 2Kbytes of RAM, up to 256 bytes of data EEPROM and up to

Figure 3. Me m ory Map

0000h

007Fh 0080h

087Fh 0880h

0BFFh 0C00h

0CFFh 0D00h

0FFFh

1000h

FFDFh FFE0h

FFFFh

HW Registers

(see Table 2)

1024 Bytes RAM 1536 Bytes RAM 2048 Bytes RAM

Reserved

Optional EEPROM

(256 Bytes)

Reserved

Program Memory

(60K, 48K, 32K, 16K Bytes)

Interrupt & Reset Vectors

(see Table 7 on page 32)

60Kbytes of user program memory. The RAM space includes up to 2 56 bytes for the st ack from 0100h to 01FFh.

The highest address by tes contain the user re set and interrupt vectors.

0080h

00FFh

0100h

01FFh

0200h

047Fh or 067Fh or 087Fh

Short Addressing RAM (zero page)

Stack

(256 Bytes)

16-bit Addressing

RAM

1000h

60 KBytes

4000h

48 KBytes

8000h

32 KBytes

C000h

16 KBytes

FFFFh

11/152

Page 12

ST72311R, ST72511R, ST72532R

Table 2. Hardware Register Map

Address Block

0000h 0001h

Port A

0002h

Label

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

0003h Reserved Area (1 Byte) 0004h

0005h 0006h

Port C

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register Port C Option Register

0007h Reserved Area (1 Byte) 0008h

0009h 000Ah

Port B

PBDR PBDDR PBOR

Port B Data Register Port B Data Direction Register Port B Option Register

000Bh Reserved Area (1 Byte) 000Ch

000Dh 000Eh

Port E

PEDR PEDDR PEOR

Port E Data Register Port E Data Direction Register Port E Option Register

000Fh Reserved Area (1 Byte) 0010h

0011h 0012h

Port D

PDDR PDDDR PDOR

Port D Data Register Port D Data Direction Register Port D Option Register

Reset

Status

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

Remarks

R/W R/W

R/W

R/W R/W R/W

R/W

R/W R/W R/W

0013h Reserved Area (1 Byte)

0014h 0015h 0016h

Port F

PFDR PFDDR PFOR

Port F Data Register Port F Data Direction Register Port F Option Register

00h

00h 00h

0017h

Reserved Area (9 Bytes)

001Fh 0020h MISCR1 Miscellaneous Register 1 00h R/W

0021h 0022h 0023h

0024h 0025h 0026h 0027h

SPI

ITC

SPIDR SPICR SPISR

ISPR0 ISPR1 ISPR2 ISPR3

SPI Data I/O Register SPI Control Register SPI Status Register

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

xxh 0xh 00h

FFh FFh FFh FFh

0028h Reserved Area (1 Byte) 0029h MCC MCCSR Main Clock Control / Status Register 01h R/W

12/152

R/W R/W R/W

R/W R/W Read Only

R/W R/W R/W R/W

Page 13

ST72311R, ST72511R, ST72532R

Address Block

002Ah 002Bh

002Ch EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

002Dh

0030h 0031h

0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

WATCHDOG

TIMER A

Label

WDGCR WDGSR

TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Watchdog Control Register Watchdog Status Register

Reserved Area (4 Bytes)

Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

Reset

Status

7Fh

000x 000x

00h 00h xxh xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

Remarks

R/W R/W

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W

R/W 0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

TIMER B

SCI

TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

00h 00h xxh xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h C0h

xxh

00xx xxxx

xxh

00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

Read Only R/W R/W R/W R/W R/W

R/W

13/152

Page 14

ST72311R, ST72511R, ST72532R

Address Block

0058h 0059h

005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h

006Fh 0070h

0071h 0072h

0073h 0074h 0075h 0076h

0077h 0078h 0079h

CAN

ADC

PWM ART

Label

CANISR CANICR CANCSR CANBRPR CANBTR CANPSR

ADCDR ADCCSR

PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR

ARTCSR ARTCAR ARTARR

Reserved Area (2 Bytes)

CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X

Data Register Control/Status Register

PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register

Reset

Status

00h

23h

00h

xxh

00h

Remarks

R/W R/W R/W R/W R/W R/W See CAN Description

Read Only R/W

R/W R/W R/W R/W R/W

R/W R/W R/W

007Ah

007Fh

Reserved Area (6 Bytes)

Legend: x=unde fined, R/W=rea d/write Notes:

1. The contents of the I/O p ort DR registers are readable only i n out put c onfigurat ion. I n i nput c onfiguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

14/152

Page 15

2 EPROM PROGRAM MEMORY

ST72311R, ST72511R, ST72532R

The program memory of the OTP and EPROM devices can be programmed with E PROM program ming tools available from STMicroelectronics

EPROM Erasure

EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current.

It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of

sunlight can be sufficient t o cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure.

An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces I power-saving modes du e to photo-diode leakage currents.

15/152

Page 16

ST72311R, ST72511R, ST72532R

3 DATA EEPROM

3.1 INTRODUCTION

The Electrically Erasable Programmable Read Only Memory can be us ed as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

Figure 4. EEPR OM Block Diagra m

FALLI N G

EEPROM INTERRUPT

EECSR

DETECTOR

EEPROMRESERVED

IE LAT00 0 0 0 PGM

3.2 MAIN FEATURES

■ Up to 16 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained erase and progr ammi ng cycle s

■ Interna l c ont rol of the global programming cycle

duration

■ End of programming cycle interrupt flag

■ WAIT mode management

EDGE

HIGH VOLTAGE

PUMP

ADDRESS

DECODER

ADDRESS BUS

ROW

DECODE R

MEMORY MATRIX

(1 ROW = 1 6 x 8 BITS)

DATA

MULTIPLEXER

EEPROM

128128

16 x 8 BITS

DATA LATCH ES

DATA BUS

16/152

Page 17

DATA EEPROM (Cont’d)

ST72311R, ST72511R, ST72532R

3.3 MEMORY ACCESS

The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 5 describes these different memory access modes.

Read Operation (LAT=0)

The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the dat a bus in l ess th an 1 CPU clock cycle . This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code.

Note: In order to ensure the correct read out of the EEPROM over the entire temperature range, the cell whose contents will be read, must be read twice in compliance with the following conditions:

■ a first reading must be immediately foll owed by

a second reading – all interrupts must be disabled until the two

readings are performed

– no other instructions are allowed between the

two reading instructions

■ the data of the first reading has to be discarded

The described procedu re corresponds to the fo llowing code sequence:

sim ld A,eeprom_var ld A,eeprom_var

rim

where eeprom_var adresses t he EERPOM cell to be read. Any of the ST7 addressing modes may be used.

Write Operation (LAT=1)

To access the write m ode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access t o the EEPRO M area o ccurs , the value is l atched in side the 16 data latch es ac cording to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPR OM cells. The effective high address (row) is determined by the la st EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same hig h address: only the four Le ast Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an in terrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two w rite access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LA T bit. It is not possible to read the latched data. This note is ilustrated by the Figure 6.

Figure 5. Data EE P R OM Pr ogramming Fl ow c hart

READ MOD E

LAT=0

PGM=0

READ B YT ES

IN EEPROM AREA

INTERRUPT GENERATION

IF IE= 1 0 1

CLEARED BY HARDWARE

WRITE MODE

LAT=1

PGM=0

WRITEUPTO16BYTES

IN EEPROM AREA

(with the same 12 MSB of the address)

STARTPROGRAMMING CYCLE

LAT=1

PGM=1 (set by software)

LAT

17/152

Page 18

ST72311R, ST72511R, ST72532R

DATA EEPROM (Cont’d)

3.4 POWER SAVI NG MO DE S Wait mode

The DATA EEPROM can enter WAIT mode on execution of the WFI inst ruction of the m icrocontroller. The DATA EEPROM will immediately enter this mode if there is no programming i n progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.

Halt mode

The DATA EEPROM immediatly enters HALT mode if the microcontroller exec utes the HA LT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

Figure 6. Data EE P R OM Pr ogramming Cy cl e

READ OP ERATION NOT POSSIBLE

INTERNAL PROGRAMMING VOLTAGE

ERASE CYCLE WRITE CYCLE

WRITEOF

DATA LATCHES

3.5 ACCESS ERROR HANDLING

If a read access occurs while LAT=1, then the data bus will not be driven.

If a write access occurs while LAT=0, then the data on the bu s w ill not be latche d.

If a programming cycl e is interrupted (by software/ RESET action), the memory data will not be guaranteed.

READ OPERATION POSSIBLE

PROG

EEPROM INTERRUPT

LAT

PGM

18/152

Page 19

DATA EEPROM (Cont’d)

ST72311R, ST72511R, ST72532R

3.6 REGISTER DESCRIPTION

Bit 1 = LAT

Latch Access Transfer

This bit is set by software. It is cleared by hard-

CONTROL/STATUS REGISTER (CSR)

Read/Write Reset Value: 0000 0000 (00h)

00000IELATPGM

ware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode

Bit 0 = PGM

Programming control and status

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated

Bits 7:3 = Reserved, forced by hardware to 0.

if the ITE bit is set. 0: Programming finished or not yet started

Bit 2 = IE

Interrupt enable

This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when t he PGM bit is cleared by hardware. The interrupt request is

1: Programming cycle is in progress

Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed

automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled

Table 3. DATA EEPROM Register Map and Reset Values

Address

(Hex.)

Label

76543210

002Ch

EECSR

Reset Value

00000IE0

RWM

PGM

19/152

Page 20

ST72311R, ST72511R, ST72532R

4 CENTRAL PROCE SSI NG UNIT

4.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

4.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 7. CPU Registers

4.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specifi c ins t r uc tions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as tempora ry storage areas f or dat a manipulation. (The Cross-A ssembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Cou nt er (P C )

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

1C1I1HI0NZ

1X11X1XX 70

PCL

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

20/152

Page 21

ST72311R, ST72511R, ST72532R

CENTRAL PROCESSING UNIT (Cont’d)

Zero

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

Bit 1 = Z This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

11I1HI0NZ

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test The 8-bit Condition Code register c ontains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instructions. It is reset by hardware during the same instruction s.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines .

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. I t’s a copy of the re-

sult 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

instructions. Bit 0 = C

This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Manageme nt B i ts

Bit 5,3 = I1, I0 The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priorit y I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared b y hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

Carry/borrow.

Interrupt

21/152

Page 22

ST72311R, ST72511R, ST72532R

CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

00000001

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, wi thout indicating the s tack ove rflow. The previously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The stack is used to save the retu rn address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc-

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardw are. Following a n MCU Reset, or after a Reset Stack Pointe r instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack

tions. In the case of an interrupt, the PCL is stored at the first location point ed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.

higher address.

Figure 8. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 0100h

@ 01FFh

X PCH PCL

PCH PCL

Stack Higher Address = 01FFh Stack Lower Address =

PCH PCL

0100h

A X

PCH

PCL

PCH

PCL

A X

PCH

PCL

PCH

PCL

PCH PCL

22/152

Page 23

5 SUPPLY, RESET AND CLOCK MANAGEMENT

ST72311R, ST72511R, ST72532R

The ST72311R, ST72511R and ST72532R microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview

Main features

■ Main supply low voltage detection (LVD)

■ RESET Manager (RSM)

■ Low consumption resonator oscillator

is shown in F igure 9.

Figure 9. Cl oc k , RESET, Option and Supply Manage ment Overview

OSC2

OSC1

RESET

OSCILLATOR

RESET

LOW VOLTAGE

DETECTOR

(LVD)

OSC

MAIN CLOCK

CONTROLLER

FROM

WATCHDOG

PERIPHERAL

23/152

Page 24

ST72311R, ST72511R, ST72532R

5.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V

supply voltage is below a V

reference

IT-

value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

is below:

when VDD is rising

–V

IT+

when VDD is falling

–V

IT-

The LVD func t ion is illustrated in F igure 10. Provided the minimum V

the oscillator frequency) is below V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

Figure 10. Low Voltage Detector vs Reset

IT+

IT-

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional function whi ch can be se-

lected when ordering the device (ordering information).

hys

RESET

24/152

Page 25

5.2 RESET SEQUENCE MANAGER (RSM)

ST72311R, ST72511R, ST72532R

5.2.1 Introd uct i on

The reset sequence manager in cludes three RESET sources as shown in F igure 12:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET s eque nc e cons i sts o f 3 p has es

as shown in Figure 11:

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 12. Reset Block Diagram

RESET

CPU

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

COUNTER

FETCH

VECTOR

INTERNAL RESET

WATC HDOG RESET

LVD RESET

25/152

Page 26

ST72311R, ST72511R, ST72532R

RESET SEQUENCE MANAGER (Cont’d)

5.2.2 Asynchronous External RES ET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

This pull-up has no fixe d value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized as shown in Figure 13. This detection is asynchronous and theref ore the M C U can enter reset state even in HALT mode.

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electr ical characteristics section.

Figure 13. RESET Sequences

IT+

IT-

5.2.3 Inte r na l Lo w Volta ge Detection RESET

Two differen t RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 13.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

avoid parasitic resets.

5.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET low during t

pin acts as an output that is pulled

w(RSTL)out

CAUTION: this output signal as not enough energy to be used to drive external devices.

WATCHDOG

RESET

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

DELAY

RUN

h(RSTL)in

SHORT EXT.

RESET

RUN

DELAY

WATCHDOGUNDERFLOW

RUN

DELAY

w(RSTL)out

INTERNAL RESET (4096T FETCH VECTOR

CPU

)

26/152

Page 27

5.3 LOW CONSUMPTION OSCILLATOR

ST72311R, ST72511R, ST72532R

The f

main clock of the ST7 can be generated

OSC

by two different source types:

■ an external source

■ a crystal or ceramic resonator oscillators

The associated hardware configuration are shown in Table 4 . Refer to the electrical characteristics section for mor e d etails.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillator

This oscillator (based on constant current source) is optimized in t erms of c onsumption and has the advantage of producing a very accurate rate on the m ain clo ck of th e S T7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in T able 4 and have to be mounted as close as possible to the oscillator pins in ord er to minimize output distortion and start-up stabilization time.

This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Table 4. ST7 Clock Sources

Hardware Configuration

OSC1 OSC2

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC1 OSC2

ST7

LOAD

CAPACITORS

OBP

27/152

Page 28

ST72311R, ST72511R, ST72532R

6 INTE RRUPTS

6.1 INTRODUCTION

The CPU enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP – 1 maskable Top Level Event: TLI

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed int errupt vector addre sses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller.

6.2 MASKI NG AN D PROC ESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of

each interrupt vector (see Table 1). The processing flow is shown in Figure 1.

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according t o

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the c ontents of t he saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 5. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

Low

High

Figure 14. Inte rru pt P rocessing Flow cha r t

RESET

RESTORE PC, X, A, CC

FROM STACK

28/152

PENDING

INTERRUPT

FETCH NEX T

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT STAYS PENDING

TLI

Interrupt has the same or a

lower software priority

than current one

STACK PC, X, A, CC

LOA D I1:0 F ROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

I1:0

softwarepriority

than current one

Interrupthas a higher

Page 29

INTERRUPTS (Cont’d)

ST72311R, ST72511R, ST72532R

Servicing Pe nding Interrup ts

As several interrupts can b e pending at the sam e time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 2 describes this decision process.

Figure 15. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previ ous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (ex ternal or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 1). After stacking the PC, X, A and CC reg-

isters (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 1 as a TLI. Caution: TRAP can be interrupted by a TLI.

■ RESET

The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vect or sourc es can be serviced if the corresponding interrupt is e nabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC regist er). If any of these two conditions is false, the interrupt is la tched and thus remains pending.

■ TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI se rvice routi ne.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a grou p connected to the same interrupt line are selected simultaneously, these will b e lo gically NAND ed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

29/152

Page 30

ST72311R, ST72511R, ST72532R

INTERRUPTS (Cont’d)

6.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with e xit from HALT mode capab ility and it is selected through the same decision process shown in Figure 2.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 16. Concurrent Int errupt Manag e m ent

IT2

IT1

IT4

IT2

RIM

IT1

IT3

TLI

IT0

TLI

IT1

HARDWARE PRIORITY

MAIN

11 / 10

6.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 3 and Fig ure 4 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in

Figure 4. The interrupt hardware priority is given in

this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

SOFTWARE PRIORITY LEVEL

IT0

IT3

IT4

MAIN

3 3 3 3 3 3 3/0

11 11 11 11 11 11

USED STACK = 10 BYTES

Figure 17. Nested Interrupt Management

IT2

IT1

IT4

IT1

IT2

RIM

HARDWARE PRIORITY

MAIN

IT4

IT3

TLI

IT0

TLI

11 / 10

30/152

IT4

IT0

IT3

IT1

SOFTWARE PRIORITY LEVEL

IT2

MAIN

I1 I0

3 3 2 1 3 3 3/0

11 11 00 01 11 11

USED STACK = 20 BYTES

Page 31

INTERRUPTS (Cont’d)

ST72311R, ST72511R, ST72532R

6.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

11I1 H I0 NZC

Bit 5, 3 = I1, I0

Software Interr u p t Priori ty

These two bits indicate the current interrupt software priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

Low

High

These two bits are set/cleared by ha rdware whe n entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by sof tw are wi th th e RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TLI, TRAP and RESET events c an i nter rupt a level 3 program.

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt ve ctor (except R ESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h )

The RESET, TRAP and TLI v ectors have no sof tware priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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Page 32

ST72311R, ST72511R, ST72532R

INTERRUPTS (Cont’d) Table 6. Dedicated Interrupt Instruc tion Set

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

In order not to lose the cu rrent so ftwar e priorit y level, the RIM, SIM, HA LT, WF I and PO P CC ins tructio ns sho uld nev er be used in an interrupt routine.

Table 7. Int errupt Mapp in g

N°

0 TLI External Top Level Interrupt MISCR2 yes FFFAh-FFFBh 1 MCC/RTC Main Clock Controller Time Base Interrupt MCCSR FFF8h-FFF9h 2 ei0 External Interrupt Port A3..0 3 ei1 External Interrupt Port F2..0 FFF4h-FFF5h 4 ei2 External Interrupt Port B3..0 FFF2h-FFF3h 5 ei3 External Interrupt Port B7..4 FFF0h-FFF1h

6 CAN CAN Peripheral Interrupts CANISR FFEEh-FFEFh 7 SPI SPI Peripheral Interrupts SPISR

8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh

9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h 10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h 11 EEPROM EEPROM Interrupt EECSR FFE4h-FFE5h 12 Not Used FFE2h-FFE3h 13 PWM ART PWM ART Overflow Interrupt ARTCSR Yes FFE0h-FFE1h

Source

Block

RESET Reset

TRAP Software Interrupt no FFFCh-FFF Dh

Description

Label

N/A

Priority

Order

Highest

Priority

Lowest Priority

Exit from

HALT

yes FFFEh-FFFFh

Address

Vector

FFF6h-FFF7h

FFECh-FFEDh

Note 1: Valid for HALT and ACTIVE-HA LT m odes except for t he MCC/RT C interrupt source which exits from ACTIVE-HALT mode only.

32/152

Page 33

INTERRUPTS (Cont’d) Table 8. Nested Interrupts Register Map and Reset Values

ST72311R, ST72511R, ST72532R

Address

(Hex.)

0024h

0025h

0026h

0027h

Label

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value1111

76543210

ei1 ei0 MCC/RTC TLI

I1_3

I1_7

EEPROM SCI TIMER B TIMER A

I1_11

I0_3

SPI CAN ei3 ei2

I0_7

I0_11

I1_2

I1_6

I1_10

I0_2

I0_6

I0_10

I1_13

I1_1

I1_5

I1_9

PWMART Not Used

I0_1

111

I0_5

I0_9

I0_13

I1_4

I1_8

I1_12

I0_4

I0_8

I0_12

33/152

Page 34

ST72311R, ST72511R, ST72532R

7 POWER SAVIN G MO DES

7.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): SLOW, WAIT (SLOW WAIT), AC- TIVE HALT and HALT.

After a RESET the normal operating m ode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f

CPU

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 18. P ower Saving Mo de Transitions

High

RUN

SLOW

7.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

CPU

In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in norm al ope ra ting mode. The CPU and peripherals are clocked at this lower frequency.

Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is al ready in SLOW mode.

Figure 19. SLOW Mode Clock Transitions

CPU

OSC

/4 f

OSC

/8 f

OSC

WAIT

SLOW WAIT

ACTIVE HALT

HALT

Low

POWER CONSUMPTION

MISCR1

CP1:0

SMS

00 01

NEW SLOW

FREQUENCY

REQUEST

NORMALRUN MODE

REQUEST

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Page 35

POWER SAVING MODES (Cont’d)

ST72311R, ST72511R, ST72532R

7.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This pow er s av in g mode is s e lected by ca llin g the ‘WFI’ instr uc ti o n. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘ 10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to th e starting address of the interrupt or Reset service routine. The MCU will r e main in W AIT mod e unt il a Rese t or an Interrupt occurs, causing it to wake up.

Refer to Figure 20.

Figure 20. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

INTERRUPT

PERIPHERALS CPU I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

ON ON

OFF

ON ON ON

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

35/152

Page 36

ST72311R, ST72511R, ST72532R

POWER SAVING MODES (Cont’d)

7.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MC U. They are both entered by executing the ‘HALT’ in struction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 HALT mode 1 ACTIVE-HALT mode

7.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a rea l time clock available. It is entered by exec uting the ‘HALT’ instruction when the OIE bit of t he M ain Clock Controller Status register (MCCSR) is set (see Section

10.2 on page 52 for more details on the MCCSR

tion of either an MCC/RTC interrupt, a specific interrupt (see Table 7, “Interrupt Mapping,” on page 32) or a RESET. When exiting ACTIVEHALT mode by means of a RESET or an interrupt, a 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by servicing the in terru pt o r by fe tch ing the re set vec tor wh ich woke it up (see Figure 22).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked exc ept t hos e w hich get their clock supply from another clock generator (such as external o r a ux iliary oscillat o r) .

The safeguard against staying l ocked in ACT IVEHALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 21. ACTIVE-HALT Timing Overview

ACTIVE

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 22. ACT IV E - HA LT Mode Flow - cha rt

HALT INSTRUCTION

(MCCSR.OIE=1)

INTERRUPT

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

ON OFF OFF

ON OFF

Notes:

1. Peripheral clocked with an external clock source

can still be active.

2. Only the MCC/RTC interrupt and som e s pecific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 7, “Interrupt M appi ng ,” on p age 32 for more details.

3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

36/152

Page 37

POWER SAVING MODES (Cont’d)

7.4.2 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 52 for more details on the MCCSR register).

The MCU can exit HALT m ode on reception of either a specific interrupt (see Table 7, “Interrupt Mapping,” on page 32) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the i nterrupt or by fetching the reset vector which woke it up (see Figure 24).

When entering HALT mode, the I bit in the CC register is forced to 0 to e nable interrupt s. Therefore, if an interrupt is pending, the MCU wakes immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WD GHA LT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 14.1 on page 144 for more details).

Figure 23. HALT Timing Overview

ST72311R, ST72511R, ST72532R

Figure 24. HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=0)

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

4096 CPU CLOCK CYCLE

OSCILLATOR PERIPHERALS CPU I[1:0] BITS

WATCHDOG

RESET

DELAY

DISABLE

OFF

OFF OFF

ON OFF

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=0]

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

FETCH

VECTOR

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some spec ific interrupt s can exit the MCU from HALT mode (su ch as ex ternal i nterrupt). Refer to Table 7, “Interrupt Mapping,” on page 32 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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Page 38

ST72311R, ST72511R, ST72532R

8 I/O POR TS

8.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs and for specific pins:

– external interrupt generat ion – alterna te signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

8.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implem entation section). The generic I/O block diagram is shown in Figure 25

8.2.1 Input Modes

The input configuration is sele cted by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latc h valu e but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independent ly generate an int errupt request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the Miscellaneous register.

Each external interrupt vector is linked t o a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones.

In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Fi gure 26).

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified.

8.2.2 Output Modes

The output configuration is selecte d by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0V 1V

Vss

Floating

8.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is au tomatically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is autom atically conf igured in ou tput mode (push-pull or open drain according to the peripheral).

When the signal is goi ng to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin h as to be configured in input floating mode.

38/152

Page 39

I/O PORTS (Cont’d) Figure 25. I /O Port General B loc k D iag ram

ST72311R, ST72511R, ST72532R

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNA TE OUTPUT

ALTERNA TE ENABLE

If implemented

PULL-UP CONFIGURATION

N-BUFFER

CMOS SCHMITT TRIGGER

P-BUFFER (see table below)

PULL-UP (see table below)

PAD

DIODES (see table below)

ANALOG

INPUT

EXTERNAL INTERRUPT SOURCE (eix)

POLARITY SELECTION

Table 9. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffer

Input

Output

Floating with/without Interrupt Off Pull-up with/withou t Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

FROM OTHER BITS

ALTERNATE

INPUT

Diodes

to V

Off

Note: The diode to V true open drain pads. A local protection between the pad and V vice against positive stress.

is implemented to protect the de-

is not implemented in the

to V

39/152

Page 40

ST72311R, ST72511R, ST72532R

I/O PORTS (Cont’d) Table 10. I/O Port Configurations

Hardware Configuration

NOT IMPLEMENTED IN TRUEOPEN DRAIN I/O PORTS

INPUT

NOT I MPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

OPEN-DRAIN OUTPUT

PAD

PULL-UP CONFIGURATION

FROM

OTHER

PINS

INTERRUPT CONFIGURATION

DR REGISTER ACCESS

ENABLE OUTPUT

ALTERNATE INPUT

EXTERNAL INTERRUPT SOURCE (ei

POLARITY

SELECTION

ANALOG INPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DATABUS

)

DATA BUS

NOT I MPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

PUSH-PULL OUTPUT

PAD

ENABLE OUTPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DATA BUS

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function outp ut status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

40/152

Page 41

I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analo g multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it i s recommended not to have clocking pins located close t o a sele cted analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

8.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR regi sters and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to anot her should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 26 Other transitions are potentially risky and shou ld be avoide d, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 26. I nt errupt I/O Port Sta te Transitions

ST72311R, ST72511R, ST72532R

Standard Ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

Interrupt P orts PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

PA3, PB4, PB3, PF2 (without pull-up)

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1

True Open D rai n P orts PA7:6

MODE DDR

floating input 0 open drain (high sink ports) 1

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT push-pull

= DDR, OR

The I/O port register configurations are summarized as follows.

Pull-up Input Port (CANTX requirement) PE2

MODE

pull-up input

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Page 42

ST72311R, ST72511R, ST72532R

I/O PO R T S (Cont’d)

8.4 LOW POWER MODES 8.5 INTERRUPTS

Mode Description

WAIT

HALT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

External interrupt on selected external event

Event

Flag

Enable

Control

Bit

DDRx

ORx

Exit from Wait

Yes Yes

Table 11. Port Configuration

Port Pin name

PA7:6 floating true open-drain

Port A

Port B Port C PC7:0 floating pull-up open drain push-pull PC3:2 only

Port D PD7:0 floating pull-up open drain push-pull No Port E

Port F

* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.

PA5:4 floating pull-up open drain push-pull PA3 floating floating interrupt open drain push-pull PA2:0 floating pull-up interrupt open drain push-pull PB4, PB3 floating floating interrupt open drain push-pull PB7:5, PB2:0 floating pull-up interrupt open drain push-pull

PE7:3, PE1:0 floating pull-up open drain push-pull PE7:4 only PE2 pull-up input only * No PF7:3 floating pull-up open drain push-pull PF7:6 only PF2 floating floating interrupt open drain push-pull PF1:0 floating pull-up interrupt open drain push-pull

OR = 0 OR = 1 OR = 0 OR = 1 High-Sink

Input Output

Exit

from

Halt

Yes

42/152

Page 43

I/O PO R T S (Cont’d)

8.5.1 Register Description

ST72311R, ST72511R, ST72532R

DATA REGISTER (DR)

Port x Data Register PxDR with x = A, B, C, D, E or F.

Read/Write Reset Value: 0000 0000 (00h)

D7 D6 D5 D4 D3 D2 D1 D0

Bit 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I /O pin ( pin configured as input).

OPTION REGISTER (OR)

Port x Option Register PxOR with x = A, B, C, D, E or F.

Read/Write Reset Value: 0000 0000 (00h)

O7 O6 O5 O4 O3 O2 O1 O0

Bit 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.

The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected.

Each bit is set and cleared by software.

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register PxDDR with x = A, B, C, D, E or F.

Read/Write Reset Value: 0000 0000 (00h)

Input mode: 0: floating input 1: pull-up input with or without interrupt

Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Bit 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software.

0: Input mode 1: Output mode

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Page 44

ST72311R, ST72511R, ST72532R

I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values

Address

(Hex.)

Reset Value

of all IO port registers

0000h PADR

0002h PAOR 0004h PCDR

0006h PCOR 0008h PBDR

000Ah PBOR 000Ch PEDR

000Eh PEOR

0010h PDDR

Label

76543210

00000000

MSB LSB0001h PADDR

MSB LSB0005h PCDDR

MSB LSB0009h PBDDR

MSB LSB000Dh PEDDR

MSB LSB0011h PDDDR 0012h PDOR 0014h PFDR

0016h PFOR

MSB LSB0015h PFDDR

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Page 45

9 MISCELLANEOUS REGISTERS

ST72311R, ST72511R, ST72532R

The miscellaneous registers allow control over several features such as the e xternal interrupt s or the I/Oalternate functions.

9.1 I/O PORT INTE R RUP T SENSITIVITY

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the Miscellaneous registers (Figure 27). This control allows to have up to 4 fully independen t external int errupt s ource sensitivities.

Each external interrupt source can be gen erated on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

To guarantee correct functiona lity, the sensitivity bits in the MISCR registers must be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). See I/O port register and Miscellaneous register descriptions for more details on the programming.

9.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers allow to manage four I/O port miscellaneous alternate functions:

■ Main clock signal (f

■ A Beep signal output on PF1 (with three

/2) output on PF0

OSC

selectable audio frequencies)

■ A TLI management on a dedicated pin

■ A SPI S S pin internal control to use the PC7 I/O

port function while the SPI is active.

These functions are described in details in the

Section 9.3 "MISCELLANEO US REGISTERS" on page 46.

Figure 27. External Interru pt Sour ces vs MIS C R

PA3

SOURCES

PA2 PA1 PA0

MISCR2.IPA

PF2 PF1 PF0

PB3 PB2 PB1 PB0

MISCR2.IPB PB7 PB6 PB5 PB4

ei0

INTERRUPT

SOURCE

ei1

INTERRUPT

SOURCE

ei2

INTERRUPT

SOURCE

ei3

INTERRUPT

SOURCE

MISCR1

IS20 IS21

SENSITIVITY

CONTROL

MISCR1

IS10 IS11

SENSITIVITY

CONTROL

45/152

Page 46

ST72311R, ST72511R, ST72532R

MISCELLANE OUS REGISTERS (Cont ’d)

9.3 MISCELLANEOUS REGISTERS

Bit 4:3 = IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write Reset Value: 0000 0000 (00h)

IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS

Bit 7:6 = IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts:

- ei2 (port B3..0)

IS11 IS1 0

00 0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

External Interrupt Sensit ivity

MISCR2.IPB =0 MISCR2.IPB=1

Falling edge &

low level

Rising edge & high level

bits, is applied to the following external interrupts:

- ei0 (port A3..0)

IS21 IS20

00 0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

External Interrupt Sensitivity

MISCR2.IPA=0 MISCR2.IPA=1

Falling edge &

low level

- ei1 (port F2..0)

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Rising edge & high level

- ei3 (port B7..4)

IS11 IS1 0 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = MCO

Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

port)

OSC

/2on I/O

Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

/ 4 0 0

OSC

/ 8 1 0

OSC

/ 16 0 1

OSC

/ 32 1 1

OSC

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.

= f

0: Normal mode. f 1: Slow mode. f

CPU

is given by CP1, CP0

OSC

/ 2

See Se ction 7.2 "SLO W MODE" on page 34 and

Section 10.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)" on page 52 for more details.

46/152

Page 47

MISCELLANE OUS REGISTERS (Cont ’d)

ST72311R, ST72511R, ST72532R

MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write Reset Value: 0000 0000 (00h)

Bit 3 = TLIS This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared.

TLI sensitivity

0: Falling edge

IPA IPB BC1 BC0 TLIS TLIE SSM SSI

1: Rising edge

Bit 2 = TLIE

TLI enable

This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by

Bit 7 = IPA This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It is set and cleared by softw are. 0: No sensit iv ity in v er s ion 1: Sensitiv it y inv er s ion See Section 9.1 "I/O PORT INTERRUPT SENSI-

TIVITY" on page 45 and the description of the IS2x

bits of the MISCR1 register for more details.

Bit 6 = IPB This bit is used to invert the sensitivity of the port B

Interrupt polarity for port A

Interrupt polarity for port B

software. 0: TLI disabled 1: TLI enabled Note: a parasitic interrupt can be generated when clearing the TLIE bit.

Bit 1 = SSM

SS mode selection

This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS

input from the external SS

pin.

1: I/O mode (PC7), the level of the SPI SS

read from the SSI bit. [3:0] external interrupts. It is set and cleared by softw are.

0: No sensit iv ity in v er s ion 1: Sensitiv it y inv er s ion See Section 9.1 "I/O PORT INTERRUPT SENSI-

TIVITY" on page 45 and the description of the IS1x

Bit 0 = SSI This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.

SS internal mode

bits of the MISCR1 register for more details.

signal is

Bit 5:4 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capab ility .

BC1 BC0 Beep mode with f

0 0 Off 0 1 ~2-KHz 1 0 ~1-KHz 1 1 ~500-Hz

=16MHz

OSC

Output

Beep signal

~50% duty cycle

The beep output signal is available in ACTIVEHALT mode but has to be di sabled to reduce the consumption.

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Page 48

ST72311R, ST72511R, ST72532R

MISCELLANE OUS REGISTERS (Cont ’d) Table 13. Miscellaneous Register M ap and Reset Value s

Address

(Hex.)

0020h

0040h

Label

MISCR1

Reset Value

MISCR2

Reset Value

76543210

IS11

IPA

IS10

IPB

MCO

BC1

IS21

BC0

IS20

TLIS

CP1

TLIE

CP0

SSM

SMS

SSI

48/152

Page 49

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

ST72311R, ST72511R, ST72532R

10.1.1 Introduction

The Watchdog tim er is used to detect t he occurrence of a software fault, usually generated by external interference or by unforeseen logi cal conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset o n expiry of a programmed time period, unless the program refresh-

es the counter’s contents before the T6 bit becomes cleared.

10.1.2 Main Features

■ Programmable timer (64 increments of 12288

CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) after a HALT

instruction or when the T6 bit reaches zero

Figure 28. Watchd og Block Diag ram

RESET

■ Hardware Watchdog selectable by option byte

■ Watchdog Reset indicated by status flag (in

versions with Safe Reset option only)

10.1.3 Functional Description

The counter value stored in the CR register (bits T[6:0]), is decremented every 12,288 m ac hine cycles, and the length of the timeout perio d can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becom es cleared), it initia tes a reset cycle pulling low the reset pin for typically 500ns.

CPU

WATCHDOG CONTROL REGISTER (CR)

WDGA

T6 T0

7-BIT DOWNCOU NTE R

CLOCK DIVIDER

12288

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Page 50

ST72311R, ST72511R, ST72532R

WATCHD OG TI M E R (Cont’d)

The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to b e stored in the CR register must be between FFh and C0h (see Table 14 .Watchdog Timing (fCPU = 8 MHz)):

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imm e-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset.

Table 14.Watchdog Timing (f

CR Register

initial value

Max FFh 98.304

Min C0h 1.536

= 8 MHz)

CPU

WDG timeout period

(ms)

10.1.7 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA

Activation bit

. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generat e a sof t ware reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

10.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option b yte, the watchdog is always active and the WDGA bit in the CR is not used.

Refe r to the device- specif ic Optio n Byte descri ption.

10.1.5 Low Power Modes

Mode Description

WAIT No effect on Watchdog.

Immediate reset generation as soon as

HALT

the HALT in s truct ion is executed if the Watchdog is activated (WDGA bit is set).

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

STATUS REGISTER (SR)

Read/Write Reset Value*: 0000 0000 (00h)

-------WDOGF

Bit 0 = WDOGF

Watchdog flag

. This bit is set by a watc hdog rese t a nd clea red by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred

* Only by software and power on/off reset Note: This register is not us ed i n versions without

LVD Reset.

10.1.6 Interrupts

None.

50/152

Page 51

WATCHD OG TI M E R (Cond’t) Table 15. Watchdog Time r Register Map and Rese t Values

ST72311R, ST72511R, ST72532R

Address

(Hex.)

002Ah

002Bh

Label

WDGCR

Reset Value

WDGSR

Reset Value

76543210

WDGA

WDOGF

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Page 52

ST72311R, ST72511R, ST72532R

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)

The Main Clock Controller consi sts of t hree di fferent functions:

■ a programmable CPU clock prescaler

■ a clock-out signal to supply external devices

■ a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1 Programmable CPU Clock Prescaler

The programmable CP U clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See

Section 7.2 "SLOW MODE" on page 34 for more

details). The prescaler s elect s th e f

main clock frequen-

CPU

cy and is controlled by three bits in the MISCR1 register: CP[1:0] and SMS.

CAUTION: The prescaler does not act on the CAN peripheral clock source. This peripheral is always supplied by the f

/2 clock source.

OSC

10.2.2 Clock-out Capability

The clock-out capability is an alternate function of an I/O port pin that out put s a f external devices. It is controlled by t he M CO bit in the MISCR1 register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.

10.2.3 Real Time Clock Timer (RTC)

The counter of the real time clock t imer allows an interrupt to be generated based on an accurate real time clock. Four di fferent t ime bas es depending directly on f tionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 7.4

"ACTIVE-HALT AND HALT MODES " on page 36

for more details.

Figure 29. Main Clock Controller (MCC/RTC) Block Diagram

/2 clock to drive

OSC

are available. The whole func-

OSC

CLOCKTO CAN

PERIPHERAL

OSC

MCCSR

MCC/RTC INTERRUPT

DIV 2

OSC

MISCR1

RTC

COUNTER

TB1 TB0 OIE OIF

0000

ALTERNATE

FUNCTION

MCO ----

PORT

DIV 2, 4, 8, 16

CP1 CP0

SMS

CPU

MCO

CPU CLOCK

TO CPU AND

PERIPHERALS

52/152

Page 53

ST72311R, ST72511R, ST72532R

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)

10.2.4 Register Description MISCELLANEOUS REGISTER 1 (MISCR1)

See “MISCELL ANEO U S REGIS TERS” Section.

Bit 0 = OIF This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0).

MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0001 (01h)

0: Timeout not reached 1: Timeout reached

CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

10.2.5 Low Power Modes

0000TB1TB0OIEOIF

Mode Description

Bit 7:4 = Reserved, always read as 0.

Bit 3:2 = TB[1:0]

Time base control

These bits select the programmable divider time

WAIT

ACTIVEHALT

base. They are set and cleared by software.

=8MHz f

OSC

Time Base

OSC

=16MHz

TB1 TB0

HALT

10.2.6 Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active

Counter

Prescaler

32000 4ms 2ms 0 0

64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1

(RIM instruction). A modification of the time base is taken into account at the end of the current period (prev iously set) to avoid an unwanted time shift. This allows to

Interrupt Event

use this time base as a real time clock.

Time base overflow

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVE-

event

Note:

1. The MCC/RTC interrupt allows to exit from AC-

TIVE-HALT mode, not from HALT mode. HALT mode.

When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving

mode

Oscillator interrupt flag

No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit from HALT” capability.

Event

Enable

Control

Flag

OIF OIE Yes No

Bit

Exit from Wait

Exit

from

Halt

Table 16. MCC/RTC Register Map and Reset Values

Address

(Hex.)

0029h

Label

MCCSR

Reset Value0000

76543210

TB1

TB0

OIE

OIF

53/152

Page 54

ST72311R, ST72511R, ST72532R

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction

The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare capabilities and of a 7-bit prescaler clock source.

These resources allow three possible operating modes:

– Generation of up to 4 independent PWM signals – Output compare and Time base interrupt – External event detector

Figure 30. PWM Auto-Reload Timer Block Diagram

The two first modes can be used together with a single counter frequency.

The timer can b e used to wake up the M CU from WAIT and HALT modes.

PWMx

ARTCLK

PWMCR

PORT

ALTERNATE

FUNCTION

EXT

CPU

MUX

OEx

INPUT

EXCL

OPx

POLARITY CONTROL

ARR

COUNTER

PROGRAMMABLE

PRESCALER

CC2 CC1 CC0 TCE FCRL OIE OVF

OCRx

COMPARE

8-BIT COUNTER

(CAR REGISTER)

DCRx

LOAD

ARTCSR

OVFINTERRUPT

54/152

Page 55

PWM AUTO-RELOAD TIMER (Cont’d)

10.3.2 Functional Description

ST72311R, ST72511R, ST72532R

Counter

The free running 8-bit cou nter is f ed b y the out put of the prescaler, and is incremented on every rising edge of the clock signal.

It is possible to read or write the content s of the counter on the fly by reading or writing the Counter Access register (ARTCAR).

When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

COUNTER

= f

INPUT

The timer counter’s input clock (f

/ 2

CC[2:0]

INPUT

) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2

This f

INPUT

(where n = 0, 1,..7).

frequency source is selected through the EXCL bit of the ARTCSR register and can be either the f

or an external input frequency f

CPU

EXT

The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TC E is set, the coun ter runs at the rate of the selected clock sour ce .

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are cleared and f

INPUT

= f

CPU

. The counter can be initialized by: – Writing to the ARTARR register and then setting

the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR reg-

ister. – Writing to the ARTCAR counter access register, In both cases the 7-bit pres caler is also cleared,

whereupon counting will start from a known value. Direct access to the prescaler is not possible.

Output compare contro l

The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an outpu t compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.

This double buffering method avoids glitch generation when changing the duty cycle on the fly.

Figure 31. Output compare control

COUNTER

ARTARR=FDh

COUNTER

OCRx

PWMDCRx

PWMx

FDh FEh FFh FDh FEh FFh FDh FEh

FDh

FFh

FEh

55/152

Page 56

ST72311R, ST72511R, ST72532R

PWM AUTO-RELOAD TIMER (Cont’d) Independent PWM signal generation

This mode allows up to four Pulse Width Mo dulat ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode.

Each PWMx ou tput signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function.

The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value.

PWM

= f

COUNTER

/ (256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the P WMCR register.

Figure 32. PWM Auto-reload Timer Function

255

DUTY CYCLE

(PWMDCRx)

When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored.

It should be noted that the reload values wil l also affect the value and the resolution of t he duty cycle of the PWM out put s ign al. T o obt ain a signal on a PWMx pin, the contents of the OCRx register must be greater than the con tents of the AR TARR register.

The maximum avai lable resolution for the PW Mx duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.

AUTO-RELOAD

COUNTER

(ARTARR)

000

WITH OEx=1 AND OPx=0

WITH OEx=1 AND OPx=1

PWMx OUTPUT

Figure 33. PWM Signal from 0% to 100% Duty Cycle

COUNTER

ARTARR=FDh

COUNTER

OCRx=FCh

OCRx=FDh

OCRx=FEh

AND OPx=0

WITH OEx=1

PWMx OUTPUT

OCRx=FFh

FDh FEh FFh FDh FEh FFh FDh FEh

56/152

Page 57

PWM AUTO-RELOAD TIMER (Cont’d)

ST72311R, ST72511R, ST72532R

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be

External clock and event detector mode

Using the f auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the n be counted before setting the OVF flag.

used as a time base in the application.

When enteri ng HALT m ode while f all the timer control registers are frozen but the counter continues to increment. If the OIE bit is set, the next over flow of the c ounter will generat e an interrupt which wakes up the MCU.

Figure 34. External Event Detector Example (3 counts)

EXT=fCOUNTER

ARTARR=FDh

COUNTER

OVF

FDh FEh FFh FDh

external prescaler input clock, the

EXT

EVENT

FEh FFh FDh

= 256 - ARTARR

EVENT

number of even ts to

is selected,

EXT

INTERRUPT

IF OIE=1

ARTCSR READ

INTERRUPT

IF OIE=1

57/152

Page 58

ST72311R, ST72511R, ST72532R

PWM AUTO-RELOAD TIMER (Cont’d)

10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR)

Read/Write Reset Value: 0000 0000 (00h)

0: New transition not yet reached 1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read/Write Reset Value: 0000 0000 (00h)

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

Bit 7 = EXCL

External Clock

CA7 C A6 CA5 CA4 CA3 CA2 CA1 CA0

This bit is set and cleared by software. I t selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock.

Bit 6:4 = CC[2:0]

Counter Clock Control

These bits are set and cleared by software. They determine the prescaler division ratio from f

COUNTER

INPUT

/ 2 / 4

/ 8 / 16 / 32 / 64

/ 128

With f

=8 MHz CC2 CC1 CC0

INPUT

8 MHz 4 MHz 2 MHz

1 MHz 500 KHz 250 KHz 125 KHz

62.5 KHz

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

INPUT

0 1 0 1 0 1 0 1

Bit 7:0 = CA[7:0]

Counter Access Data

These bits can be set and cleared e ither by hardware or by software. The ARTCAR register is used to read or write the auto-reload counter “on the fly” (while it is counting).

AUTO-RELOAD REGISTER (ARTARR)

Read/Write Reset Value: 0000 0000 (00h)

AR7 AR 6 AR5 AR4 AR3 AR2 AR1 AR0

Bit 3 = TCE

Timer Counter Enable

This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running.

Bit 2 = FCRL

Force Counter Re-Load

This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count.

Bit 1 = OIE

Overflow Interrupt Enable

This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable.

Bit 0 = OVF

Overflow Flag

This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR val-

Bit 7:0 = AR[7:0]

Counter Auto-Reload Data

These bits are set and cleared by so ftware. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same t ime, the PWM out put levels are changed according to the corresponding OPx bit in the PWMCR register.

This register has two PWM management functions:

– Adjusting the PWM frequency – Setting the PWM duty cycle resolution

PWM Frequency vs. Resolution:

ARTARR

value

0 8-bit ~0.244-KHz 31.25-KHz

[ 0..127 ] > 7-bit ~0.244-KHz 62.5-KHz [ 128..191 ] > 6-bit ~0.488-KHz 125-KHz [ 192..223 ] > 5-bit ~0.977-KHz 250-KHz [ 224..239 ] > 4-bit ~1.953-KHz 500-KHz

Resolution

PWM

Min Max

58/152

Page 59

PWM AUTO-RELOAD TIMER (Cont’d)

ST72311R, ST72511R, ST72532R

PWM CONTROL REGISTER (PWMCR)

Read/Write Reset Value: 0000 0000 (00h)

OE3OE2OE1OE0OP3OP2OP1OP0

Bit 7:4 = OE[3:0]

PWM Output Enable

These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled.

Bit 3:0 = OP[3:0]

PWM Output Polarity

These bits are set and cleared by software. They independently select the po larity of the fo ur PWM

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write Reset Value: 0000 0000 (00h)

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 7:0 = DC[7:0]

Duty Cycle Data

These bits are set and cleared by software. A PWMDCRx register is associated with the OCRx

register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.

output signals.

PWMx output level

Counter <= OCRx Counter > OCRx

100 011

OPx

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

59/152

Page 60

ST72311R, ST72511R, ST72532R

PWM AUTO-RELOAD TIMER (Cont’d) Table 17. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

Label

PWMDCR3

Reset Value

PWMDCR2

Reset Value

PWMDCR1

Reset Value

PWMDCR0

Reset Value

PWMCR

Reset Value

ARTCSR

Reset Value

ARTCAR

Reset Value

ARTARR

Reset Value

76543210

DC7

OE3

EXCL

CA7

AR7

DC6

OE2

CC2

CA6

AR6

DC5

OE1

CC1

CA5

AR5

DC4

OE0

CC0

CA4

AR4

DC3

OP3

TCE

CA3

AR3

DC2

OP2

FCRL

CA2

AR2

DC1

OP1

OIE

CA1

AR1

DC0

OP0

OVF

CA0

AR0

60/152

Page 61

10.4 16-BIT TIMER

ST72311R, ST72511R, ST72532R

10.4.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (

input capture

waveforms (

) or generating up to two output

output compare

and

PWM

Pulse lengths and waveform perio ds c an be m odulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized a fter a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, regi ster names are prefixed with TA (Timer A) or TB (Timer B).

10.4.2 Main Features

■ Programmable prescaler: f

■ Overflow status flag and maskable interrupt

■ External clock inpu t (must be at least 4 times

slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8.

CPU

of active edge

■ Output compare functions with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Input capture functions with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse Width Modulation mode (PWM)

■ One Pulse mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

10.4.3 Functional Description

10.4.3.1 Counter

The main block of the Programmab le Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nific a nt byte ( MS Byte ) .

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Count er Hi gh Regi ster ( ACHR) is th e

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byt e (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Stat us register (SR). (See note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the cloc k control bits of the CR2 register, as illustrated in Table 18 Clock

Control Bits. The value in the counter regi ster re-

peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency c an be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

The Block Diagram is shown in Figure 35. *Note: Some timer pins m ay not be available (not

bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

61/152

Page 62

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d) Figure 35. Timer Block Diagram

CPU

ST7 INTERNAL BUS

MCU-PERIPHERAL INTERFACE

EXTCLK

EXEDG

1/2 1/4

1/8

CC[1:0]

8 high

COUNTER

ALTERNATE

COUNTER

OVERFLOW

DETECT CIRCUIT

8 low

8-bit

buffer

high

OUTPUT

COMPARE REGISTER

TIMER INTERNAL BUS

OUTPUT COMPARE

CIRCUIT

low

16 16

low

high

OUTPUT COMPARE REGISTER

88 8

high

INPUT

CAPTURE

EDGE DETECT

CIRCUIT1

EDGE DETECT

CIRCUIT2

8 8 8

low

high

low

INPUT

CAPTURE

ICAP1

ICAP2

62/152

(See note)

TIMER INTERRUPT

ICF2ICF1 000OCF2OCF1 TOF

(Status Register) SR

(Control Register 1) CR1

LATCH1

LATCH2

OC2E

PWMOC1E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FO LV1OCIETOIE

EXEDG

IEDG2CC0CC1

(Control Register 2) CR2

Note: If IC, OC and TO interrupt requests have separate vectors then the last O R is not present (See device In terrupt Vec tor Table)

OCMP1

OCMP2

Page 63

16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter

Beginning of the sequence

At t0

Read MS Byte

LS Byte

is buffered

Other

instructions

Returns the buffered

LS Byte value at t0

At t0 +∆t

Read LS Byte

Sequence completed

The user must read the MS Byte f irst, then the LS Byte value is buffered automatically.

This buffered value rem ains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, One Pulse mo de or P WM m ode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these cond itions is false, the interrupt remains pending to be issued as soon as they are both true.

ST72311R, ST72511R, ST72532R

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Count ing then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.4.3.2 External Clock

The external clock (wh ere available) is selected if CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronised with t he falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

63/152

Page 64

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d) Figure 36. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFL OW FLAG (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

Figure 37. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0 001

Figure 38. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

64/152

Page 65

16-BIT TIMER (Cont’d)

10.4.3.3 Input Capture

In this section, the index, there are 2 input capture functions in the 16-bit timer.

The two input capture 16-bit registers (IC1R and IC2R) are used to latch the valu e of the free running counter after a transition is detected by the ICAP

pin (see figure 5).

MS Byte LS Byte

ICiR IC

The IC

R register is a read-only register.

The active transition is software programmable

through the IEDG Timing resolution is one count of the free running

counter: (

Procedure:

To use the input capture function, select the following in the CR2 register:

– Sele ct the timer clock (CC[1:0]) (see Table 18

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this conf iguration

is available). And select the following in the CR1 register: – Set the ICI E bit to ge nerat e an in terrupt after an

input capture com ing from e ither the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as a floating input or input

with pull-up without interrupt if this conf iguration

is available).

CPU

bit of Control Registers (CRi).

/CC[1:0]).

, may be 1 or 2 because

HR ICiLR

ST72311R, ST72511R, ST72532R

When an input capture occurs: – The ICF – The IC

running counter on the active transition on the ICAP

– A timer interrupt is generated if the ICIE bit i s s e t

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture in terrupt reques t (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. An access (read or write) to the IC

Notes:

1. After reading the IC input capture data is inhibited and ICF never be set until the IC read.

2. The IC counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One Pulse mode and PWM mode only the input capture 2 function can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connecte d to the timer. So any transitions on these pins activate the input capture function. Moreover if one of th e ICAP as an input and the s econd one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the in put capture function

1).

6. The TOF bit can be used with an interrupt in order to measure events that exce ed the timer range (FFFFh).

bit is set.

R register contains t he val ue of the free

pin (see Figure 40 ).

bit) is done in two steps:

bit is set.

iLR

HR register, the transfer of

will

LR register is also

R register contains the free running

pin is configured

is disabled by reading the ICiHR (see note

65/152

Page 66

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

IC2R Register

16-BIT

EDGE DETECT

CIRCUIT1

IC1R Register

16-BIT FREE RUNNING

COUNTER

Figure 40. Input Capture Timing Diagram

TIMER CLOCK

ICIE

(Control Register 1) CR1

IEDG1

(Status Register) SR

ICF2ICF1 000

(Control Register 2) CR2

IEDG2

CC0

CC1

COUNTER REGISTER

ICAPi FLAG

ICAPi REGISTER

Note: Active edge is rising edge.

66/152

FF01 FF02 FF03

ICAPi PIN

FF03

Page 67

16-BIT TIMER (Cont’d)

10.4.3.4 Output Compare

In this section, the index,

, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer .

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found bet ween the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

E bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be com pared to the counter register each timer clock cycle.

MS Byte LS Byte

ROC

HR OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

R value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OC

OCMP

E bit if an output is needed then the

pin is dedicated to the output com pare

signal.

– Sele ct the timer clock (CC[1:0]) (see Table 18

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVL

bit to applied to the OCMPi pins

after the match occurs. – Set the OC IE bit to generate an interrupt if it is

needed. When a match is found between OCRi register

and CR register:

– OCF

bit is set.

ST72311R, ST72511R, ST72532R

– The OCMP

pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC

R register value required for a specific timing application can be c alcul ated using the following f ormula:

∆t * f

∆ OC

R =

CPU

PRESC

Where:

∆t = Output compare period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 18

Clock Control Bits)

If the timer clock is an external clock, the formula is:

∆ OC

R = ∆t

* fEXT

Where:

∆t = Output compare period (in seconds)

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (i.e.

clearing the OCF

1. Reading the SR register while the OCF

set.

2. An access (read or write) to the OC The following procedure is recommended to pre-

vent the OCF it is read and the write to the OC

– Write to the OC

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

– Write to the OC

compare function and clears the OCF

bit) is done by:

bit from being set between the time

R register:

HR register (further compares

bit, which may be already set).

LR register (enables the output

bit is

LR register.

bit).

67/152

Page 68

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d) Notes:

1. After a proces sor write cycle to the OC ister, the output compare function is inhibited

iLR

until the OC

2. If the OC

E bit is not set, the OCMPi pin is a general I/O port and the OLVL appear when a match is f ound but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f OCMP

are set while the counter value equals

the OC

R register value (see Figure 42 on page

CPU

69). This behaviour is the same in OPM or

PWM mode. When the timer clock is f external clock mode, O CF

/4, f

CPU

and OCMPi are set while the counter value equals the OC ter value plus 1 (see Figure 43 on page 69).

4. The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used.

5. The value in the 16-bit OC OLV

bit should be changed after each suc-

R register and the

cessful comparison in order to control an output waveform or establish a new elapsed timeout.

iHR

reg-

bit will not

/2, OCFi and

/8 or in

CPU

R regis-

Forced Compare Output capabili ty

When the FOLV

bit is set by software, the OLVL bit is copied to the OCMPi pin. The OLVi bit has to be toggled in ord er to t oggle th e OCMP it is enabled (OC

E bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

FOLVL

bits have no effect in either One-Pulse

mode or PWM mode.

pin when

Figure 41. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

OC1R Register

16-bit

OC2R Register

OC1E CC0CC1

OC2E

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1

(Status Register) SR

OLVL1OLVL2OCIE

000OCF2OCF1

Latch

OCMP1

OCMP2

68/152

Page 69

16-BIT TIMER (Cont’d) Figure 42. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

TIMER

CPU

ST72311R, ST72511R, ST72532R

COUNTER REGISTER

OUTPUT COMPARE REGISTER

OUTPUT COMPARE FLAG

OCMP

(OCRi)

(OCFi)

PIN (OLVLi=1)

Figure 43. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER

OUTPUT COMPARE FLAG

(OCRi)

LATCH

(OCFi)

2ED0 2ED1 2ED2

TIMER

CPU

2ED0 2ED1 2ED2

2ED3

2ED42ECF

OCMPi PIN (OLVLi=1)

69/152

Page 70

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The One Pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the a ctive trans ition o n th e

ICAP1 pin with the IEDG1 bit must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 18

Clock Control Bits).

(the ICAP1 pin

Clearing the Input Capture in terrupt reques t (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. An access (read or write) to the IC

bit) is done in two steps:

iLR

bit is set.

The OC1R register value required for a specific timing application can be calculated usi ng the following formula:

R Value =

CPU

PRESC

- 5

Where: t = Pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 18

Clock Control Bits)

If the timer clock is an external clock the formula is:

OCiR = t

* fEXT

-5

Wher e: t = Pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of t he OC1R register, the OLV L1 bit is output on the OCMP1 pin (see Figure 44).

One Pulse mode cycle

When

event occurs

on ICAP1

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

When

Counter = OC1R

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, th e ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

70/152

Notes:

1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. When the Pulse Width Modulation (PWM ) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used t o perfo rm input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge o ccurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When One P ulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.

Page 71

16-BIT TIMER (Cont’d) Figure 44. One Pulse Mode Timing Example

ST72311R, ST72511R, ST72532R

COUNTER

ICAP1

OCMP1

FFFC FFFD FFFE 2ED0 2E D1 2ED2

OLVL2

compare1

Note: IEDG1=1, OC1R=2ED 0h, OLV L1=0, OLVL2=1

Figure 45. P ul se Wi dt h M odulation Mo de Ti m in g E xa m p le

COUNTER

OCMP1

FFFC FFFD FFFE

34E2

OLVL2

2ED0 2ED1 2ED2

compare2 compare1 compare2

FFFC FFFD

2ED3

OLVL2OLVL1

34E2 FFFC

OLVL2OLVL1

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

71/152

Page 72

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d)

10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal wi th a frequency a nd pul se length determined by the value of the OC1R and OC2R registers.

The Pulse Width Modulation mode uses the com plete Output Compare 1 funct ion plus the OC2R register, and so these functions cannot be used when the PWM mode is activated.

Procedure

To use Pulse Width Modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using th e formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the p ulse i f OLVL1= 0 and OLVL2=1, using the formula in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 18

Clock Control Bits).

If OLVL1=1 and O LVL2=0, t he length of t he pos itive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=OLVL2 a c ontinuous s ign al will be seen on the OCMP1 pin.

Pulse Width Modulation cycle

When

Counter

= OC1R

When

Counter = OC2R

OCMP1 = OLVL1

OCMP1 = OLVL2

Counter is reset

to FFFCh

The OC

R register value required for a specific timing application can be c alcul ated using the following f ormula:

R Value =

CPU

PRESC

- 5

Where: t = Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 18 Clock

Control Bits)

If the timer clock is an external clock the formula is:

OCiR = t

* fEXT

-5

Wher e: t = Signal or pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 45)

Notes:

1. After a write instruction to the OC

HR register,

the output compare function is inhibited until the

LR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode, therefore the Ou tput Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In PWM mode the ICAP1 pin c an not be used

to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also ge nerate an interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM ) and

One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

72/152

ICF1 bit is set

Page 73

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d)

10.4.4 Low Power Modes

Mode Description

WAIT

HALT

10.4.5 Interrupts

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF the counter value present when exiting from HALT mode is captured into the IC

Interrupt Event

pin, the input capture detection circuitry is armed. Consequent-

bit is set, and

R register.

Event

Flag

Enable

Control

Bit

ICIE

OCIE

Exit from Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt ev ents are co nnecte d to the same inte rrupt vector (see In terrupts chap-

ter). These events generate an interrupt if the correspo nding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse mode No Not Recommended PWM Mode No Not Recommended

See note 4 in Section 10.4.3.5 "One Pulse Mode" on page 70

See note 5 in Section 10.4.3.5 "One Pulse Mode" on page 70

See note 4 in Section 10.4.3.6 "Pulse Width Modulation Mode" on page 72

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

AVAILABLE RESO URC ES

No Partially No No

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ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d)

10.4.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the count er and the a lternate counter.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC 2E bit is set and even if there is no successful compariso n.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 3 = FOLV1 This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and e ven if there i s no successful comparison.

Bit 2 = OLVL2

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

This bit is copied to the OCMP2 pin whenev er a successful compa rison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.

Bit 1 = IEDG1

Bit 6 = OCIE 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Output Compare Interrupt Enable.

Timer Overflow Interrupt Enable.

This bit determines wh ich type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = OLVL1 The OLVL1 bi t is c opied to t he OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC 1E bit is s et in the CR2

Forced Output Compare 1.

Output Level 2.

Input Edge 1.

Output Level 1.

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Page 75

ST72311R, ST72511R, ST72532R

16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM 0: PWM mode is not active. 1: PWM mode is active, the OCMP 1 pin outputs a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Pulse Width Modulation.

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse mode.

0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is g iven by the I EDG1 bit. Th e length of the generated pulse depends on the contents of the OC1R register.

Bits 3:2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 18. Clock Control Bits

Timer Clock CC1 CC0

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

CPU

External Clock (where

available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines wh ich type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines wh ich type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

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16-BIT TIMER (Cont’d) STATUS REGISTER (SR)

Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.

ICF1 OCF1 TOF ICF2 OCF2 0 0 0

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached th e OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the lo w byte of the IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value). 1: The content of the free running counter matches

the content of the OC1R regis ter. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value). 1: The free running counter has rolled over from

FFFFh to 0000h. To clear this bit, first read the SR register, then read or write t he low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value). 1: The content of the free running counter matches

the content of the OC2R regis ter. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Bit 2-0 = Reserved, forced by hardware to 0.

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

MSB LSB

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit re gister tha t co ntains t he hi gh part of the value to be compared to the CHR register.

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

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16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that cont ains the high part of the value to be compared to the CHR register.

ST72311R, ST72511R, ST72532R

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister tha t co ntains t he hi gh part of the counter value.

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does no t clear the T OF bit in SR register.

MSB LSB

COUNTER HIGH REGISTER (CHR)

MSB LSB

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that cont ains the high part of the counter value.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only

Reset Value: Undefined This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

MSB LSB

Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

MSB LSB

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

MSB LSB

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16-BIT TIMER (Cont’d) Table 19. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Timer A: 32 Timer B: 42

Timer A: 31 Timer B: 41

Timer A: 33 Timer B: 43SRReset Value

Timer A: 34 Timer B: 44

Timer A: 35 Timer B: 45

Timer A: 36 Timer B: 46

Timer A: 37 Timer B: 47

Timer A: 3E Timer B: 4E

Timer A: 3F Timer B: 4F

Label

CR1

Reset Value

CR2

Reset Value

ICHR1

Reset Value

ICLR1

Reset Value

OCHR1

Reset Value

OCLR1

Reset Value

OCHR2

Reset Value

OCLR2

Reset Value

76543210

ICIE

OC1E

ICF1

MSB

OCIE

OC2E

OCF1

------

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

PWM

ICF2

CC1

OCF2

CC0

IEDG20EXEDG

LSB

Timer A: 38 Timer B: 48

Timer A: 39 Timer B: 49

Timer A: 3A Timer B: 4A

Timer A: 3B Timer B: 4B

Timer A: 3C Timer B: 4C

Timer A: 3D Timer B: 4D

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

ICHR2

Reset Value

ICLR2

Reset Value

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

MSB

------

LSB

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Page 79

10.5 SERIAL PERIPHE R AL IN TE R FACE ( SPI)

ST72311R, ST72511R, ST72532R

10.5.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

The SPI is normally us ed for communication between the microcontroller and external peripherals or another microcontroller.

Refer to the Pin Description chapter for the devicespecific pin-out.

10.5.2 Main Features

■ Full duplex, three-wire synchronous transfers

■ Master or slave operation

■ Four master mode frequencies

■ Maximum slave mode frequency = f

■ Four programmable master bit rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collision flag protection

■ Master mode fault protection capability.

CPU

/4.

10.5.3 General description

The SPI is connect ed to external d evices through 4 alternate pins:

– MISO: Master In Slave Out pin – MOSI: Master Out Slave In pin – SCK: Serial Clock pin –SS

: Slave select pin

A basic example of interconnections between a single master and a single slave is illustrated on

Figure 46.

The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first).

When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is prov ided by the m aster device via the SCK pin).

Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and recei ve r-full bits. A s tatus f lag is used to indicate that the I/O operation is complete.

Four possible data/clock timing relationship s may be chosen (s ee Figure 49) but m aster and slave must be programmed with the same timing mode.

Figure 46. Serial Peripheral Interface Master/Slave

MASTER

MSBit LS Bit MSBit L SBit 8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

MISO

MOSI

SCK

+5V

MISO

MOSI

SCK

SLAVE

8-BIT SHIFT REGISTE R

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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 47. Serial Peripheral Interface Block Diagram

Internal Bus

MOSI

MISO

SCK

Read

Read Buffer

8-Bit Shift Register

Write

MASTER

CONTROL

WCOL

SPIF

SPIE SPE SPR2 MSTR CPHA SPR0SPR1CPOL

MODF

- --

SPI

STATE

CONTROL

request

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SERIAL CLOCK GENERATOR

Page 81

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4 Functional Description

Figure 46 shows the serial peripheral interface

(SPI) block diagram. This interface contains 3 dedicated registers:

– A Control Register (CR) – A Status Register (SR) – A Data Register (DR)

Refer to the CR, SR and DR registers in Section

10.5.7for the bit definitions.

ST72311R, ST72511R, ST72532R

In this configuration t he M OSI pin is a data output and to the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is written the DR register.

The data byte is parallel loaded into the 8-bit shift register (from th e i nte rna l bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first.

10.5.4.1 Master Configuration

In a master configuration, the serial clock is generated on the SCK pin.

Procedure

– Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

– Select the CPOL and CPHA bits to define one

of the four relationships between the data transfer and the serial clock (see Figure 49).

–The SS

pin must be connected to a high level signal during the complete byte tran smit sequence.

– The MSTR and SPE bits must be set (they re-

main set only if the SS

pin is connected to a

high level signal).

When data tr ansfer i s compl ete:

– The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SR registe r while the SPIF bit is set

2. A read to the DR register.

Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device.

The value of the SPR0 & SPR1 bits is not used for the data transfer.

Procedure

– For correct data transfer, the slave device

must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure

49.

–The SS

signal during the complete byte tran smit sequence.

– Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

In this configuration the MOSI pin is a data input and the MISO pin is a data output.

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serial ly t o the M ISO pi n m os t significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

pin must be conne cted to a lo w level

When data tr ansfer i s compl ete:

– The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SR registe r while the SPIF bit is set.

2.A read to the DR register.

Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 10.5.4.6).

Depending on the CPHA bi t, the S S

pin has to be set to write to the DR regi ster between ea ch data byte transfer to avoid a write collision (see Section

10.5.4.4).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.3 Data Transfer Format

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses.

The SS

pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer.

Clock Phase and Clock Polarity

Four possible timing relationships may be chose n by software, using the CPOL and CPHA bits.

The CPOL (clock polarity) bit cont rols the steady state value of the clock when no data is being transferred. This bit affects both m as ter and sl av e modes.

The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge.

Figure 49, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between th e master and the slave device.

The SS

pin is the slave device select input and can

be driven by the master device.

ST72311R, ST72511R, ST72532R

The master device applies data to its MOSI pinclock edge before the capture clock edge.

CPHA bit is set

The second edge on the SCK pin (falling edg e if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition.

No write collision should occur even if the SS stays low during a transfer of s everal bytes (see

Figure 48).

CPHA bit is reset

The first edge on the SCK pin (falling edge if CPOL bit is set, rising ed ge if CPOL bit is reset ) is the MSBit capture strobe. Data is latched on the oc currence of the first clock transition.

The SS

pin must be toggled high and low between

each byte transmitted (see Figure 48). To protect the transmission from a write collision a

low value on the SS

pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS

pin must be high to write a new data byte in the DR without producing a write coll is ion .

Figure 48. CPHA / SS

MOSI/MISO

Master

Slave SS

(CPHA=0)

Slave

(CPHA=1)

Timing Dia gram

Byte 1 Byte 2

Byte 3

VR02131A

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ST72311R, ST72511R, ST72532R

SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 49. D at a C lo ck Ti m in g D i agram

SCLK ( w ith

CPOL = 1)

SCLK ( w ith CPOL = 0)

CPHA =1

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPOL = 1

CPOL = 0

MISO

(from master)

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

CPHA =0

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI

(from slave)

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

84/152

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

VR02131B

Page 85

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.4 Write Collision Error

A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external dev ice. When t his happens, the transfer continues uninterrupted; and the software w rit e w ill be uns u c c es s ful.

Write collisions can occur both in master and slave mode.

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.

In Slave mode

When the CPHA bit is set: The slav e device will re ceive a clock (S CK) ed ge

prior to the latch of the first data transfer. This first clock edge will freeze t he d ata in the slave device DR register and output the MSBit on to the external MISO pin of the slave device.

The SS

pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.

ST72311R, ST72511R, ST72532R

When the CPHA bit is reset: Data is latched on the occurrence of the first clock

transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its

pin has been pulled low.

SS For this reason, the SS

each data byte transfer, to allow the CPU to write in the DR register without generating a write collision.

In Master mode

Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer.

The SS

pin signal must be always high on the

master device.

WCOL bit

The WCOL bit in the SR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 50).

pin must be high, between

Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Read SR

THEN

Read DR Write DR

SPIF =0 WCOL=0

Read SR

THEN

SPIF =0 WCOL=0 WCOL=1 if a transfer has started

before the 2nd step

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

Read SR

Read DR

THEN

WCOL=0

Note: W riting to the DR register instead of readin g in it does not reset the WCOL bit

if no transfer has started

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS

Master mode fault affects the SPI peripheral in the following ways:

– The MODF bit is set and an SPI interrupt is

– The SPE bit is reset. This blocks all output

– The MSTR bit is reset, thus forcing the device

pin pulled low, then the MODF bit is set.

generated if the SPIE bit is set.

from the device and disables the SPI peripheral.

into slave mode.

may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set.

The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine.

Clearing the MODF bit is done through a software sequence:

1. A read or write access to the SR register while

the MODF bit is set.

2. A write to the CR register.

Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS

pin must be pulled high during the clearing se-

quence of the MODF bit. The SPE and MSTR bits

10.5.4.6 Overrun Condition

An overrun condition occurs w hen the mas ter device has sent several data bytes and the slave device has not cleared the S PIF bit issuing from the previous data byte transmitted.

In this case, the rec eiver buffer contains the b yte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost.

This condition is not detected by the SPI peripheral.

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Page 87

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems: – Single Master System – Multimaster System

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written its DR regis-

Single Master System

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 51).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS

The SS

pins of the slave devices.

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

ter. Other transmission security methods can use

ports for handshake lines or data by tes with command fields.

Multi-master System

A multi-master system may al so be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit

Note: T o prevent a b us conflict on the MISO line

in the SR register.

the master allows only one active slave device during a transmission.

ST72311R, ST72511R, ST72532R

Fig u re 51. Si ngle Master Con figuration

SCK

Slave MCU

MOSI

MISO

MOSI MOSI MOSIMISO MISO MISOMISO

SCK

Master

MCU

Ports

Slave MCU

SCK SCK

Slave MCU

MCU

Slave

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ST72311R, ST72511R, ST72532R

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5 Low Power Modes

Mode Description

WAIT

HALT

10.5.6 Interrupts

No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with

“exit from HALT mode” capability.

Interrupt Event

SPI End of Transfer Event SPIF Master Mode Fault Event MODF Yes No

Event

Flag

Enable

Control

Bit

SPIE

Exit from Wait

Yes No

Note: The SPI interrupt even ts are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt ma sk in the CC register is reset (RIM instruction).

Exit

from

Halt

88/152

Page 89

ST72311R, ST72511R, ST72532R

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.7 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0000xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE

Serial peripheral interrupt enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 6 = SPE

Serial peripheral output enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.5.4.5 "Master Mode Fault" on

page 86).

0: I/O port connected to pins 1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.

Bit 3 = CPOL

Clock polarity.

This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin.

Bit 2 = CPHA

Clock phase.

This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 1:0 = SPR[1:0]

Serial peripheral rate.

These bits are set and c leared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master.

These 2 bits have no effect in slave mode.

Table 20. Serial P eri pheral Baud Rate

Bit 5 = SPR2

Divider Enable

this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 20. 0: Divider by 2 enabled 1: Divider by 2 disabled

Bit 4 = MSTR

Master.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.5.4.5 "Master Mode Fault" on

page 86).

0: Slave mode is selected 1: Master mode is selected, the function of the

SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Serial Clock SPR2 SPR1 SPR0

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

CPU

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Page 90

ST72311R, ST72511R, ST72532R

SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR)

Read Only Reset Value: 0000 0000 (00h)

DATA I/O REGISTER (DR)

Read/Write Reset Value: Undefined

SPIFWCOL-MODF----

Bit 7 = SPIF

Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the DR register are inhibited.

Bit 6 = WCOL

Write Collision status.

This bit is set by hardware when a write to the DR

D7 D6 D5 D4 D3 D2 D1 D0

The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle t he SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

Warning:

A write to the DR regis ter places da ta directly into the shift register for transmission.

A read to the the DR register returns the v alue located in the buffer and not the contents of the shift

register (See Figure 47 ). register is done during a transmit sequence. It is cleared by a software sequence (see Fi gure 50). 0: No write collision occurred 1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF

Mode Fault flag.

This bit is set by hardware when the SS pin is pulled low in master mode (see Section 10. 5.4.5

"Master Mode Fault" on page 86). An SPI i nterrupt

can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bits 3-0 = Unused.

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Page 91

SERIAL PERIPHERAL INTERFACE (Cont’d) Table 21. SPI Register Map and Reset Values

ST72311R, ST72511R, ST72532R

Address

(Hex.)

0021h

0022h

0023h

Label

SPIDR

Reset Value

SPICR

Reset Value

SPISR

Reset Value

76543210

MSB

xxxxxxx

SPIE

SPIF

SPE

WCOL

SPR20MSTR0CPOL

CPHA

MODF

00000

SPR1

LSB

SPR0

91/152

Page 92

ST72311R, ST72511R, ST72532R

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.6.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an indust ry stand ard NRZ asynchronous

serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

10.6.2 Main Features

■ Full duplex, asynchronous communi cations

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

■ Independently programmable transmit and

receive baud rates up to 250K baud using conventional baud rate generator and up to 500K baud using the extended baud rate generator.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB) – Idle line

■ Muting function for multiprocessor configurations

■ LIN compatible (if MCU clock frequency

tolerance

■ Separate enable bits for Transmitter and

≤2%)

Receiver

■ Three error detection flags:

– Overrun error – Noise error – Frame error

■ Five interrupt sources with flags:

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

10.6.3 General Description

The interface is externally connected to another

device by two pins (see Figure 2.):

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through this pins, serial data is transmitted and re-

ceived as frames comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

– A conventional type for commonly-use d baud

rates,

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard oscillator frequencies.

10.6.4 LIN Protocol support

For LIN applications where resynchronization is

not required (application clock t olerance less than

or equal to 2%) the LIN protocol can be efficiently

implemented with this standard SCI.

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Page 93

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 52. SCI Block Diagram

ST72311R, ST72511R, ST72532R

TDO

RDI

Write

Transmit Data Register (TDR)

Transmit Shift Register

TRANSMIT

CONTROL

CR2

WAKE

UNIT

Read

Received Data Register (RDR)

Received Shift Register

SBKRWURETEILIERIETCIETIE

WAKE

RECEIVER

CONTROL

TDRE TC RDRF

(DATA REGISTER) DR

CR1

IDLE OR NF FE -

RECEIVER

CLOCK

CPU

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

/16

/PR

TRANSMITTER RATE

CONTROL

BRR

SCP1

CONVENTIONAL BAUD RATE GENERATOR

SCP0

SCT2

SCT1SCT0SCR2 SCR1SCR0

RECEIVER RATE CONTRO L

93/152

Page 94

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Functional Description

The block diagram of the S erial Control Interface, is shown in Figure 1.. It contains 6 dedicated registers:

– Two control registers (CR1 & CR2) – A status register (SR) – A baud rate register (BRR) – An extended pres caler receiver register (ERPR) – An extended prescaler transmitter register (ETPR) Refer to the register descriptions in Section 0.1.8

for the definitions of each bit.

Figure 53. Word length programming

10.6.5.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the CR1 register

(see Figure 1.).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame

of “1”s followed by t he start bit of the n ext frame

which contains data.

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transm itter inserts an ex-

tra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their

own baud rate generator.

9-bit Word length (M bit is set)

Data Frame

Start

Bit

Bit0 Bit1

Bit2

Bit3 Bit4

Idle Frame

Break Frame

8-bit Word length (M bit is reset)

Data Frame

Start

Bit

Bit0 Bit1

Bit2

Bit3 Bit4

Idle Frame

Break Fram e

Bit5 Bit6

Possible

Parity

Bit

Bit7 Bit8

Possible

Parity

Bit

Bit7

Stop

Bit

Next Data Frame

Start

Stop

Bit

Start

Bit

Extra

’1’

Next Data Frame

Next Start

Bit

Start

Bit

Start

Extra

’1’

Bit

Start

Bit

94/152

Page 95

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. W hen the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on t he TDO pin. In this m ode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1.).

Procedure

– Sele ct the M bit to define the word length. – Select the desired baud rate using the BRR and

the ETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first transmission.

– Acc ess the SR register and write the data to

send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is a lways perf ormed by the following software sequence:

1. An access to the SR register

2. A write to the DR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The dat a transfer is beginning. – The next data can be written in the DR register

without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is ta king place, a write instruction to the DR register places the data directly in the shift register, the data trans mission starts, and the TDRE bit is immediately set.

ST72311R, ST72511R, ST72532R

When a frame trans mission is com plete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is set and

the I bit is cleared in the CCR register.

Clearing the TC bit is pe rformed by the following

software sequence:

1. An access to the SR register

2. A write to the DR register

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 2.).

As long as the SBK bit is set, the SCI send break

frames to the T DO pin. After clearing this bit by

software the SCI insert a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI t o send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

Note: Resetting and setting t he TE bit causes t he

data in the TDR register to be lost . Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the DR.

95/152

Page 96

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit i s set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 1.).

Procedure

– Sele ct the M bit to define the word length. – Select the desired baud rate using the BRR and

the ERPR registe r s.

– Set the RE bit, this enables the receiver which

begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception. Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SR register

2. A read to the DR register. The RDRF bit must be cleared before the end of t he

reception of the next character to avoid an overrun error.

Break Character

When a break charact er is rec eived, t he S CI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared.

When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SR register followed by a DR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between v alid inc oming dat a and noise.

When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the

DR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself generates an interrupt.

The NF bit is reset by a SR register read operation followed by a DR register read operation.

Framing E rror

A framing error is detected when: – The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the

DR register. – No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt. The FE bit is reset by a SR register read operation

followed by a DR register read operation.

96/152

Page 97

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

ETPR

EXTENDED TRANSMITTER PRESC AL ER REGISTER

ERPR

EXTENDED RECEIVER PRESCALER REGIST E R

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

CPU

/16

/2 /PR

RECEIV ER RA T E

SCP1

TRANSMITTER RATE

CONTROL

SCT2

SCP0

SCT1SCT0SCR2 SCR1SCR0

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

TRANSMITTER

CLOCK

BRR

RECEIVER

CLOCK

97/152

Page 98

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5.4 Conventional Baud Rate Generation

The baud rate for the receiver a nd trans mitter (Rx and Tx) are set independent ly and calculated as follo ws:

(32

CPU

PR)*RR

Tx =

(32

CPU

PR)*TR

Rx =

with: PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT0, SCT1 & SCT2 bit s ) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR0,SCR1 & SCR2 bits) All this bits are in the BRR register. Example: If f

is 8 MHz (normal mode) and if

CPU

PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 baud.

Caution: The baud rate registers M UST NOT b e written to (changed o r refreshed) while the t ransmitter or the receiver is enabled.

10.6.5.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.

The extended baud rat e generator block diagram is described in the Figure 3..

The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register.

Note: the extended prescaler is activated by setting the ETPR or ERPR register to a value other

than zero. The baud rates are calculated as follows:

Tx =

CPU

ETPR

Rx =

CPU

ERPR

with: ETPR = 1,..,255 (see ETPR register) ERPR = 1,.. 255 (see ERPR register)

10.6.5.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often des irable that only the intended message recipient should actively receive the f ull me ssag e cont ents, thus reducing redundant SCI service overhead for all non addressed receivers.

The non addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU b it by software puts the SCI in sleep mode:

All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the

following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RW U bit and sets the RDRF bit, which allows the receiver to receiv e thi s word normally and to use it as an address word.

98/152

Page 99

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.6 Low Power Modes Mode Description

WAIT

HALT

10.6.7 Interrupts

Transmit Data Register Empty TDRE TIE Yes No Transmission Complete TC TCIE Yes No Received Data Ready to be Read RDRF Overrrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No

No effect on SCI. SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Enable

Control

Bit

RIE

Interrupt Event

Event

Flag

Exit from Wait

Yes No

Exit

from

Halt

The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

99/152

Page 100

ST72311R, ST72511R, ST72532R

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.8 Register Description STATUS REGISTER (SR)

Read Only Reset Value: 1100 0000 (C0h)

Note: The I DLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode.

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently

TDRE TC RDRF IDLE OR NF FE

being received in the s hift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generate d i f RIE=1 in th e CR2 reg-

Bit 7 = TDRE This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register

Note: data will not be transferred to the shift register as long as the TDRE bit is not reset.

Transmit data register empty.

ister. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected

Note: When this bit is set RDR regi ster content will not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SR register followed by a

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generat ed if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register).

read to the DR register). 0: No noise is detected 1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

0: Transmission is not complete 1: Transmission is complete

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchroniza-

Bit 5 = R DRF

Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read

tion, excessive noise or a b reak character is detected. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a I dle Line is de-

overrun error, it will be transferred and only the OR bit will be se t.

tected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a

Bit 0 = Unused.

read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected

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Datasheet ST72311R, ST72511R, ST72532R Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual