DATASHEET ST7032 DATASHEET (Sitronix)

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Sitronix ST7032

Dot Matrix LCD Controller/Driver

n Features

l 5 x 8 dot matrix possible l Low power operation support:

-- 2.7 to 5.5V

l Range of LCD driver power

-- 3.0 to 7.0V

l 4-bit, 8-bit, serial MPU or 400kbits/s fast

I2C-bus interface are available

l 80 x 8-bit display RAM (80 characters max.) l 10,240-bit character generator ROM for a

total of 256 character fonts(max)

l 64 x 8-bit character generator RAM(max) l 16-common x 80-segment and 1-common x

80-segment ICON liquid crystal display driver

l 16 x 5 –bit ICON RAM(max)

l Wide range of instruction functions:

Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift, double height font

l Automatic reset circuit that initializes the

controller/driver after power on and external reset pin

l Internal oscillator(Frequency=540KHz) and

external clock

l Built-in voltage booster and follower circuit

(low power consumption )

l Com/Seg direction selectable l Multi-selectable for CGRAM/CGROM size l Instruction compatible to ST7066U and

KS0066U and HD44780

l Available in COG type

n Description

The ST7032 dot-matrix liquid crystal display controller can display alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4 / 8-bit with 6800-series or 8080-series, 3/4-line serial interface microprocessor. Since all the functions such as display RAM, character generator ROM/RAM and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be used with this controller/driver.

The ST7032 character generator ROM size is 256 5x8dot bits which can be used to generate 256 different character fonts (5x8dot).

The ST7032 is suitable for low voltage supply (2.7V to

5.5V) and is perfectly suitable for any portable product which is driven by the battery and requires low power consumption.

The ST7032 LCD driver consists of 17 common signal drivers and 80 segment signal drivers. The maximum display RAM size can be either 80 characters in 1-line display or 40 characters in 2-line display. A single ST7032 can display up to one 16-character line or two 16-character lines.

The ST7032 dot-matrix LCD driver does not need extra cascaded drivers.

n Product Number

ST7032 supports various function for customer. Please specify correct product number for application: For example, “ST7032–0D” the first part is illustrated below and the second part is the identification code of the built-in character generation ROM. Please refer to the appendix for the character generation ROM code information.

ST7032

ST7032i IIC interface

Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.

6800-4bit / 8bit, 4-Line interface (without IIC interface)

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ST7032

ST7032 Serial Specification Revision History

Version

1.0 2003/3/24

1.1 2003/8/27 1. Include ST7032i

1.2 2005/10/17

1.2a 2006/05/23 1. Modify description mistake (Page 1)

1.3 2007/11/09

1.4 2008/08/18 Update I/O PAD Circuit

Date Description

1. Change “Version 0.1y-Preliminary” to “Version 1.0”

2. Modify Bias resistor value

3. Modify OSC frequency table

4. Adding Serial interface flow chart & example code

5. Adding “E” connection state for serial interface

1. To modify Operating Temperature Range Ta=-30°C to 85°C

2. To modify Storage Temperature Range Ta=-65°C to 150°C

3. To modify the vlcd voltage Range 3.0v~7.0v

4. To modify the limiting values -0.3v~+6.0v

5. To add Chip Thickness: 480 um

1. Add appendix section for Character Generation ROM.

2. Move ROM table to appendix.

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ST7032

n Pad Dimensions

Center on

(-2470,-445)

152

Center on

(2100,185)

(0,0)

Center on

(2470, -445)

139

138

35μm35μm

35μm

30μm 40μm

30μm30μm

30μm 30μm

30μm

Ø Chip Size: 5130.0 x 1080.0μm Ø Chip Thickness: 480μm Ø Bump Pitch : 62μm(min) Ø Bump Height : 17μm(Typ) Ø Bump Size :

l Pad No.1~54 : 54 x 97μm l Pad No.55~152 : 40 x 97μm

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ST7032

n Pad Location Coordinates

Pad No. Function

1 XRESET 2165.5 420.5 41 EXT -874.5 420.5 2 OSC1 2089.5 420.5 42 VSS -950.5 420.5 3 OSC2 2013.5 420.5 43 CLS -1026.5 420.5 4 RS 1937.5 420.5 44 CAP1N -1102.5 420.5 5 CSB 1861.5 420.5 45 CAP1N -1178.5 420.5 6 RW 1785.5 420.5 46 VOUT -1254.5 420.5 7 E 1709.5 420.5 47 VOUT -1330.5 420.5 8 DB0 1633.5 420.5 48 V0 -1406.5 420.5

9 DB1 1557.5 420.5 49 V0 -1482.5 420.5 10 DB2 1481.5 420.5 50 V1 -1558.5 420.5 11 DB3 1405.5 420.5 51 V2 -1634.5 420.5 12 DB4 1329.5 420.5 52 V3 -1710.5 420.5 13 DB5 1253.5 420.5 53 V4 -1786.5 420.5 14 DB6 1177.5 420.5 54 NC -1862.5 420.5 15 DB7 1101.5 420.5 55 COM[8] -2445.5 423 16 VSS 1025.5 420.5 56 COM[7] -2445.5 361 17 VSS 949.5 420.5 57 COM[6] -2445.5 299 18 VSS 873.5 420.5 58 COM[5] -2445.5 237 19 OPF1 797.5 420.5 59 COM[4] -2445.5 175 20 OPF2 721.5 420.5 60 COM[3] -2445.5 113 21 OPR1 645.5 420.5 61 COM[2] -2445.5 51 22 OPR2 569.5 420.5 62 COM[1] -2445.5 -11 23 SHLC 493.5 420.5 63 COMI1 -2445.5 -73 24 SHLS 417.5 420.5 64 SEG[1] -2445.5 -135 25 VDD 341.5 420.5 65 SEG[2] -2445.5 -197 26 VDD 265.5 420.5 66 SEG[3] -2445.5 -259 27 VDD 189.5 420.5 67 SEG[4] -2445.5 -321 28 VIN 113.5 420.5 68 SEG[5] -2445.5 -383 29 VIN 37.5 420.5 69 SEG[6] -2130.5 -420.5 30 TEST1 -38.5 420.5 70 SEG[7] -2068.5 -420.5 31 TEST2 -114.5 420.5 71 SEG[8] -2006.5 -420.5 32 VSS -190.5 420.5 72 SEG[9] -1944.5 -420.5 33 NC -266.5 420.5 73 SEG[10] -1882.5 -420.5 34 VOUT -342.5 420.5 74 SEG[11] -1820.5 -420.5 35 VOUT -418.5 420.5 75 SEG[12] -1758.5 -420.5 36 PSB -494.5 420.5 76 SEG[13] -1696.5 -420.5 37 VSS -570.5 420.5 77 SEG[14] -1634.5 -420.5 38 PSI2B -646.5 420.5 78 SEG[15] -1572.5 -420.5 39 CAP1P -722.5 420.5 79 SEG[16] -1510.5 -420.5 40 CAP1P -798.5 420.5 80 SEG[17] -1448.5 -420.5

X Y Pad No. Function

X Y

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ST7032

Pad No. Function

81 SEG[18] -1386.5 -420.5 121 SEG[58] 1093.5 -420.5 82 SEG[19] -1324.5 -420.5 122 SEG[59] 1155.5 -420.5 83 SEG[20] -1262.5 -420.5 123 SEG[60] 1217.5 -420.5 84 SEG[21] -1200.5 -420.5 124 SEG[61] 1279.5 -420.5 85 SEG[22] -1138.5 -420.5 125 SEG[62] 1341.5 -420.5 86 SEG[23] -1076.5 -420.5 126 SEG[63] 1403.5 -420.5 87 SEG[24] -1014.5 -420.5 127 SEG[64] 1465.5 -420.5 88 SEG[25] -952.5 -420.5 128 SEG[65] 1527.5 -420.5 89 SEG[26] -890.5 -420.5 129 SEG[66] 1589.5 -420.5 90 SEG[27] -828.5 -420.5 130 SEG[67] 1651.5 -420.5 91 SEG[28] -766.5 -420.5 131 SEG[68] 1713.5 -420.5 92 SEG[29] -704.5 -420.5 132 SEG[69] 1775.5 -420.5 93 SEG[30] -642.5 -420.5 133 SEG[70] 1837.5 -420.5 94 SEG[31] -580.5 -420.5 134 SEG[71] 1899.5 -420.5 95 SEG[32] -518.5 -420.5 135 SEG[72] 1961.5 -420.5 96 SEG[33] -456.5 -420.5 136 SEG[73] 2023.5 -420.5 97 SEG[34] -394.5 -420.5 137 SEG[74] 2085.5 -420.5 98 SEG[35] -332.5 -420.5 138 SEG[75] 2147.5 -420.5 99 SEG[36] -270.5 -420.5 139 SEG[76] 2445.5 -383

100 SEG[37] -208.5 -420.5 140 SEG[77] 2445.5 -321 101 SEG[38] -146.5 -420.5 141 SEG[78] 2445.5 -259 102 SEG[39] -84.5 -420.5 142 SEG[79] 2445.5 -197 103 SEG[40] -22.5 -420.5 143 SEG[80] 2445.5 -135 104 SEG[41] 39.5 -420.5 144 COM[9] 2445.5 -73 105 SEG[42] 101.5 -420.5 145 COM[10] 2445.5 -11 106 SEG[43] 163.5 -420.5 146 COM[11] 2445.5 51 107 SEG[44] 225.5 -420.5 147 COM[12] 2445.5 113 108 SEG[45] 287.5 -420.5 148 COM[13] 2445.5 175 109 SEG[46] 349.5 -420.5 149 COM[14] 2445.5 237 110 SEG[47] 411.5 -420.5 150 COM[15] 2445.5 299 111 SEG[48] 473.5 -420.5 151 COM[16] 2445.5 361 112 SEG[49] 535.5 -420.5 152 COMI2 2445.5 423 113 SEG[50] 597.5 -420.5 114 SEG[51] 659.5 -420.5 115 SEG[52] 721.5 -420.5 116 SEG[53] 783.5 -420.5 117 SEG[54] 845.5 -420.5 118 SEG[55] 907.5 -420.5 119 SEG[56] 969.5 -420.5 120 SEG[57] 1031.5 -420.5

X Y Pad No. Function

X Y

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ST7032

n Block Diagram

OSC1OSC2

XRESET

CLS

RS RW E

CSB

PSB

PSI2B

DB4 to DB7

Reset circuit

MPU

interface

Instruction

decoder

Address

counter

Data

(DR)

CPG

(AC)

Display data

RAM

(DDRAM)

80x8 bits

Timing

generator

80-bit

shift

16-bit

shift

80-bit

latch

circuit

Common

signal driver

Segment

signal driver

COM1 to COM16

COMI

SEG1 to SEG80

V0~V4

DB0 to DB3

SHLC SHLS

EXT

OPR1,2 OPF1,2

VSS

VDD

Input/

output

buffer

Busy

flag

Character

generator RAM

(CGRAM)

64 bytes

ICON RAM

80 bits

Character

generator ROM

(CGROM)

10.240 bits

Parallel/serial converter

and

attribute circuit

controller

Cursor

and

blink

LCD drive

voltage

follower

Voltage booster

circuit

VOUT

VIN

CAP1P CAP1N

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ST7032

onnect

(compatible to ST7066U, but

n Pin Function

Name Number I/O Interfaced with

XRESET 1 I MPU

RS 1 I MPU

R/W 1 I MPU

E 1 I MPU

CSB 1 I MPU

DB4 to DB7

DB0 to DB3

Ext 1 I ITO option

PSB 1 I MPU

PSI2B 1 I ITO option

OPR1,

OPR2

4 I/O

2 I ITO option

MPU

Function

External reset pin. Only if the power on reset used, the XRESET pin must be fixed to VDD. Low active. Select registers. 0: Instruction register (for write)

Busy flag & address counter (for read) 1: Data register (for write and read) Select read or write (In parallel mode). 0: Write 1: Read Starts data read/write. (“E” must connect to “VDD” when serial interface is selected.) Chip select in parallel mode and serial interface (Low active).When the CSB in falling edge state (in serial interface), the shift register and the clock counter are reset. Four high order bi-directional data bus pins. Used for data transfer and receive between the MPU and the ST7032. DB7 can be used as a busy flag. In serial interface mode DB7 is SI (input data), DB6 is SCL (serial clock). In I2C interface DB7 (SDA) is input data and DB6 (SCL) is clock input. SDA and SCL must connect to I2C bus (I2C bus is to c a resister between SDA/SCL and the power of I2C bus ). Four low order bi-directional data bus pins. Used for data transfer and receive between the MPU and the ST7032. These pins are not used during 4-bit operation. Extension instruction select: 0:enable extension instruction(add contrast/ICON/double height font/ extension instruction) 1:disable extension instruction without 5x11dot font) Interface selection 0:serial mode (“E” must connect to “VDD” when serial mode is selected.) 1:parallel mode(4/8 bit) In I2C interface PSB must connect to VDD

PSB PSI2B

0 0 No use 0 1 SI4 1 0 SI2 (I2C ) 1 1 Parallel 68

Character generator select:

OPR1 OPR2

0 0 240 8 0 1 250 6 1 0 248 8 1 1 256 0

Interface

CGROM CGRAM

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ST7032

or between this

Name Number I/O Interfaced with

Common signals direction select:

SHLC 1 I ITO option

SHLS 1 I ITO option

COM1 to

COM16

COMI 2 O LCD ICON common signals

SEG1 to

SEG80

OPF1 OPF2

CAP1P 1 - Power supply CAP1N 1 - Power supply

16 O LCD

80 O LCD Segment signals

2 I ITO option

0:Com1~16←Row address 15~0(Invert) 1:Com1~16←Row address 0~15(Normal) Segment signals direction select: 0:Seg1~80←Column address 79~0(Invert) 1:Seg1~80←Column address 0~79(Normal) Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 or 1/9 duty factor

The built-in voltage follower circuit selection

OPF1 OPF2

0 0 Built-in voltage follower(only use at EXT=0) 0 1 Built-in bias resistor(3.3KΩ) ±30% 1 0 Built-in bias resistor(9.6KΩ) ±30%

1 1 External bias resistor select For voltage booster circuit(VDD-VSS) External capacitor about 0.1u~4.7uf

Function

Bias select

VIN 1 - Power supply Input the voltage to booster

VOUT 1 - Power supply

V0 to V4 5 - Power supply

VDD

VSS

CLS I ITO option

OSC1 OSC2

TEST1,2 2 I/O

2 - Power supply

2 I/O

Oscillation

Test pin TEST1,2 must connect to VDD.

DC/DC voltage converter. Connect a capacit terminal and VIN when the built-in booster is used. Power supply for LCD drive V0-Vss = 7V (Max) Built-in/external Voltage follower circuit VDD : 2.7V to 5.5V, VSS: 0V

Internal/External oscillation select 0:external clock 1:internal oscillation When the pin input is an external clock, it must be input to OSC1.

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ST7032

n EXT option pin difference table

ST7066U normal mode (EXT=1) Extension mode (EXT=0)

Booster Always OFF ON/OFF control by instruction

Can’t use the follower circuit

Bias (V0~V4)

Contrast adjust Control by external VR

ICON RAM Can’t be use RAM size has 80 bit width (S1~S80).

Only use external resistor or internal resistor(1/5 bias)

Follower or internal/external resistor selectable

1. Control by instruction with follower

2. Control by external VR with internal/external resistor

Instruction Control normal instruction similar to ST7066U.

Double height font Only 5x8 font Can set 5x8 or 5x16 font

OSC frequency adjust Only adjust by external clock. Can set OSC frequency by instruction set.

Control extension instruction for low power consumption.

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ST7032

Instruction Write operation (MPU writes Instruction code

n Function Description

l System Interface

This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I2C interface. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR); the other is instruction register (IR).

The data register (DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data.

Using RS input pin to select command or data in 4-bit/8-bit bus mode.

RS R/W

I2C interface

It just only could write Data or Instruction to ST7032 by the IIC Interface. It could not read Data or Instruction from ST7032 (except Acknowledge signal).

SCL: serial clock input SDA: serial data input

Slaver address could only set to 0111110, no other slaver address could be set

The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data bit to the RAM. The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

BIT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.1.

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.3.

· Transmitter: the device, which sends the data to the bus

· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

· Slave: the device addressed by a master

L L

into IR) L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR)

Table 1. Various kinds of operations according to RS and R/W bits.

Operation

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ST7032

· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message

· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to

do so and the message is not corrupted

· Synchronization: procedure to synchronize the clock signals of two or more devices.

ACKNOWLEDGE

Acknowledge is not Busy Flag in I2C interface.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C Interface is illustrated in Fig.4.

SDA

SCL

SDA

SCL

SDA

SCL

START con ditionSTOP con dition

MASTER

TRANSMITTER/

RECEIVER

data line

stable;

data valid

Figure 1. Bit transfer

change of data

allowed

Figure 2. Definition of START and STOP conditions

SLAVE

RECEIVER (1)

0111100

Figure 3. System configuration

SLAVE

RECEIVER (2)

0111101

SLAVE

RECEIVER (3)

0111110

SLAVE

RECEIVER (4)

0111111

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ST7032

I2C Interface protocol The ST7032 supports command, data write addressed slaves on the bus. Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Only one 7-bit slave addresses (0111110) is reserved for the ST7032. The R/W is assigned to 0 for Write only. The I2C Interface protocol is illustrated in Fig.5.

The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7032i device. If the RS bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C INTERFACE-bus master issues a STOP condition (P).

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Figure 4. Acknowledgement on the 2-line Interface

START

condition

not acknowledge

acknowledge

clock pulse for

acknowledge ment

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ST7032

Instruction Write operation (MPU writes Instruction code

During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR).

The data register (DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data.

To select register, use RS input in I2C interface.

l Busy Flag (BF) When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.

l Address Counter (AC) Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.

Write mode

S 01111 1

slave address

0 1 Another control byte will follow the data byte unless a STOP condition is received.

RS R/W

L L H L Data Write operation (MPU writes data into DR)

acknowledgement

from ST7032i

1 0

R/W

01111

slave address

R S

1 0

acknowledgement

control byte

from ST7032i

2n>=0bytes

command word

acknowledgement

data byte

000000

control byte

from ST7032i

R S

acknowledgement

control byte

1 byte

D 7

from ST7032i

MSB.......................LSB

D6D5D4D3D2D1D

data byte

acknowledgement

data byte

n>=0bytes

Figure 5. 2-line Interface protocol

Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by a STOP condition. Co

Operation

into IR)

Table 2. Various kinds of operations according to RS and R/W bits.

from ST7032i

A P

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ST7032

l Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80

x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 7 for the relationships between DDRAM addresses and positions on the liquid crystal display.

The DDRAM address (ADD ) is set in the address counter (AC)as hexadecimal. Ø 1-line display (N = 0) (Figure 8)

When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7032, 16 characters are displayed. See Figure 8. When the display shift operation is performed, the DDRAM address shifts. See Figure 9.

High order bitsLow order bits

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Figure 7. DDRAM Address

Display Position (digit)

123456787980

DDRAM Address

Display Position DDRAM Address

00 01 02 03 04 05 ........ 4D 4E 4F

Figure 8. 1-Line Display

123416

00 01 02 03 .... 0F

Example : DDRAM Address 4F

1 0 0 1 1 1 1

For Shift Left

For Shift Right

Figure 9. 1-Line by 16-Character Display Example

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1001 02 03 04 ....

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ST7032

Ø 2-line display (N = 1) (Figure 10)

Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. See Figure

10.

Display Position

123456383940

DDRAM Address (hexadecimal)

Case 2: For a 16-character  2-line display See Figure 11. When display shift operation is performed, the DDRAM address shifts. See Figure 11.

Display Position

DDRAM Address

12345678910111213141516

00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47

00 01 02 03 04 05 ........ 25 26 27

40 41 42 43 44 45 ........ 65 66 67

Figure 10. 2-Line Display

08 09 0A 0B 0C 0D 0E 0F 48 49 4A 4B 4C 4D 4E 4F

0801 02 03 04 05 06 07

For Shift Left

For Shift Right

00 01 02 03 04 05 0627 40 41 42 43 44 45 4667

Figure 11. 2-Line by 16-Character Display Example

09 0A 0B 0C 0D 0E 0F 10

4841 42 43 44 45 46 47

0807 09 0A 0B 0C 0D 0E 4847 49 4A 4B 4C 4D 4E

5049 4A 4B 4C 4D 4E 4F

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l Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate 240/250/248/256 5 x 8 dot character patterns (select by OPR1/2 ITO pin). User-defined character patterns are also available by mask-programmed ROM.

l Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of code table (refer to appendix) to show the character patterns stored in CGRAM.

See Table 4 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM.

l ICON RAM In the ICON RAM, the user can rewrite icon pattern by program. There are totally 80 dots for icon can be written. See Table 5 for the relationship between ICON RAM address and data and the display patterns.

l Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area.(In I2C interface the reading function is invalid.)

l LCD Driver Circuit LCD Driver circuit has 17 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 17 bit common register, segment data also output through segment driver from 80 bit segment latch.

l Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter.

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0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 - 0 0 0 0 0 0 1 1 1 - - - 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 - 0 0 1 0 0 1 1 1 1 - - - 0 0 0 0 0

Character Code

(DDRAM Data)

b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Table 4. Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character

Notes:

1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).

2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bit will light up the 8th line regardless of the cursor presence.

3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).

4. As shown Table 4, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H.

5. “1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.

6. Different OPR1/2 ITO option can select different CGRAM size.

CGRAM

Address

patterns (CGRAM Data)

Character Patterns

(CGRAM Data)

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When SHLS=1, ICON RAM map refer below table

ICON address

D7 D6 D5 D4 D3 D2 D1 D0

00H - - - S1 S2 S3 S4 S5 01H - - - S6 S7 S8 S9 S10 02H - - - S11 S12 S13 S14 S15 03H - - - S16 S17 S18 S19 S20 04H - - - S21 S22 S23 S24 S25 05H - - - S26 S27 S28 S29 S30 06H - - - S31 S32 S33 S34 S35 07H - - - S36 S37 S38 S39 S40 08H - - - S41 S42 S43 S44 S45

09H - - - S46 S47 S48 S49 S50 0AH - - - S51 S52 S53 S54 S55 0BH - - - S56 S57 S58 S59 S60 0CH - - - S61 S62 S63 S64 S65 0DH - - - S66 S67 S68 S69 S70 0EH - - - S71 S72 S73 S74 S75 0FH - - - S76 S77 S78 S79 S80

When SHLS=0, ICON RAM map refer below table

ICON address

D7 D6 D5 D4 D3 D2 D1 D0

ICON RAM bits

00H - - - S80 S79 S78 S77 S76

01H - - - S75 S74 S73 S72 S71

02H - - - S70 S69 S68 S67 S66

03H - - - S65 S64 S63 S62 S61

04H - - - S60 S59 S58 S57 S56

05H - - - S55 S54 S53 S52 S51

06H - - - S50 S49 S48 S47 S46

07H - - - S45 S44 S43 S42 S41

08H - - - S40 S39 S38 S37 S36

09H - - - S35 S34 S33 S32 S31 0AH - - - S30 S29 S28 S27 S26 0BH - - - S25 S24 S23 S22 S21 0CH - - - S20 S19 S18 S17 S16 0DH - - - S15 S14 S13 S12 S11 0EH - - - S10 S9 S8 S7 S6 0FH - - - S5 S4 S3 S2 S1

Table 5. ICON RAM map

When ICON RAM data is filled the corresponding position displayed is described as the following table.

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Set DDRAM address to "00H" from

without

Whether during internal operation or

n Instructions

There are four categories of instructions that:

l Designate ST7032 functions, such as display format, data length, etc. l Set internal RAM addresses l Perform data transfer with internal RAM l Others

Ø instruction table at “Normal mode”

(When “EXT” option pin connect to VDD, the instruction set follow below table)

Instruction Code

Instruction

Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

Write "20H" to DDRAM. and set DDRAM address to "00H" from AC

Description

Instruction

Execution Time OSC= 380KHz

1.08 ms

OSC= 540kHz

0.76 ms

OSC= 700KHz

0.59 ms

Return Home

Entry Mode Set

Display ON/OFF

Cursor or Display Shift

Function Set Set CGRAM

Set DDRAM address

Read Busy flag and address

Write data to RAM Read data from RAM

0 0 0 0 0 0 0 0 1 x

0 0 0 0 0 0 0 1 I/D S

0 0 0 0 0 0 1 D C B

0 0 0 0 0 1 S/C R/L x x

0 0 0 0 1 DL N x x x

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Sets cursor move direction and specifies display shift. These operations are performed during data write and read. D=1:entire display on C=1:cursor on B=1:cursor position on S/C and R/L: Set cursor moving and display shift control bit, and the direction, changing DDRAM data.

DL: interface data is 8/4 bits N: number of line is 2/1

Set CGRAM address in address counter

Set DDRAM address in address counter

not can be known by reading BF. The contents of address counter can also be read. Write data into internal RAM (DDRAM/CGRAM) Read data from internal RAM (DDRAM/CGRAM)

1.08 ms

26.3 us 18.5 us 14.3 us

0.76 ms

0 0 0

Note: Be sure the ST7032 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7032. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time.

0.59 ms

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Set DDRAM address to "00H" from

*0 IS

Whether during internal operation or

control bit, and the direction, without

Internal OSC

Power/ICON

Ø instruction table at “Extension mode”

(when “EXT” option pin connect to VSS, the instruction set follow below table)

Instruction Code

Instruction

Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

Write "20H" to DDRAM. and set DDRAM address to "00H" from AC

Description

Instruction

Execution Time OSC= 380KHz

1.08 ms

OSC= 540kHz

0.76 ms

OSC= 700KHz

0.59 ms

Return Home

Entry Mode Set

Display ON/OFF

Function Set

Set DDRAM address

0 0 0 0 0 0 0 0 1 x

0 0 0 0 0 0 0 1 I/D S

0 0 0 0 0 0 1 D C B

0 0 0 0 1 DL N DH

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Read Busy flag and

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

address Write data

to RAM Read data from RAM

Note * : this bit is for test command , and must always set to “0”

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Instruction table 0(IS=0)

Cursor or Display Shift

Set CGRAM

0 0 0 0 0 1 S/C R/L x x

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Instruction table 1(IS=1)

frequency Set ICON

address

control/Contr

0 0

0 0 0 1 0 1 Ion Bon C5 C4

0 0 0 1 BS F2 F1 F0

0 1 0 0 AC3 AC2 AC1 AC0

ast set Follower

control Contrast set

0 0

0 1 1 0 Fon

0 1 1 1 C3 C2 C1 C0

Rab

AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Sets cursor move direction and specifies display shift. These operations are performed during data write and read. D=1:entire display on C=1:cursor on B=1:cursor position on DL: interface data is 8/4 bits N: number of line is 2/1 DH: double height font IS: instruction table select

Set DDRAM address in address counter

not can be known by reading BF. The contents of address counter can also be read. Write data into internal RAM (DDRAM/CGRAM/ICONRAM) Read data from internal RAM (DDRAM/CGRAM/ICONRAM)

S/C and R/L: Set cursor moving and display shift

changing DDRAM data. Set CGRAM address in address counter

BS=1:1/4 bias BS=0:1/5 bias F2~0: adjust internal OSC frequency for FR frequency. Set ICON address in address counter. Ion: ICON display on/off Bon: set booster circuit on/off C5,C4: Contrast set for internal follower mode. Fon: set follower circuit on/off Rab2~0: select follower amplified ratio. Contrast set for internal follower mode.

1.08 ms

26.3 us 18.5 us 14.3 us

0.76 ms

0 0 0

0.59 ms

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n Instruction Description

l Clear Display

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 00 00 10

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1").

l Return Home

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 00 00 X1

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM do not change.

l Entry Mode Set

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 00 10 SI/D

Set the moving direction of cursor and display.

Ø I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM.

Ø S: Shift of entire display

When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1": shift left, I/D = "0" : shift right).

S I/D Description

H H Shift the display to the left H L Shift the display to the right

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l Display ON/OFF

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 00 D1 BC

Control display/cursor/blink ON/OFF 1 bit register.

Ø D : Display ON/OFF control bit

When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM.

Ø C : Cursor ON/OFF control bit

When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

Ø B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off.

Alternating

display

Every

64 frames

Cursor

l Cursor or Display Shift

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 10 R/LS/C XX

Ø S/C: Screen/Cursor select bit

When S/C=”High”, Screen is controlled by R/L bit. When S/C=”Low”, Cursor is controlled by R/L bit.

Ø R/L: Right/Left

When R/L=”High”, set direction to right.

When R/L=”Low”, set direction to left.

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed.

S/C R/L Description AC Value

L L Shift cursor to the left AC=AC-1

L H Shift cursor to the right AC=AC+1 H L Shift display to the left. Cursor follows the display shift AC=AC H H Shift display to the right. Cursor follows the display shift AC=AC

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l Function Set

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 DL1 DHN IS0

Ø DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When in 4-bit bus mode, it needs to transfer 4-bit data by two times.

Ø N : Display line number control bit

When N = "High", 2-line display mode is set. When N = "Low", it means 1-line display mode.

Ø DH : Double height font type control bit

When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address can only use 00H~27H. When DH= “High” and N= “High”, it is forbidden. When DH = " Low ", display font is normal (5x8 dot).

N DH

L L 1 5x8 1 5x8

L H 1 5x8 1 5x16 H L 2 5x8 2 5x8 H H 2 5x8 Forbidden

EXT option pin connect to high EXT option pin connect to low

Display Lines Character Font Display Lines Character Font

2 line mode normal display (DH=0/N=1)

1 line mode with double height font (DH=1/N=0)

Ø IS : normal/extension instruction select

When IS=” High”, extension instruction be selected (refer extension instruction table) When IS=” Low”, normal instruction be selected (refer normal instruction table)

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l Set CGRAM Address

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 10 AC4AC5 AC2AC3 AC0AC1

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

l Set DDRAM Address

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 AC61 AC4AC5 AC2AC3 AC0AC1

Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H".

l Read Busy Flag and Address

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

10 AC6BF AC4AC5 AC2AC3 AC0AC1

When BF = “High”, indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.

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l Write Data to CGRAM,DDRAM or ICON RAM

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

01 D6D7 D4D5 D2D3 D0D1

Write binary 8-bit data to CGRAM, DDRAM or ICON RAM The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.

l Read Data from CGRAM,DDRAM or ICON RAM

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

11 D6D7 D4D5 D2D3 D0D1

Read binary 8-bit data from DDRAM/CGRAM/ICON RAM The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data.

※Read data must be “set address” before this instruction.

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l Bias selection/Internal OSC frequency adjust

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 00 10 F2BS F0F1

Ø BS: bias selection

When BS=”High”, the bias will be 1/4 When BS=”Low”, the bias will be 1/5 BS will be invalid when external bias resistors are used (OPF1=1, OPF2=1)

Ø F2,F1,F0 : Internal OSC frequency adjust

When CLS connect to high, that instruction can adjust OSC and Frame frequency.

Internal frequency adjust

F2 F1 F0 VDD = 3.0 V VDD = 5.0 V

0 0 0 122 120 0 0 1 131 133 0 1 0 144 149 0 1 1 161 167

1 0 0 183 192

1 0 1 221 227 1 1 0 274 277 1 1 1 347 347

Frame frequency ( Hz )

(2 line mode)

l Set ICON RAM address

400 350 300 250 200 150

Frame(Hz)

100

01234567

Instruction Step

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 10 00 AC2AC3 AC0AC1

Set ICON RAM address to AC. This instruction makes ICON data available from MPU. When IS=1 at Extension mode, The ICON RAM address is from "00H" to "0FH".

l Power/ICON control/Contrast set(high byte)

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 10 10 B

Ø Ion: set ICON display on/off

When Ion = "High", ICON display on. When Ion = "Low", ICON display off.

Ø Bon: switch booster circuit

Bon can only be set when internal follower is used (OPF1=0, OPF2=0). When Bon = "High", booster circuit is turn on.

C4C5

When Bon = "Low", booster circuit is turn off.

Ø C5,C4 : Contrast set(high byte)

C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage for LCD driver.

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l Follower control

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

00 10 01

Ø Fon: switch follower circuit

Fon can only be set when internal follower is used (OPF1=0,OPF2=0).

When Fon = "High", internal follower circuit is turn on. When Fon = "Low", internal follower circuit is turn off.

Ø Rab2,Rab1,Rab0 : V0 generator amplified ratio

Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.

l Contrast set(low byte)

Rab

R/WRSDB6DB7DB4DB5DB2DB3DB0DB1

Rab

00 10 11 C2C3 C0C1

Ø C3,C2,C1,C0:Contrast set(low byte)

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n Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the ST7032 when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1) until the initialization ends. The busy state lasts for 40 ms after VDD rises to stable.

1. Display clear

2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display DH=0; normal 5x8 font IS=0; use instruction table 0

3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off

4. Entry mode set:

I/D = 1; Increment by 1 S = 0; No shift

5. Internal OSC frequency (F2,F1,F0)=(1,0,0)

6. ICON control Ion=0; ICON off

7. Power control

BS=0; 1/5bias Bon=0; booster off Fon=0; follower off (C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0) (Rab2,Rab1,Rab0)=(0,1,0)

Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7032. When internal Reset Circuit not operate, ST7032 can be reset by XRESET pin from MPU control signal.

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n Initializing by Instruction

l 8-bit Interface (fosc=380KHz)

POWER ON and external reset

Wait time >40mS

After VDD stable

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function set

0 0 0 0 1 1 N DH X IS

Wait time >26.3μ S

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH X IS

Wait time >26.3μ S

Internal OSC frequency

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 BS F2 F1 F0

Wait time >26.3μ S

Contrast Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 1 C3 C2 C1 C0

Wait time >26.3μ S

BF cannot be checked before this instruction.

Power/ICON/Contrast control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 1 Ion

Wait time >26.3μ S

Bon C5 C4

Follower control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 Fon

Wait time >200mS

(for power stable)

Rab2 Rab1 Rab0

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

Wait time >26.3μ S

Initialization end

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Ø Initial Program Code Example For 8051 MPU(8 Bit Interface): ;--------------------------------------------------------------------------------INITIAL_START:

CALL HARDWARE_RESET CALL DELAY40mS MOV A,#38H ;FUNCTION SET CALL WRINS_NOCHK ;8 bit,N=1,5*7dot CALL DELAY30uS MOV A,#39H ;FUNCTION SET CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1 CALL DELAY30uS MOV A,#14H ;Internal OSC frequency adjustment CALL WRINS_CHK CALL DELAY30uS MOV A,#78H ; Contrast control CALL WRINS_CHK CALL DELAY30uS MOV A,#5EH ;Power/ICON/Contrast control CALL WRINS_CHK CALL DELAY30uS MOV A,#6AH ;Follower control CALL WRINS_CHK CALL DELAY200mS ;for power stable MOV A,#0CH ;DISPLAY ON CALL WRINS_CHK CALL DELAY30uS MOV A,#01H ;CLEAR DISPLAY CALL WRINS_CHK CALL DELAY2mS MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK ;CURSOR MOVES TO RIGHT

CALL DELAY30uS ;--------------------------------------------------------------------------------MAIN_START:

XXXX XXXX XXXX

XXXX ;--------------------------------------------------------------------------------- WRINS_CHK:

CALL CHK_BUSY WRINS_NOCHK:

CLR RS ;EX:Port 3.0

CLR RW ;EX:Port 3.1

SETB E ;EX:Port 3.2

MOV P1,A ;EX:Port 1=Data Bus

CLR E

MOV P1,#FFH ;For Check Busy Flag

RET ;--------------------------------------------------------------------------------- CHK_BUSY: ;Check Busy Flag

CLR RS

SETB RW

SETB E

JB P1.7,$

CLR E

RET

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l 4-bit Interface (fosc=380KHz)

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Ø Initial Program Code Example For 8051 MPU(4 Bit Interface): ;------------------------------------------------------------------INITIAL_START:

CALL HARDWARE_RESET CALL DELAY40mS MOV A,#38H ;FUNCTION SET CALL WRINS_ONCE ;8 bit, 5*7 dot CALL DELAY2mS

MOV A,#38H ;FUNCTION SET CALL WRINS_ONCE ;8 bit, 5*7 dot CALL DELAY30uS

CALL CHK_BUSY MOV A,#28H ;FUNCTION SET CALL WRINS_ONCE ; 4 bit, 5*7 dot CALL DELAY30uS

MOV A,#29H ;FUNCTION SET CALL WRINS_CHK ; 4 bit N = 1, 5*7 dot CALL DELAY30uS ; IS = 1

MOV A,#14H ;Internal OSC CALL WRINS_CHK CALL DELAY30uS

MOV A,#78H ;Contrast set CALL WRINS_CHK CALL DELAY30uS

MOV A,#5EH ;Power/ICON/Contrast CALL WRINS_CHK CALL DELAY30uS

MOV A,#6AH ;Follower control CALL WRINS_CHK CALL DELAY200mS ;For power stable

MOV A,#0CH ;DISPLAY ON CALL WRINS_CHK CALL DELAY30uS

MOV A,#01H ;CLEAR DISPLAY CALL WRINS_CHK CALL DELAY2mS

MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK

CALL DELAY30uS ;------------------------------------------------------------------MAIN_START:

XXXX XXXX XXXX

;------------------------------------------------------------------- WRINS_CHK:

WRINS_NOCHK:

WRINS_ONCE:

;------------------------------------------------------------------- CHK_BUSY: ;Check Busy Flag

. . . .

CALL CHK_BUSY PUSH A

ANL A,#F0H CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port1=Data Bus CLR E POP A SWAP A

ANL A,#F0H CLR RS CLR RW SETB E MOV P1,A CLR E MOV P1,#FFH ;For Check Bus Flag RET

PUSH A MOV P1,#FFH

CLR RS SETB RW SETB E MOV A,P1 CLR E MOV P1,#FFH CLR RS SETB RW SETB E NOP CLR E JB A.7,$1 POP A

RET

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ST7032

l Serial interface & IIC interface ( fosc = 380KHz )

POWER ON and external reset

Wait time >40mS

After VDD stable

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH 0 IS

Wait time >26.3μ S

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N DH 0 IS

Wait time >26.3μ S

Internal OSC frequency

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 BS F2 F1 F0

Wait time >26.3μ S

Contrast set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 1 C3 C2 C1 C0

Wait time >26.3μ S

Power/ICON/Contrast control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0 1 Ion

Wait time >26.3μ S

Bon C5 C4

Follower control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 0 Fon

Wait time >200mS (for power stable)

Rab2 Rab1 Rab0

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

Wait time >26.3μ S

Initialization end

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ST7032

Ø Initial Program Code Example For 8051 MPU(Serial Interface): ;--------------------------------------------------------------------------------INITIAL_START:

CALL HARDWARE_RESET

CALL DELAY40mS

MOV A,#38H ;FUNCTION SET

CALL WRINS_NOCHK ;8 bit,N=1,5*7dot

CALL DELAY30uS

MOV A,#39H ;FUNCTION SET

CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1

CALL DELAY30uS

MOV A,#14H ;Internal OSC frequency adjustment

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#78H ;Contrast set

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#5EH ;Power/ICON/Contrast control

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#6AH ;Follower control

CALL WRINS_NOCHK

CALL DELAY200mS ;for power stable

MOV A,#0CH ;DISPLAY ON

CALL WRINS_NOCHK

CALL DELAY30uS

MOV A,#01H ;CLEAR DISPLAY

CALL WRINS_NOCHK

CALL DELAY2mS

MOV A,#06H ;ENTRY MODE SET

CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT

CALL DELAY30uS ;--------------------------------------------------------------------------------MAIN_START:

XXXX XXXX XXXX XXXX . . .

;--------------------------------------------------------------------------------- WRINS_NOCHK:

PUSH 1 MOV R1,#8 CLR RS

RLC A MOV SI,C SET SCL NOP CLR SCL DJNZ R1,$1 POP 1

CALL DLY1.5mS RET

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ST7032

n Interfacing to the MPU

The ST7032 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fast I thus allowing interfacing with 4-bit, 8-bit or I

C MPU.

l For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3

are disabled. The data transfer between the ST7032 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data.

Ø Example of busy flag check timing sequence

C operation,

CSB

R/W

Internal

operation

DB7

Ø Intel 8051 interface(4 Bit)

Functioning

IR7IR3AC3

Busy flag checkBusy flag checkInstruction writeInstruction write

Not

AC3IR3IR7

Busy

COM1 to COM16

P1.0 to P1.3

P3.0 P3.1 P3.2

P3.3CSB

Intel 8051 SerialST7032

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DB4 to DB7

RS R/W E

SEG1 to SEG80

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ST7032

l For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

Ø Example of busy flag check timing sequence

CSB

R/W

Internal

operation

DB7

Ø Intel 8051 interface(8 Bit)

P1.0 to P1.7

Intel 8051 SerialST7032

Data

Instruction

write

P3.0 P3.1 P3.2

Functioning

Busy flag

check

BusyBusyData

Busy flag

check

COM1 to COM16

DB0 to DB7

RS R/W E

SEG1 to SEG80

CSBP3.3

Not

Busy

Busy flag

check

Instruction

write

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ST7032

l For serial interface data, only two bus lines (DB6 to DB7) are used.

Ø Example of timing sequence

CSB

D7D6D5D4D3D2D1D0D7D6D5D4D3D2

SCL

1234567891011121314

Note:The falling edge must cause on CSB before the serial clock ( SCL ) active.

Ø Intel 8051 interface(Serial)

P1.6 to P1.7

P3.0 P3.3

Intel 8051 SerialST7032

COM1 to COM16

SI , SCL

RS CSB

SEG1 to SEG80

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ST7032

l For I

Ø Example of timing sequence

SDA

C interface data, only two bus lines (DB6 to DB7) are used.

D7D6D5D4D3D2D1D0

ACK

. . . . . . .

ACK

SCL

Ø Intel 8051 interface( I

Intel 8051 SerialST7032

123456789

C )

P1.6 to P1.7SDA , SCL

COM1 to COM16

SEG1 to SEG80

. . . . . .

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ST7032

n Supply Voltage for LCD Drive

l When external bias resistors are used

(OPF1=1,OPF2=1)

VCC (2.7~ 5.5V)

OPF1OPF2 VOUT

VIN CAP1P

CAP1N

VDD

V1 V2

Vext

VR R

VSS

1/4 bias

GND

l When built-in bias resistors(9.6KΩ) are used

(OPF1=1,OPF2=0)

VLCD

VCC(2.7~5.5V)

VCC (2.7~ 5.5V)

OPF1OPF2 VOUT

VIN CAP1P CAP1N

1/5 bias

Vext

VDD

V0 V1

V2 V3 V4

VSS

Vext

VLCD

GND

OPF1 VOUT

VIN CAP1P

CAP1N

VDD

V0 V1

V2 V3

VLCD

OPF2

VSS

GND

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ST7032

l When built-in bias resistors(3.3KΩ) are used

(OPF1=0,OPF2=1)

OPF2 VOUT

VIN CAP1P

CAP1N

VCC (2.7~ 5.5V)

VDD

V0 V1

Vext

V3 V4

OPF1

VSS

GND

l When built-in voltage followers with external Vout are used

(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)

VLCD

Vext ≧ V0

VCC (2.7~ 5.5V)

VOUT

VIN

CAP1P CAP1N

OPF1 OPF2

VDD

V0 V1

V2 V3 V4

VSS

Don't need to connect stable capacitor when use internal follower circuit

VLCD

GND

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ST7032

l When built-in booster and voltage followers are used(OPF1=0,OPF2=0)

VIN

VOUT

CAP1P CAP1N

VCC (2.7~ 3.5V)

VDD

V0 V1

V2 V3 V4

Don't need to connect stable capacitor when use internal follower circuit

VOUT≦2xVDD

VDD=2.7~3.5V

VLCD

2 x step-up voltage relationships

VSS=0V

OPF1 OPF2

VSS

GND

Note: Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).

|Vout-V0|>0.5V(minimum)

Vout

VCC

GND

VDD

VSS

(System side)(ST7032Side)

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ST7032

Ø V0 voltage follower value calculation

Vout(≧VDD)VDD

Vref

V0=(1+

) Vref

VSS

While Vref=VDD (

α+36

100

)

C5 C4 C3 C2 C1 C0 α Rab2 Rab1 Rab0 1+Rb/Ra

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1.25 0 0 0 0 1 0 2 0 1 0 1.5

. .

0 1 1 1.8 1 0 0 2

1 0 1 2.5 1 1 1 1 0 1 61 1 1 0 3 1 1 1 1 1 0 62 1 1 1 3.75 1 1 1 1 1 1 63

13579111315171921232527293133353739414345474951535557596163

V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)

The recommended curve: follower = 04H

Notes:

1. Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.

2. If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.

3. internal built-in booster can only be used when OPF1=0,OPF2=0.

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ST7032

02468101214161820222426283032343638404244464850525456586062

V0 level

The recommanded curve: follower = 01H

(Condition:Booster on, Follower on, VIN = 3.5 V, VDD=5.0V, Display off)

Notes:

1. Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.

2. If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.

3. internal built-in booster can only be used when OPF1=0,OPF2=0.

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ST7032

n AC Characteristics

l 68 Interface

R/W

tAW6 tAH6

CSB

tCYC6

tEWH

tEWL

tr tf

tDS6 tDH6

D0 to D7

(Write)

tACC6 tOH6

D0 to D7

(Read)

( Ta = 25°C )

Item Signal Symbol Condition

VDD=2.7 to 4.5V

Rating

Min. Max. Min. Max.

VDD=4.5 to 5.5V

Rating

Units

Address hold time RS tAH6 Address setup time RS tAW6 System cycle time RS tCYC6 — Data setup time D0 to D7 Data hold time D0 to D7 Access time D0 to D7 Output disable time D0 to D7 Enable Rise/Fall time E tr,tf —

Enable H pulse time E tEWH Enable L pulse time E tEWL

Note: All timing is specified using 20% and 80% of VDD as the reference.

V1.4 2008/08/18

tDS6 tDH6

tACC6

tOH6

—

CL = 100 pF

— 200 - 120 -

— 150 - 130 -

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20 - 20 -

20 - 20 400 - 280 100 - 80 -

40 - 20 -

- 500 - 400

300 - 150 -

- 20 - 20

Page 45

ST7032

l Serial Interface

CSB

tCSS tCSH

tSAS tSAH

tSCYC

tSLW

SCL

tf tr

tSDS tSDH

VDD=2.7 to 4.5V

Item Signal Symbol Condition

Min. Max. Min. Max.

Serial Clock Period SCL “H” pulse width SCL “L” pulse width SCL Rise/Fall time SCL tr,tf — Address setup time Address hold time Data setup time Data hold time

CS-SCL time CS

SCL

tSCYC

tSHW tSLW

tSAS tSAH tSDS tSDH tCSS

—

tCSH

*1 All timing is specified using 20% and 80% of VDD as the standard.

200 - 100 -

20 - 20 -

160 - 120 -

10 - 10 -

250 - 150 -

10 - 10 10 - 20 20 - 20 -

350 - 200 -

tSHW

VDD=4.5 to 5.5V

Rating

- 20 - 20

Rating

( Ta = 25°C )

Units

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ST7032

load represent by each bus

l I2C interface

SDA

tBUF

tLOW

tHIGH

SCL

tDH;STA

tHD;DAT

SDA

tSU;STA

VDD=2.7 to 4.5V

Item Signal Symbol Condition

SCL clock frequency f SCL clock low period t SCL clock high period Data set-up time t Data hold time

SCL,SDA rise time t SCL,SDA fall time

Capacitive line Setup time for a repeated START condition

Start condition hold time

SCL

SCL,

SDA

DC 400 DC 400 KHz

SCLK

1.3

LOW

HIGH

SU;DAT

HD:DAT

—

— 0.6

SU;STA

— 0.6

HD;STA

—

Rating

Min. Max.

0.6

180

0 0.9 0 0.9 us 20+0.1Cb 20+0.1Cb

—

300 300

400

VDD=4.5 to 5.5V

—

— —

20+0.1Cb 20+0.1Cb

— —

tSU;DAT

SU;STO

( Ta = 25°C )

Rating

Min. Max.

1.3

0.6

100

—

0.6

—

— —

300 300

400 pf

— —

Units

us ns

us us

Setup time for STOP condition t Bus free time between a Stop and

START condition

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SCL

— 0.6

SU;STO

— 1.3

BUF

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—

0.6

1.3

—

Page 47

ST7032

l Internal Power Supply Reset

Notes:

w tOFF compensates for the power oscillation period caused by momentary power supply oscillations. w Specified at 4.5V for 5V operation,and at 2.7V for 3V operation. w If 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not operate normally.

l Hardware reset(XRESET)

2.7V/4.5V

0.2V0.2V0.2V

trcc

tOFF

tOFF≧1mS0.1mS≦trcc≦10mS

2.7V/4.5V

0.2V

tr100nS

≦

tL>100uS

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ST7032

n Absolute Maximum Ratings

Characteristics Symbol Value

Power Supply Voltage VDD -0.3 to +6.0

LCD Driver Voltage V

Input Voltage V

Operating Temperature T

Storage Temperature T

n DC Characteristics

( TA = 25℃ , VDD = 2.7 V – 4.5 V )

7.0- Vss to -0.3+Vss

LCD

-0.3 to VDD+0.3

-30oC to + 85oC

-65oC to + 150oC

STO

Symbol Characteristics

Test Condition Min. Typ. Max. Unit

VDD Operating Voltage - 2.7 - 4.5 V

LCD Voltage V0-Vss 2.7 - 7.0 V

LCD

VDD=3.0V

ICC Power Supply Current

(Use internal

- 160 230 uA

booster/follower circuit)

IH1

IL1

IH2

IL2

OH1

OL1

Input High Voltage

(Except OSC1)

Input Low Voltage

(Except OSC1)

Input High Voltage

(OSC1)

Input Low Voltage

(OSC1)

Output High Voltage

(DB0 - DB7)

Output Low Voltage

(DB0 - DB7)

- 1.9 - VDD

- - 0.3

0.7

VDD

- - -

IOH = -1.0mA

= 1.0mA - - 0.8 V

0.75

VDD

- 0.8 V

- VDD

0.2

VDD

- - V

OH2

COM

SEG

LEAK

PUP

Output High Voltage

(Except DB0 - DB7) Output Low Voltage

OL2

(Except DB0 - DB7)

Common Resistance V

Segment Resistance V

Input Leakage

Current

Pull Up MOS Current

= -0.04mA

IOL = 0.04mA - -

= 4V, Id = 0.05mA

LCD

= 4V, Id = 0.05mA

LCD

VIN = 0V to VDD -1 - 1 µA

VDD = 3V 20 30 40 µA

0.8

VDD

- VDD

0.2

VDD

- 2 20 KΩ

- 2 30 KΩ

fOSC Oscillation frequency VDD = 3V,1/17duty 350 540 1100 KHz

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ST7032

n DC Characteristics

( TA = 25℃, VDD = 4.5 V - 5.5 V )

Symbol Characteristics

VDD Operating Voltage V

LCD Voltage V0-Vss 2.7 - 7.0 V

LCD

ICC Power Supply Current

IH1

IL1

IH2

IL2

OH1

OL1

Input High Voltage

(Except OSC1)

Input Low Voltage

(Except OSC1)

Input High Voltage

(OSC1)

Input Low Voltage

(OSC1)

Output High Voltage

(DB0 - DB7)

Output Low Voltage

(DB0 - DB7)

Test Condition Min. Typ. Max. Unit

- 4.5 - 5.5 V

VDD=5.0V

(Use internal

booster/follower circuit)

- 2.7 - VDD

- -0.3 - 0.8 V

- - - 1.0 V

IOH = -1.0mA 3.8 - VDD

= 1.0mA - - 0.8 V

- 240 340 uA

0.7

VDD

- VDD

OH2

OL2

COM

SEG

LEAK

PUP

Output High Voltage (Except DB0 - DB7)

Output Low Voltage

(Except DB0 - DB7)

Common Resistance V Segment Resistance V

Input Leakage

Current

Pull Up MOS Current

= -0.04mA

IOL = 0.04mA - -

= 4V, Id = 0.05mA

LCD

= 4V, Id = 0.05mA

LCD

VIN = 0V to VDD -1 - 1 µA

VDD = 5V 65 95 125 µA

0.8

VDD

- VDD

0.2

VDD

- 2 20 KΩ

- 2 30 KΩ

fOSC Oscillation frequency VDD = 5V,1/17duty 350 540 1100 KHz

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ST7032

n LCD Frame Frequency

l 1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time

= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect to High)

COM1

COM2

200 clocks

1 2 3 4 16 1 2 3 4 16 1 2 3 4 16

V0 V1 V2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

COM16

SEGx off

SEGx on

V0 V1 V2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

1 frame

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ST7032

l 1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to High)

200 clocks

1 2 3 4 17 1 2 3 4 17 1 2 3 4 17

V0 V1 V2

COM1

COM2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

COM17

SEGx off

SEGx on

V0 V1 V2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

V0 V1 V2

V3 V4 Vss

1 frame

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ST7032

l 1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to

400 clocks

1 2 3 4 8 1 2 3 4 8 1 2 3 4 8

V0 V1

COM1

COM2

COM8

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

V0 V1

SEGx off

SEGx on

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

1 frame

High)

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ST7032

l 1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =

1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to

400 clocks

1 2 3 4 9 1 2 3 4 9 1 2 3 4 9

V0 V1

COM1

COM2

COM9

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

V0 V1

SEGx off

SEGx on

V2 V3

V4 Vss

V0 V1

V2 V3

V4 Vss

1 frame

High)

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Page 54

ST7032

n I/O Pad Configuration

PSB

PSB=1 => Pull-Up

PSB=0 => Floating

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ST7032

n LCD and ST7032 Connection

SHLC/SHLS ITO option pin can select at different direction for LCD panel

l Com normal direction/Seg normal direction

l Com normal direction/Seg reverse direction

l Com reverse direction/Seg normal direction

l Com reverse direction/Seg reverse direction

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ST7032

n Application Circuit(ST7066U normal mode)

Ø Use internal resistor(9.6K ohm) and contrast adjust with external VR. Ø Booster always off. Ø Has 240 character of CGROM and 8 characters of CGRAM Ø Internal oscillator.

Dot Matrix LCD Panel

Vext

VOUT VIN

CAP1N CAP1P

V0 V1 V2 V3 V4

Seg 1-80Com 1-16

ST7032

RS,R/W,E,CSB,DB0-DB7,XRESET

To MPU

VDD

CLS

SHLC

SHLS

EXT OPF1 OPF2

OPR1 OPR2

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ST7032

n Application Circuit(Extension mode)

Ø Use internal follower circuit. Ø Booster has 2 times pump. Ø Has 240 character of CGROM and 8 characters of CGRAM Ø Internal oscillator

Dot Matrix LCD Panel

Vext

VOUT VIN

Seg 1-80Com 1-17

CLS

SHLC

SHLS

CAP1N CAP1P

V0 V1 V2 V3 V4

ST7032

RS,R/W,E,CSB,DB0-DB7,XRESET

EXT OPF1 OPF2

OPR1 OPR2

To MPU

l When the heavy load is applied, the dotted line part could be added.

VDD

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Page 58

ST7032

n Application Circuit(for glass layout)

l ST7032 over Glass,6800 serial 8bit interface, with booster and follower circuit on

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Page 59

ST7032

l ST7032 over Glass,6800 serial 4bit interface, with booster and follower circuit on

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Page 60

ST7032

l ST7032 under Glass, serial interface, with booster and follower circuit on

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Page 61

ST7032

l ST7032i under Glass, IIC interface, with booster and follower circuit on

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Page 62

Appendix – Product Number

Product Number OPR1 OPR2 Support Character

ST7032-0D 1 1 English/Japan/European

Table A1. Correspondence between Character Codes and Character Patterns

Page 63

Table A2. Select display pattern in CGRAM or CGROM (use OPR1, OPR2)

Replaced By CGRAM Pattern

OPR2,OPR1=(0,0)

OPR2,OPR1=(0,1)

OPR2,OPR1=(1,1)OPR2,OPR1=(1,0)