Datasheet ST62T62CM6, ST62T62CM3, ST62T62CB6, ST62T62CB3, ST62T52CM6 Datasheet (SGS Thomson Microelectronics)

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November 1999 1/78

Rev. 2.7

ST62T52C

ST62T62C/E62C

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER AND EEPROM

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM: 64 bytes(noneonST62T52C)

■ User Programmable Options

■ 9 I/Opins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 5 I/Olines can sinkupto30mA todriveLEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timerwith 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator SafeGuard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 4 analog inputs

■ On-chip Clockoscillator canbe drivenbyQuartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port)

DEVICE SUMMARY

DEVICE

EPROM

(Bytes)

OTP

(Bytes)

EEPROM

ST62T52C 1836 ST62T62C 1836 64 ST62E62C 1836 64

(See end of Datasheet for Ordering Information)

PDIP16

PSO16

CDIP16W

SSOP16

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Table of Contents

Document

Page

ST62T52C/ST62T62C/E62C ............................1

1 GENERAL DESCRIPTION . .. . . . ................................................ 5

1.1 INTRODUCTION . . . . . .. . . . . . . ............................................ 5

1.2 PIN DESCRIPTIONS . . . . . . ................................................6

1.3 MEMORY MAP . . . . . . . . . . ................................................7

1.3.1 Introduction . . . ..................................................... 7

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . .................................. 8

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . ................................ 9

1.3.4 Stack Space . . . . . . . . . . . . ............................................9

1.3.5 Data Window Register (DWR) . ........................................10

1.3.6 Data RAM/EEPROM Bank Register (DRBR) . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.7 EEPROM Description . . . . . . . . . . . . . . .. . . . . ........................... 12

1.4 PROGRAMMING MODES . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.1 Option Bytes . . . . . . . . . . . . . . .. . . . . . . . . .............................. 14

1.4.2 Program Memory . . . ................................................ 14

1.4.3 . EEPROM Data Memory . . . . ......................................... 15

2 CENTRAL PROCESSING UNIT . . ............................................... 16

2.1 INTRODUCTION . . . . . .. . . . . . . ........................................... 16

2.2 CPU REGISTERS . . . .................................................... 16

3 CLOCKS, RESET, INTERRUPTS AND POWERSAVING MODES . . ...................18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . ........................................... 18

3.1.1 Main Oscillator . .. . . . . . . .. . . . . . . . . . ................................. 18

3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . 19

3.1.3 Oscillator Safe Guard . . . . . ...........................................19

3.2 RESETS . . . . . . . . .. . .. . . . . . . . . .. . . . . . . . . . .. . . . .. . . . .. . . . .. . . . . . . .. . . . . . . 22

3.2.1 RESET Input . . .................................................... 22

3.2.2 Power-on Reset .................................................... 22

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . .. ................................. 23

3.2.4 LVD Reset . . . . .. . . . ............................................... 23

3.2.5 Application Notes . . . ................................................23

3.2.6 MCU Initialization Sequence . . . . . . . . ..................................24

3.3 DIGITAL WATCHDOG . . . . . . . . . . .. . . . . . . .................................. 26

3.3.1 Digital Watchdog Register (DWDR) . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.2 Application Notes . . . ................................................28

3.4 INTERRUPTS . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . .. .. . . . . 30

3.4.1 Interrupt request . ...................................................30

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . .. ................................. 31

3.4.3 Interrupt Option Register(IOR) . . . . . . . . . . . . . . . . . . . .. . . . . ............... 32

3.4.4 Interrupt Sources . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . 32

3.5 POWER SAVING MODES . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 34

3.5.1 WAIT Mode ....................................................... 34

3.5.2 STOP Mode . .. . . . . . ...............................................34

3.5.3 Exit from WAIT and STOP Modes . . . . ..................................35

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Table of Contents

Document

Page

4 ON-CHIP PERIPHERALS . . . .. . . . . . . ...........................................36

4.1 I/O PORTS . . . . . . .. . . . . . . . . . ............................................ 36

4.1.1 Operating Modes . . . . . . .. . . . .. . . . .. . . . . . . ........................... 37

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 38

4.1.3 ARTimer alternate functions . . . . .. . . . . . . . . . ........................... 40

4.2 TIMER . . . . . . . . . . . . .. . . . . . . .. .. . . . . . . . ................................. 41

4.2.1 Timer Operation . . . . . . . .. . . . . . . . . . . . . . .............................. 42

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . ................................ 42

4.2.3 Application Notes . . . ................................................42

4.2.4 Timer Registers . . . . . ...............................................43

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . .............................. 44

4.3.1 AR Timer Description . . . . . . . . ........................................44

4.3.2 Timer Operating Modes . . .. . . . .. . . . .................................. 44

4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . ................................. 48

4.4 A/D CONVERTER (ADC) . . ............................................... 50

4.4.1 Application Notes . . . ................................................50

5 SOFTWARE . . . . . . . . . . . . . . . . . ............................................... 52

5.1 ST6 ARCHITECTURE . ................................................... 52

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . .................................. 52

5.3 INSTRUCTION SET . . . . . . . ............................................... 53

6 ELECTRICAL CHARACTERISTICS . .. . . . . . . . . . . . . . .............................. 58

6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................58

6.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 59

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........60

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 61

6.5 A/D CONVERTERCHARACTERISTICS . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 62

6.6 TIMER CHARACTERISTICS . . . . ........................................... 62

6.7 SPI CHARACTERISTICS . . ...............................................62

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . ........................... 62

7 GENERAL INFORMATION . . .. . . . . . . ...........................................68

7.1 PACKAGE MECHANICALDATA . . . . . . . . . . . . . . . . . ........................... 68

7.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 70

ST62P52C/ST62P62C . . . . ............................71

1 GENERAL DESCRIPTION . .. . . . ............................................... 72

1.1 INTRODUCTION . . . . . .. . . . . . . ........................................... 72

1.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 72

1.2.1 Transfer of Customer Code . . . . . . . . . . ................................. 72

1.2.2 Listing Generation and Verification . . . . ................................. 72

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Table of Contents

Document

Page

ST6252C/ST6262B . . . . ..............................75

1 GENERAL DESCRIPTION . .. . . . ............................................... 76

1.1 INTRODUCTION . . . . . .. . . . . . . ........................................... 76

1.2 ROM READOUT PROTECTION .. . . . .. . . . . . ................................76

1.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 78

1.3.1 Transfer of Customer Code . . . . . . . . . . ................................. 78

1.3.2 Listing Generation and Verification . . . . ................................. 78

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ST62T52C ST62T62C/E62C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62T52C and ST62T62C devicesis lowcost members of theST62xx 8-bitHCMOSfamily ofmicrocontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core issurroundedby a numberof on-chip peripherals.

The ST62E62C isthe erasable EPROM version of the ST62T62C device, which may be used to emulate the ST62T52C and ST62T62C devices as well as the ST6252C and ST6262B ROMdevices.

OTP and EPROM devices are functionally identical. The ROM basedversions offer the same functionality selecting as ROM options the options de-

fined in the programmable option byte of the OTP/EPROM versions.

OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choicein a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.

These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability (except ST62T52C), an 8-bit A/D Converter with4 analoginputsanda Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.

Figure 1. Block Diagram

TEST

NMI INTERRUPT

PROGRAM

STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6

POWER

SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

8-BIT

A/D CONVERTER

PA4..PA5/ Ain

PB0, PB2..PB3 / 30 mA Sink

DDVSS

OSCin OSCout RESET

WATCHDOG

MEMORY

PB6 / ARTimin / 20 mA Sink

PORT C PC2..PC3 / Ain

AUTORELOAD

TIMER

PB7 / ARTimout/ 20 mA Sink

128 Bytes

1836 bytes OTP

(ST62T52C, T62C)

1836 bytes EPROM

(ST62E62C)

DATA EEPROM

64 Bytes

(ST62T62C/E62C)

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ST62T52C ST62T62C/E62C

1.2 PIN DESCRIPTIONS VDDand VSS. Power is supplied to the MCU via

these two pins. VDDis the power connection and VSSis the ground connection.

OSCin and OSCout. These pins are internally connected tothe on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active-low RESET pin is used to restart themicrocontroller.

TEST/VPP. TheTEST must be held at VSSfor nor- mal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programmingMode is entered.

NMI. TheNMI pin provides the capability for asynchronous interruption,byapplying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive. It is providedwith anon-chip pullup resistor (if option has been enabled), and Schmitt triggercharacteristics.

PA4-PA5. These 2 lines are organized as one I/O port (A). Each line may be configured under software controlas inputs withor without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pulloutputs, analog inputs for the A/D converter.

PB0, PB2-PB3, PB6-PB7. These 5 lines are organized as one I/O port (B).Each linemaybe configured under software control as inputs with or without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or push-pull outputs. PB6/ARTIMin and PB7/ARTI-

Mout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3pins canbedefinedbyoption either with pull-up or high impedance.

PB0, PB2-PB3, PB6-PB7 scan also sink30mA for direct LED driving.

PC2-PC3. These 2 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output.

Figure 2. ST62T52C, E62C and T62C Pin Configuration

1 2 3 4 5 6 7 89

PB0

/TEST

PB2

PB3

ARTIMin/PB6

PC2/Ain

PC3/Ain

PA5/Ain PA4/Ain

ARTIMout/PB7

NMI

RESET

OSCout

OSCin

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ST62T52C ST62T62C/E62C

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in thesethreememory spaces is described in the following paragraphs.

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.

Figure 3. Memory Addressing Diagram

PROGRAM SPACE

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

DATA RAM

BANK SELECT

WINDOW SELECT

RAM

X REGISTER Y REGISTER V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW

RAM / EEPROM BANKING AREA

000h

03Fh 040h

07Fh 080h 081h 082h 083h 084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

MEMORY

DATA READ-ONLY

MEMORY

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed viathe12-bit ProgramCounter register (PC register).

1.3.2.1 Program Memory Protection

The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Oncethe Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with aprotectionset can therefore not be accepted.

Figure 4. ST62T52C/T62C Program

Memory Map

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP/EPROM)

1836 BYTES

0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h

0FFBh 0FFCh 0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

0880h

087Fh

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d)

1.3.3 Data Space

Data Spaceaccommodates all the datanecessary for processingthe user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T52C, T62C and ST62E62C devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/Oport registers, the peripheral data and control registers, the interrupt option register and theDataROM Window register (DRW register).

Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as wellas the current program counter contents.

Table 1. Additional RAM / EEPROM Banks

Table 2. ST62T52C, T62C and ST62E62C Data

Memory Space

Device RAM EEPROM

ST62T52C 1 x 64 bytes ST62T62C 1 x 64 bytes 1 x 64bytes

RAM / EEPROM banks

000h

03Fh

DATA ROM WINDOW AREA

040h

07Fh X REGISTER 080h Y REGISTER 081h V REGISTER 082h

W REGISTER 083h

DATA RAM 60 BYTES

084h

0BFh

PORT A DATA REGISTER 0C0h PORT B DATA REGISTER 0C1h

PORT C DATA REGISTER 0C2h

RESERVED 0C3h PORT A DIRECTION REGISTER 0C4h PORT B DIRECTION REGISTER 0C5h PORT C DIRECTIONREGISTER 0C6h

RESERVED 0C7h

INTERRUPT OPTIONREGISTER 0C8h*

DATA ROM WINDOW REGISTER 0C9h*

RESERVED

0CAh

0CBh PORT A OPTION REGISTER 0CCh PORT B OPTION REGISTER 0CDh PORT C OPTION REGISTER 0CEh

RESERVED 0CFh

A/D DATA REGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER PRESCALERREGISTER 0D2h

TIMER COUNTERREGISTER 0D3h

TIMER STATUS CONTROL REGISTER 0D4h

AR TIMER MODE CONTROL REGISTER 0D5h AR TIMERSTATUS/CONTROLREGISTER1 0D6h AR TIMERSTATUS/CONTROLREGISTER2 0D7h

WATCHDOG REGISTER 0D8h

AR TIMERRELOAD/CAPTURE REGISTER 0D9h

AR TIMERCOMPARE REGISTER 0DAh

AR TIMER LOAD REGISTER 0DBh

OSCILLATOR CONTROL REGISTER 0DCh*

MISCELLANEOUS 0DDh

RESERVED

0DEh 0E7h

DATA RAM/EEPROM REGISTER 0E8h*

RESERVED 0E9h

EEPROMCONTROL REGISTER 0EAh

RESERVED

0EBh 0FEh

ACCUMULATOR 0FFh

* WRITE ONLY REGISTER

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d)

1.3.5 Data Window Register (DWR)

TheDataread-only memorywindowislocatedfrom address 0040h toaddress 007Fh in Data space. It allows directreadingof64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memoryby writingtheappropriatecodeinthe Data Window Register (DWR).

The DWR can beaddressedlike anyRAMlocation in theData Space, it is howevera write-only register andtherefore cannotbe accessedusingsinglebit operations. This register is used to position the 64-byte read-onlydata window(from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the registeraddress given in the instruction (as least significant bits) and the content of the DWR register (asmost significant bits),as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Data Window Register (DWR)

Address: 0C9h — Write Only

Bits 6, 7= Not used. Bit 5-0 = DWR5-DWR0:

Data read-only memory

Window Register Bits.

These are the Data readonly memory Window bits that correspond to the upper bits of the dataread-only memory space.

Caution:

This register is undefined on reset. Neither read nor single bit instructionsmay be used to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot saveand thenrestoretheregister’s previous contents. If it is impossible to avoid writing to the DWRduring the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also writeto theimage register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

765432 0

543210

READ

67891011

VR01573C

DATA SPACE ADDRESS

59h

000

01001

Example:

(DWR)

DWR=28h

1100000001

ROM

ADDRESS:A19h

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d)

1.3.6 Data RAM/EEPROM Bank Register (DRBR)

Address: E8h — Write only

Bit 7-5= These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2. Bit 3-1. Not used Bit 0. DRBR0. This bit, when set, selects EEP-

ROM page 0. The selection of the bank is made byprogramming

the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1.No more than one bank should be setat a time.

The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register isused toselect the desired 64-byte RAM bank of the Data Space. The bank number has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address).

This registeris not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa-

tion. The DRBR register is not modified when an interrupt or a subroutine occurs.

Notes : Care is requiredwhen handling the DRBR register

as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of thisregister in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Care must also be taken not to change the E

PROM page (when available) when the parallel writing mode is set for theE PROM, as defined in EECTL register.

Table 3. Data RAM Bank Register Set-up

---

DRBR

---

DRBR

DRBR ST62T52C ST62T62C

00 None None 01 Not available EEPROM page 0 02 Not Available Not Available 08 Not available Not available

10h RAM Page 2 RAM Page 2

other Reserved Reserved

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage.

Data spacefrom 00h to3Fh ispagedas described in Table 4 . EEPROM locations are accessed directly by addressing these paged sections of data space.

The EEPROM does notrequire dedicated instructions forread orwrite access.Onceselectedviathe Data RAM Bank Register, the active EEPROM page is controlledby theEEPROM Control Register (EECTL),which is described below.

Bit E20FFoftheEECTL registermust bereset prior to any write or read access to the EEPROM. If no bank hasbeenselected, orif E2OFFisset,any access is meaningless.

Programming must be enabled by setting the E2ENA bitof the EECTL register.

The E2BUSY bit of the EECTL register is setwhen the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless.

Provided E2OFFand E2BUSY arereset, an EEPROM location is readjust like any other data location, alsoin terms of access time.

Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed andpower consumption advantages, the latter being particularly important in battery powered circuits).

General Notes: Data should be writtendirectly to the intended ad-

dress in EEPROM space.There is no buffer memory between data RAM andthe EEPROM space.

When the EEPROM is busy (E2BUSY = “1”) EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set.

Care is required whendealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine.

If it is impossible to avoid writing to this register within an interrupt service routine, animage of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected.

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest

power-consumption.

Dataspace addresses. Banks 0 and 1.

Byte 0 1234567 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h

Up to8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

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ST62T52C ST62T62C/E62C

MEMORY MAP(Cont’d) Additional Notes on Parallel Mode:

If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. After the ROW addressis latched,the MCUcanonly “see” the selected EEPROM row and any attempt to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2 is set.

As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in allor inpart ofthe ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 andaccesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected.

Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must setthe E2PAR2bit betweentwo parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycleand the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low.The E2PAR1 bit can be setby the user, only if the E2ENA and E2PAR2 bits are also set.

Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set.

EEPROM Control Register (EECTL)

Address: EAh — Read/Write Reset status: 00h

Bit 7 =D7:

Unused.

Bit6=E2OFF:

Stand-byEnableBit.

WRITE ONLY. Ifthisbitis settheEEPROM isdisabled(anyaccess will bemeaningless) andthepower consumptionof the EEPROM is reduced to its lowest value.

Bit 5-4 = D5-D4:

Reserved.

MUST bekept reset.

Bit 3 =E2PAR1:

Parallel Start Bit.

WRITE ONLY. OnceinParallelMode,as soonastheusersoftware sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. Thisbitisinternally reset at the end of the programming procedure. Note that less than 8 bytescan bewritten if required, the undefined bytes being unaffected by the parallelprogrammingcycle;thisisexplainedingreater detailin the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2:

Parallel Mode En. Bit.

WRITE ONLY. This bitmust be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytesareconsidered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 arethechangingbits, as illustrated in Table 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged.

Bit 1 = E2BUSY:

EEPROM Busy Bit.

READ ONLY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The userprogram should test it before any EEPROM read orwriteoperation;any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed.

Bit 0 =E2ENA:

EEPROM Enable Bit.

WRITE ONLY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.

E2O

D5 D4

E2PAR1E2PAR2E2BUSYE2E

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ST62T52C ST62T62C/E62C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configurationcapability to the MCUs. Option byte’s content is automatically read, and the selected options enabled,when the chipreset is activated.

It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING modeoftheprogrammer.

The option bytes are located in a non-user map. No address has to bespecified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D13. Reserved. Must becleared. ADC SYNCHRO.When set, an A/D conversion is

started upon WAIT instruction execution, in order to reduce supply noise. When this bit is low, an A/D conversion isstartedassoon astheSTAbit of the A/D Converter Control Registeris set.

D11. Reserved,must be set to one. D10. Reserved,must be cleared. NMI PULL.

NMI Pull-Up

. This bit must be set high to configure the NMI pin with a pull-up resistor. When itis low, no pull-up is provided.

LVD.

LVD RESETenable.

When this bitisset,safe RESET is performed by MCU when the supply voltage is too low. When this bit is cleared, only power-on reset or external RESET are active.

PROTECT.

Readout Protection.

Thisbitallows the protection of the softwarecontents against piracy. When the bit PROTECT is sethigh, readout of the OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

EXTCNTL.

External STOP MODE control.

. When EXTCNTL is high, STOP mode is available with watchdog active by setting NMI pin to one. When

EXTCNTL is low, STOP mode is not available with the watchdog active.

PB2-3 PULL. When set this bit removespull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.

D4. Reserved.Must be cleared to 0. WDACT. This bit controls the watchdog activation.

When it is high, hardware activation is selected. The software activation is selected when WDACT is low.

DELAY. This bit enables the selection of the delay internally generated after the internal reset (external pin, LVD, or watchdog activated) is released. When DELAY is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when DELAY is high.

OSCIL.

Oscillator selection

. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided.

OSGEN.

Oscillator Safe Guard

. This bit must be set high to enable the Oscillator Safe Guard. When this bit is low, the OSG is disabled.

The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode).

1.4.2 Program Memory

EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPPpin. The programming flow of the ST62T62C is described in the User Manual of the EPROM Programming Board.

The MCUs can be programmed with the ST62E6xB EPROM programming tools available from STMicroelectronics.

Table 5. ST62T52C/T62C Program MemoryMap

Note: OTP/EPROM devices can be programmed

with the development tools available from STMicroelectronics (ST62E6X-EPB or ST626X-KIT).

PROTECT

EXTC-

NTL

PB2-3

PULL

- WDACT

DE-

LAY

OSCIL OSGEN

15 8

---

ADC

SYNCHRO

NMI

PULL

LVD

Device Address Description

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

15/78

ST62T52C ST62T62C/E62C

PROGRAMMING MODES (Cont’d)

1.4.3 . EEPROM Data Memory

EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEPROM data memory can be performed either through theapplication software or through an ex-

ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data memory.

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ST62T52C ST62T62C/E62C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPUCoreofST6 devicesisindependentof the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while thecore islinked tothededicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

TheST6FamilyCPUcorefeaturessixregistersand three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h(Y). They canalso beaccessed with the direct, shortdirect, orbit direct addressing modes. Accordingly, the ST6 instruction set can usethe indirect registers asanyother register of the data space.

Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locationsat addresses 82h (V)and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

Figure 6ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATASPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

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ST62T52C ST62T62C/E62C

CPU REGISTERS (Cont’d)

However, if theprogram space contains morethan 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incrementedafter reading the address of the current instruction. Toexecuterelative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC.The programcounter can be changedin the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- InterruptPC=Interrupt vector

- ResetPC= Reset vector

- RET& RETI instructionsPC= Pop (stack)

- NormalinstructionPC= PC + 1 Flags (C, Z). TheST6 CPU includes three pairsof

flags (CarryandZero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation,another pair is used during Interrupt mode (CI, ZI), anda third pairisused in the Non Maskable Interrupt mode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching andthus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction;it also participates inthe rotate left instruction.

The Zero flag isset if the result of the last arithmetic or logical operation was equal to zero; otherwise itis cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interruptor

a RETI instructions occurs. As the NMI mode is automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When asubroutine call (orinterrupt request)occurs, the contentsof eachlevelare shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its “deepest” position if morethan 6 nested calls orinterrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET orRETI isexecuted. In this case the nextinstruction will be executed.

Figure 7ST6 CPU Programming Mode

SHORT

DIRECT

ADDRESSING

MODE

VREGISTER

W REGISTER

PROGRAMCOUNTER

SIX LEVELS

STACKREGISTER

CZNORMAL FLAGS

INTERRUPTFLAGS

NMI FLAGS

INDEX

VA000 4 23

b0b11

ACCUM ULATO R

Y REG. PO INTER

X REG. PO INTER

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ST62T52C ST62T62C/E62C

3 CLOCKS, RESET, INTERRUPTS AND POWERSAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillatorwhich can be driven byan external clock, orused in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor (R

NET

). In addition, a Low FrequencyAuxiliary Oscillator (LFAO)canbe switched in for security reasons, to reduce powerconsumption, orto offer the benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automatically limits the internal clock frequency (f

INT

)asa function of VDD, inorder toguarantee correctoperation. These functions are illustrated in Figure 9., Figure 10., Figure 11. and Figure 12..

Figure 8.illustrates various possible oscillator configurations using anexternal crystal orceramicresonator, an external clock input, anexternal resistor (R

NET

), or the lowest cost solution using only the LFAO. CL1anCL2shouldhave acapacitance inthe range 12 tST6_CLK1o 22 pF for an oscillator frequency in the 4-8 MHz range.

The internal MCU clock frequency (f

INT

) is divided by 12to drive the Timer,theA/D converter andthe Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 11..

With an 8MHz oscillator frequency, thefastestmachine cycle is therefore 1.625µs.

A machine cycleisthesmallest unit of timeneeded to executeanyoperation(for instance,to increment the Program Counter). An instruction may require two, four, or five machine cycles forexecution.

3.1.1 Main Oscillator

The oscillatorconfiguration maybe specifiedbyselecting the appropriate option. When the CRYSTAL/RESONATOR option is selected, it must be usedwithaquartzcrystal,aceramicresonatororan externalsignalprovidedonthe OSCinpin.Whenthe RC NETWORKoptionisselected,thesystem clock is generated by an external resistor.

The main oscillator can be turned off (when the OSG ENABLED option isselected) by setting the OSCOFF bit of the ADC Control Register. The Low Frequency Auxiliary Oscillator isautomatically started.

Figure 8. Oscillator Configurations

INTEGRATED CLOCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

out

L1n

ST6xxx

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

OSC

out

NET

ST6xxx

RC NETWORK

RC NETWORK option

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ST62T52C ST62T62C/E62C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/DConverterControl Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the softwareinstruction at f

LFAO

clock frequency.

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without anyexternal components.Lastly, itactsas a safetyoscillatorin case of main oscillator failure.

This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically startsone of itsperiods after the first missing edge from the main oscillator, whateverthereason (main oscillatordefective, noclock circuitryprovided, main oscillator switched off...).

User code,normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f

LFAO

frequency.TheA/Dconverter accuracy is decreased, since the internal frequency is below 1MHz.

At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay untilthe Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

ADCR

Address: 0D1h — Read/Write

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

ADC ControlRegister

. These bits are not used.

Bit 2 = OSCOFF. When low, thisbit enables main oscillator torun. The mainoscillator is switched off when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affordsdrastically increasedoperational integrity in ST62xx devices. The OSG circuit provides three basic func-

tions: it filtersspikes from the oscillator lines which would result inover frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumptionortoprovide afixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct operation even if the power supply should drop.

The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewedas a filter whose cross-over frequency is device dependent.

Spikes on the oscillatorlinesresultinan effectively increased internal clock frequency.Inthe absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure

9.).In all cases,when the OSG is active, the maximum internal clock frequency, f

INT

, is limited to

OSG

, which is supply voltage dependent. This re-

lationship is illustrated in Figure 12.. When the OSG is enabled, the Low Frequency

Auxiliary Oscillator maybe accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figure 10.).

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below f

OSG

: the maximum authorised frequen-

cy with OSG enabled. Note. The OSG should beusedwherever possible

as it provides maximumsafety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency to f

OSG

Warning: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and amaximumvalue and is not accurate.

For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature).

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

20/78

ST62T52C ST62T62C/E62C

CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle

Figure 10. OSG Emergency Oscillator Principle

(1)

VR001932

(3)

(2)

(4)

(1) (2)

(3) (4)

Maximum Frequency for the device to work correctly Actual Quartz Crystal Frequency at OSCinpin Noise from OSCin

Resulting Internal Frequency

Main

VR001933

Internal

Emergency

Oscillator

Frequency

Oscillator

21/78

ST62T52C ST62T62C/E62C

CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram

Figure 12. Maximum Operating Frequency (f

MAX

) versus Supply Voltage (VDD)

Notes:

1. In this area, operation is guaranteed at the quartz crystal frequency.

2. When the OSG is disabled, operation in this area isguaranteedat the crystal frequency. When the OSGisenabled, operation in this area is guaranteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

area is guaranteed at the quartz crystalfrequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a f

OSG.

4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f

OSG.

MAIN

OSCILLATOR

OSG

LFAO

U X

Core

:13

:12

TIMER 1

Watchdog

POR

INT

Main Oscillator off

2.5 3.6 4 4.5 5 5.5 6

Maximum FREQUENCY (MHz)

SUPPLY VOLTAGE (V

)

FUNCTIONALITY IS NOT

OSG

Min (at 85°C)

GUARANTEED

IN THIS AREA

VR01807J

OSG

Min (at 125°C)

22/78

ST62T52C ST62T62C/E62C

3.2 RESETS

The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-onReset; – by the digital Watchdog peripheral timing out. – by LowVoltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used toreset the MCU internal state andensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signalis generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDDhas completed its rising phase and that theoscillatoris running correctly (normal RUN or WAIT modes). The MCU is keptin the Reset state as long as the RESET pin is held low.

If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN modeonly), theInputsandOutputsare configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET pinactivation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU by detecting around 2V a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon aninternal delay is initiated, inorder to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence

is executed immediately following the internal delay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (presenting oscillation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performances.

Figure 13. Reset and Interrupt Processing

INT LATCH CLEARED

NMI MASKSET

RESET

( IFPRESENT )

SELECT

NMI MODE FLAGS

IS RESETSTILL

PRESENT?

YES

PUT FFEH

ON ADDRESSBUS

FROM RESETLOCATIONS

FFE/FFF

FETCH INSTRUCTION

LOAD PC

VA000427

23/78

ST62T52C ST62T62C/E62C

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE RESET is effective as well in Power-on phase as in power supply drop with different reference val-

ues, allowing hysteresiseffect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start’s running and sinking current on the supply.

As long as the supply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU: RESET active below the voltage reference, and running mode over the voltage reference as shown on the Figure 14., that represents a powerup, power-down sequence.

Note: When the RESET state is controlled by one of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET pin is tied to low logic level.

Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

3.2.5 Application Notes

No external resistor is required between VDDand the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to VDDmust be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired structure).

RESET

VR02106A

time

24/78

ST62T52C ST62T62C/E62C

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in programROM starting at address 0FFEh). A jump tothe beginning oftheuser programmustbe coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in NonMaskable Interrupt mode; this prevents the initialisation routinefrom being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If nopendinginterrupt is present at the endof theinitialisationroutine,the MCU will continue by processing the instruction immediately following the RETIinstruction.If,however, a pending interrupt is present, it will be serviced.

Figure 15. Reset and Interrupt Processing

Figure 16. Reset Block Diagram

RESET

VECTOR

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION

ROUTINE

VA00181

RESET

ESD

POWER

WATCHDOGRESET

COUNTER

RESET

ST6 INTERNAL RESET

OSC

RESET

ON RESET

LVD RESET

VR02107A

AND. Wired

1) Resistive ESD protection. Value not guaranteed.

25/78

ST62T52C ST62T62C/E62C

RESETS (Cont’d) Table 6. Register Reset Status

Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control

AR TIMER Mode Control Register AR TIMER Status/Control 1 Register AR TIMER Status/Control 2Register AR TIMER Compare Register

Miscellaneous Register

0DCh 0EAh 0C0h to0C2h 0C4h to0C6h 0CCh to 0CEh 0C8h 0D4h

0D5h 0D6h 0D7h 0DAh

0DDh

00h

INT=fOSC

; user must set bit3 to 1 EEPROM enabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled

AR TIMER stopped

X, Y,V, W, Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A/D Result Register AR TIMER Load Register AR TIMER Reload/Capture Register

080H TO083H 0FFh 084h to0BFh 0E8h 0C9h 00h to F3h 0D0h 0DBh 0D9h

Undefined

As written if programmed

TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A/D Control Register

0D3h 0D2h 0D8h 0D1h

FFh 7Fh

FEh

40h

Max countloaded

A/D in Standby

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3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recoveryfrom software upsets.

The Watchdog circuitgenerates a Resetwhen the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. Inthe event of a software mishap (usually caused by externally generated interference), the userprogram willno longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind.

Watchdog behaviour is governed by two options, known as “WATCHDOG ACTIVATION” (i.e. HARDWARE or SOFTWARE) and “EXTERNAL STOP MODE CONTROL” (see Table7 ).

In the SOFTWARE option, the Watchdog is disabled until bit Cof theDWDR register has been set.

When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog is permanently enabled. Sincethe oscillatorwillrun continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continuesto countdown.

However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMIpin is high, the Watchdog counter is frozen and the CPU enters STOP mode.

When the MCU exits STOPmode(i.e. when an interrupt is generated), the Watchdog resumes its activity.

Table 7. Recommended Option Choices

Functions Required Recommended Options

Stop Mode & Watchdog “EXTERNAL STOPMODE” &“HARDWARE WATCHDOG”

Stop Mode “SOFTWARE WATCHDOG”

Watchdog “HARDWARE WATCHDOG”

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DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are allset to “1”, thus selectingthe longest Watchdog timer period. This time period can be set to the user’s requirements by setting theappropriatevalue for bits T0 to T5 in the DWDR register. The SR bit mustbe set to “1”, since it is this bit which generates the Reset signal when it changes to “0”; clearing this bit would generate an immediate Reset.

It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 toT5. The usershould bear inmind the fact that these bits are inverted and shifted with respect to the physicalcounter bitswhen writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timerdowncounter is illustrated in Figure 17..

Only the 6 most significant bitsmaybe used to define the time period, since it is bit 6 which triggers the Reset when it changes to “0”. This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of8MHz, thisisequivalenttotimer periods ranging from 384µs to 24.576ms).

Figure 17. Watchdog Counter Control

WATCHDOG CONTROL REGISTER

WATCHDOG COUNTER

OSC÷12

RESET

VR02068A

÷2

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DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR)

Address: 0D8h — Read/Write Reset status:1111 1110b

Bit 0 = C:

Watchdog Control bit

If thehardware option is selected,this bit is forced high andthe user cannotchange it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU).

When C is kept low the counter can be used as a 7-bit timer.

This bitis cleared to “0” on Reset. Bit 1 = SR:

Software Reset bit

This bittriggers a Resetwhen cleared. When C =“0”(Watchdog disabled)it is the MSB of

the 7-bit timer. This bitis set to “1” on Reset. Bits 2-7= T5-T0:

Downcounter bits

It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB.

These bits are set to “1” on Reset.

3.3.2 Application Notes

The Watchdog plays an important supporting role in the highnoise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability.

When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTROL should be preferred, as it provides maximum security,especially during power-on.

When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP modeto be entered when theMCU is idle.

The NMI pin can be connected to an I/O line (see Figure 18.) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdogprotection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption.

When software activation is selected and the Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember thatthe bits are in reverse order).

The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure theWatchdoghasnot been unexpectedly activated, the following instructions should be executed within the first 27 instructions:

jrr 0, WD, #+3 ldi WD, 0FDH

T0 T1 T2 T3 T4 T5 SR C

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DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog.

In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first 27 instructions following Watchdog activation (software mode), or within the first 27 instructions executed followinga Reset (hardwareactivation).

It shouldbe noted that when the GENbit islow (interrupts disabled), the NMI interrupt is active but cannot cause a wake up fromSTOP/WAIT modes.

Figure 18. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature

Figure 19. Digital Watchdog Block Diagram

NMI

SWITCH

I/O

VR02002

RSFF

DATA BUS

VA00010

-2

-12

OSCILLATOR

RESET

WRITE

RESET

DB0

DB1.7 SETLOAD

-2

SET

CLOCK

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3.4 INTERRUPTS

The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains aJump instruction totheassociated interrupt service routine. These vectors are located in Program space(see Table 8 ).

When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC registeris loaded with the address of theinterrupt vector (i.e. of the Jump instruction), which then causes a Jumpto the relevant interrupt service routine, thus servicing the interrupt.

Interrupt sourcesare linked to events either on external pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggeredthe interrupt.

The Non Maskable Interrupt requesthas the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority ofeach interrupt source is fixed.

Table 8. Interrupt Vector Map

3.4.1 Interrupt request

All interrupt sources but the Non Maskable Interrupt source canbe disabled by setting accordingly the GEN bitof the Interrupt OptionRegister (IOR). This GEN bitalso defines if aninterrupt source, including the Non Maskable Interrupt source, canrestart theMCU from STOP/WAIT modes.

Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat-

ically resetby the coreatthe beginning of the nonmaskable interrupt service routine.

Interrupt request from source #1 can be configured either as edge or level sensitivebysetting accordingly the LES bit of the InterruptOption Register (IOR).

Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly theESBbit ofthe Interrupt Option Register (IOR).

Interrupt request from sources #3 & #4 are level sensitive.

In edge sensitive mode, alatch issetwhen a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine before being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored.

Storage of interruptrequests is notavailable in level sensitive mode. To be taken into account, the low level must bepresentonthe interrupt pin when the MCU samples the line after instruction execution.

At the end of every instruction, the MCUtests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead.

Table 9. Interrupt Option Register Description

Interrupt Source Priority Vector Address

Interrupt source #0 1 (FFCh-FFDh) Interrupt source #1 2 (FF6h-FF7h) Interrupt source #2 3 (FF4h-FF5h) Interrupt source #3 4 (FF2h-FF3h) Interrupt source #4 5 (FF0h-FF1h)

GEN

SET Enable all interrupts CLEARED Disable all interrupts

ESB

SET

Rising edge mode oninterrupt source #2

CLEARED

Falling edge mode on interrupt source #2

LES

SET

Level-sensitive mode on interrupt source #1

CLEARED

Falling edge mode on interrupt source #1

OTHERS NOT USED

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INTERRUPTS (Cont’d)

3.4.2 Interrupt Procedure

The interrupt procedure is very similartoa callprocedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. There are separate setsof processor flags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved.

The following list summarizes the interrupt procedure:

MCU

– The interrupt is detected. – The C and Z flags are replaced by the interrupt

flags (orby the NMI flags).

– The PC contents are stored in the first level of

the stack.

– The normalinterrupt lines are inhibited (NMIstill

active). – The first internal latch is cleared. – TheassociatedinterruptvectorisloadedinthePC.

WARNING: In some circumstances, when a maskable interruptoccurs while the ST6 core is in NORMAL mode and especially during the execution of an ”ldi IOR, 00h” instruction (disabling all maskable interrupts):if theinterrupt arrives during the first 3 cycles of the ”ldi” instruction (which is a 4-cycle instruction) the corewill switch to interrupt mode BUTtheflagsCN and ZN will NOT switch to the interruptpair CI and ZI.

User

– User selected registers are saved within the in-

terrupt service routine (normally on a software

stack). – Thesource of the interruptis found bypollingthe

interrupt flags (if more than onesource is associ-

ated with the same vector). – The interrupt is serviced. – Return from interrupt (RETI)

MCU

– AutomaticallytheMCU switches back tothe nor-

mal flagset (or the interrupt flag set) and pops the previous PC value from the stack.

The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). Theuser shouldsave the registers which are usedwithin theinterrupt routine in a software stack. After the RETI instruction is executed, the MCU returns tothe main routine.

Figure 20. Interrupt Processing Flow Chart

INSTRU CTION

FETCH

INSTRU CTION

EXECUT E

INSTRUCTION

WAS

THE INSTRUCTION

ARETI

CLEAR

INTERR UPTMASK

SELECT

PROGRAM FLAGS

”POP”

THE STACKED PC

CHEC K IF THERE IS

AN IN TERRUP T REQUEST

AND INTERRU PTMASK

SELECT

INTER NAL MODE FLAG

PUSH THE

PC INTO THE STACK

LOAD PC FROM

INTERR UPTVEC TOR

(FFC/FFD)

SET

INTERRUPT MASK

YES

IS THE CORE

ALREADY IN

NORMAL MODE?

VA000014

YES

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INTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register(IOR)

The Interrupt Option Register (IOR) is used to enable/disable theindividual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations.

Address: 0C8h — Write Only Reset status:00h

Bit 7, Bits 3-0 =

Unused

Bit 6 = LES:

Level/Edge Selection bit

When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive modefor interrupt request is selected.

Bit 5 =ESB:

Edge Selection bit

The bit ESB selects the polarity of the interrupt source #2.

Bit 4= GEN:

Global Enable Interrupt

. When this bit is set to one, all interrupts are enabled.When this bit is cleared to zero all the interrupts (excluding NMI) are disabled.

When the GEN bit is low, the NMI interrupt is active but cannot cause a wakeupfrom STOP/WAIT modes.

This register is cleared on reset.

3.4.4 Interrupt Sources

Interrupt sources available on the ST62E62C/T62C are summarized in the Table 10 with associated mask bit to enable/disable the interrupt request.

Table 10. Interrupt Requestsand Mask Bits

- LES ESB GEN - - - -

Peripheral Register

Address Register

Mask bit Masked Interrupt Source

Interrupt

vector

GENERAL IOR C8h GEN

All Interrupts, excluding NMI

TIMER TSCR1 D4h ETI TMZ: TIMER Overflow Vector 4 A/D CONVERTER ADCR D1h EAI EOC: End of Conversion Vector 4

AR TIMER ARMC D5h

OVIE CPIE EIE

OVF: AR TIMER Overflow CPF: Successful compare EF: Active edge on ARTIMin

Vector 3

Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin Vector 1 Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin Vector 1 Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin Vector 2

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INTERRUPTS (Cont’d) Figure 21. Interrupt Block Diagram

Start

QCLK

CLR

MUX

IOR REG. C8H, bit 6

IOR REG. C8H, bit 5

CLR

CLK Q

Start

TIMER1

CPIE

CPF

TMZ

ETI

INT #4 (FF0,1)

INT #3 (FF2,3)

INT #2 (FF4,5)

INT #1 (FF6,7)

RESTART FROM

STOP/WAIT

AR TIMER

EIE

OVF

OVIE

VA0426K

PBE

Bits

PORT B

PORT A

PBE

SINGLE BIT ENABLE

FROM REGISTER PORT A,B,C

PORT C

SPINT bit

Start

QCLK

CLR

Bit GEN (IOR Register)

NMI (FFC,D)

NMI

ADC

EOC

EAI

SPIE bit

SPIDIV Register

SPIMOD Register

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3.5 POWER SAVING MODES

The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs.

3.5.1 WAIT Mode

The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a “software frozen” state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active.

WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, whilenot losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering theWAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal.

If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the Watchdog), theMCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU’s behaviour depends on thestate

of the processor coreprior to theWAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary.

3.5.2 STOP Mode

If the Watchdog is disabled,STOP mode is available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontrollercan be considered as being “frozen”, no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exitthe STOP state.

If the STOP state is exited dueto a Reset (byactivating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generated.

This case will be described in the following paragraphs. The processor core generates a delay after occurrence ofthe interrupt request, in order to wait for complete stabilisation ofthe oscillator, before executing the first instruction.

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POWER SAVING MODE (Cont’d)

3.5.3 Exit from WAIT and STOP Modes

The following paragraphs describe how the MCU exits from WAIT and STOP modes, whenan interrupt occurs (not a Reset). It should be noted that the restartsequencedepends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type.

Interrupts do not affect the oscillator selection.

3.5.3.1 Normal Mode

If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Waitmode will occuras soonasaninterrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing noother interrupts are pending.

3.5.3.2 Non Maskable Interrupt Mode

If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, theMCU exits from the Stop orWaitmode as soon as an interrupt occurs: the instruction which followsthe STOP or WAIT instruction is executed, and the MCU remains innon-maskable interrupt mode, even if another interrupt has been generated.

3.5.3.3 Normal Interrupt Mode

If theMCU was in interrupt modebeforetheSTOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered:

– If theinterrupt is a normal one, the interrupt rou-

tine in which the WAIT or STOP mode was en-

tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pendinginterruptswillbe serviced in accordance with their priority.

– In the event of a non-maskable interrupt, the

non-maskable interrupt service routine is processed first, then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction. The MCU remains in normal interrupt mode.

Notes:

To achieve the lowest power consumption during RUN or WAITmodes, the user program must take care of:

– configuringunused I/Os as inputs without pull-up

(these should be externally tied to well defined logic levels);

– placing all peripherals in their power down

modes before entering STOP mode;

When the hardware activated Watchdog is selected, or whenthesoftware Watchdogisenabled,the STOP instruction is disabled and a WAIT instruction will beexecuted in its place.

If all interrupt sources are disabled (GEN low),the MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-upsignal.

The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.

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4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations:

– Input withoutpull-up or interrupt – Input withpull-up and interrupt – Input withpull-up, but without interrupt – Analog input – Push-pull output – Open drain output The lines are organised as bytewise Ports. Each port is associated with 3 registers in Data

space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A Data, Direction and Option registers are associated with the PA0 line of Port A).

The DATA registers (DRx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be readto get the effective logic levels of the pins, but they can

be also written by user software, in conjunction with the related option registers, to select the different input mode options.

Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration.

The Data Direction registers (DDRx) allow the data direction (input or output) of each pin to be set.

The Option registers (ORx) are used to select the different port options available both in input and in output mode.

All I/O registers can be read or written to just as any other RAMlocationinData space, so no extra RAM cells are needed for port data storage and manipulation. During MCU initialization,all I/Oregisters are cleared andthe inputmode withpull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.

Figure 22. I/O PortBlock Diagram

RESET

CONTROLS

OUT

SHIFT

DATA

DIRECTION

OPTION

INPUT/OUTPUT

TO INTERRUPT

TO ADC

VA00413

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I/O PORTS (Cont’d)

4.1.1 Operating Modes

Each pinmay be individually programmed as input or output with various configurations.

This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option registers (OR). Table 11 illustrates the various port configurations which can be selected byuser software.

4.1.1.1 Input Options

Pull-up, High Impedance Option. All input lines can be individually programmed with or withoutan internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state.

4.1.1.2 Interrupt Options

All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software as described in the Interrupt Chapter for each port.

4.1.1.3 Analog Input Options

Some pins can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter.

ONLY ONE

pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.

Table 11. I/O Port Option Selection

Note: X= Don’t care

DDR OR DR Mode Option

0 0 0 Input With pull-up, no interrupt 0 0 1 Input No pull-up, no interrupt 0 1 0 Input With pull-up and with interrupt 0 1 1 Input Analog input (when available) 1 0 X Output Open-drain output (20mA sink when available) 1 1 X Output Push-pull output (20mA sink when available)

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I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence

Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure

23.. All other transitions are potentially risky and should be avoided when changing the I/O operating mode, as itis most likely that undesirablesideeffects will be experienced, such asspurious interrupt generation or two pins shorted together by the analog multiplexer.

Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since theseinstructions make an implicit read and write back of the entire register. In port input mode,however, the data registerreads from the inputpins directly, and not from the data register latches. Sincedata registerinformation in input mode isused toset the characteristics of the input pin (interrupt, pull-up, analog input), these maybe unintentionally reprogrammed depending on the state of the input pins. As a general rule, itis better to limit the use of single bit instructions on data registers to when the whole (8-bit)port is in output mode. In the case ofinputs or ofmixed inputs and

outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be writtento the port data register:

SET bit, datacopy LD a, datacopy LD DRA, a

Warning: Care must also be taken to not use instructions that act on a whole port register (INC, DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction).

The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels.

The user must takecare not toswitch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion.

Figure 23. Diagram showingSafe I/O State Transitions

Note *. xxx = DDR, OR, DR Bits respectively

Interrupt pull-up

Output Open Drain

Output Push-pull

Input pull-up (Reset state)

Input

Analog

Output

Open Drain

Output

Push-pull

Input

010*

000

100

110

011

001

101

111

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I/O PORTS (Cont’d) Table 12. I/O PortOption Selections

Note 1. Provided the correct configuration hasbeen selected.

MODE AVAILABLE ON

(1)

SCHEMATIC

Input

Reset state(

Reset stateif PULL-UP

option disabled

PA4-PA5 PB0, PB6-PB7 PC2-PC3

PB2-PB3,

Input

Reset state

Reset stateif PULL-UP

option enabled

PA4-PA5 PB0,,PB6-PB7 PC2-PC3

PB2-PB3

Input

with pull up

with interrupt

PA4-PA5 PB0, PB2-PB3,PB6-PB7 PC2-PC3

Analog Input

PA4-PA5 PC2-PC3

Open drain output

5mA

Open drain output

30mA

PA4-PA5 PC2-PC3

PB0, PB2-PB3,PB6-PB7

Push-pull output

5mA

Push-pull output

30mA

PA4-PA5 PC2-PC3

PB0, PB2-PB3,PB6-PB7

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

Data out

ADC

Data out

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I/O PORTS (Cont’d)

4.1.3 ARTimer alternate functions

When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high,ARTMout/PB7is thePWM output, independently ofthe port registers configuration.

ARTIMin/PB6 is connected to the AR Timer input. It is configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 asAR Timer input, it mustbeconfigured as input through DDRB.

Figure 24. Peripheral Interface Configuration of AR Timer

AR TIMER

ARTIMin

PWMOE

ARTIMout

PID

MUX

VR01661G

ARTIMin

ARTIMout

PID

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4.2 TIMER

The MCU features an on-chip Timer peripheral, consisting ofan 8-bit counter with a 7-bit programmable prescaler,giving a maximum count of 215.

Figure 25. shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counterregister, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bitprescaler canbe read in the PSC register at address 0D2h. The control logic device is managed in the TSCR register asdescribed in thefollowing paragraphs.

The 8-bit counter is decrement by the output (rising edge) coming from the7-bit prescalerand can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero)bit in the TSCR is set. If the ETI (Enable TimerInterrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used toexit the MCU from WAIT mode.

The prescaler input is the internal frequency (f

INT

) divided by 12. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR (see Table 13.), the clock input of the timer/counter register is multiplexed to different sources. For division factor1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler registerisconnectedtotheclock input of TCR. This bit changesitsstate at half the frequency of the prescaler input clock.For factor 4, bit 1of the PSC is connected to the clock input of TCR, and so forth. The prescaler initializebit, PSI, in the TSCR register must be set to allow the prescaler (and hence the counter) to start. If it is cleared, all the prescaler bits are set and the counter is inhibited from counting. The prescaler can be loaded with any value between0and 7Fh, if bitPSI is set. The prescaler tap is selected by means of the PS2/PS1/PS0 bits in the control register.

Figure 26. illustrates theTimer’s working principle.

Figure 25. Timer Block Diagram

DATA BUS

8-BIT

COUNTER

STATUS/CONTROL

INTERRUPT

LINE

VR02070A

6 5 4

3 2 1 0

SELECT

1OF7

b7 b6 b5 b4 b3 b2 b1 b0

TMZ ETI D5 D4 PSI PS2 PS1 PS0

INT

PSC

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TIMER (Cont’d)

4.2.1 Timer Operation

The Timer prescaler is clocked by the prescaler clock input(f

INT

÷ 12).

The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high.

4.2.2 Timer Interrupt

When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request associated with Interrupt Vector #3 is generated. When the counter decrements to

zero, the TMZ bit in the TSCR register is set to one.

4.2.3 Application Notes

TMZ is set when the counter reaches zero;however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared. This means that the Timer is stopped (PSI=“0”) and the timer interrupt is disabled.

Figure 26. Timer Working Principle

BIT0 BIT1 BIT2 BIT3 BIT6BIT5BIT4

CLOCK

7-BIT PRESCALER

8-1 MULTIPLEXER

8-BIT COUNTER

BIT0 BIT1

BIT2

BIT3 BIT4 BIT5

BIT6

BIT7

10234

PS0 PS1 PS2

VA00186

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TIMER (Cont’d)

A write to the TCR register will predominate over the 8-bit counterdecrementto00h function, i.e.if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at anytime.

4.2.4 Timer Registers Timer Status Control Register (TSCR)

Address: 0D4h — Read/Write

Bit 7 = TMZ:

Timer Zero bit

A low-to-high transition indicates that the timer count register has decrement to zero. This bit must becleared by user software before starting a new count.

Bit 6 = ETI:

Enable Timer Interrup

When set, enables the timer interrupt request (vector #3). If ETI=0 the timer interrupt isdisabled. If ETI=1 and TMZ=1 an interrupt request is generated.

Bit 5 = D5:

Reserved

Must be set to “1”. Bit 4 = D4 Do not care. Bit 3 = PSI:

Prescaler Initialize Bit

Used to initialize the prescalerand inhibit its counting. When PSI=“0” the prescaler is set to 7Fh and the counteris inhibited. When PSI=“1”the prescaler is enabled to count downwards. As long as

PSI=“0” both counter and prescaler are not running.

Bit 2, 1, 0 = PS2, PS1, PS0:

Prescaler Mux. Se-

lect.

These bits select the division ratio of the pres-

caler register.

Table 13. Prescaler Division Factors

Timer Counter Register (TCR)

Address: 0D3h — Read/Write

Bit 7-0 = D7-D0:

Counter Bits.

Prescaler Register PSC

Address: 0D2h — Read/Write

Bit 7 =D7: Always read as ”0”. Bit 6-0 = D6-D0: PrescalerBits.

TMZ ETI D5 D4 PSI PS2 PS1 PS0

PS2 PS1 PS0 Divided by

0001 0012 0104 0118 10016 10132 11064 1 1 1 128

D7 D6 D5 D4 D3 D2 D1 D0

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4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip peripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f

INT,fINT/3

or an external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ARSC1, an output pin, ARTIMout, and an input pin, ARTIMin, allow the Auto-Reload Timer to be used in4 modes:

– Auto-reload (PWMgeneration), – Output compareand reload on external event

(PLL),

– Inputcapture and output compare fortime meas-

urement.

– Input captureand output compare for period

measurement.

The AR Timer can be usedto wake the MCU from WAIT mode either with an internal or with an external clock. It also can be used to wake the MCU from STOP mode, if used with an external clock signal connected to the ARTIMin pin. A Load register allows the program to read and write the counter onthe fly.

4.3.1 AR Timer Description

The AR COUNTER is an 8-bit up-counter incremented onthe input clock’s rising edge. The counter is loaded from the ReLoad/Capture Register, ARRC, for auto-reload or capture operations, as well as for initialization. Direct access to the AR counter is not possible; however, by reading or writing the ARLR load register, it is possible to read or write the counter’s contents on the fly.

The AR Timer’s input clock can beeither the internal clock (from the Oscillator Divider), the internal clock divided by 3, or the clock signal connected to the ARTIMin pin. Selection between these clock sources is effected by suitably programming bits CC0-CC1 of theARSC1 register. The output of the AR Multiplexer feeds the 7-bit programmable AR Prescaler, ARPSC, which selects one of the 8 available taps of the prescaler, as defined by PSC0-PSC2 in the AR Mode Control Register. Thus the division factor ofthe prescaler can be set to 2n (where n = 0, 1,..7).

The clock input tothe ARcounterisenabled bythe TEN (Timer Enable) bit in the ARMC register. When TEN isreset, the AR counterisstopped and

the prescaler and counter contents are frozen. When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset.

The AR counter may also be initialized by writing to the ARLR load register, which also causes an immediate copy of the value tobeplacedinthe AR counter, regardless of whether the counter is running or not. Initialization of the counter, by either method, will also cleartheARPSC register,whereupon counting will start from a known value.

4.3.2 Timer Operating Modes

Four different operating modes are available for the AR Timer:

Auto-reload Mode with PWM Generation. This mode allows a Pulse Width Modulated signal to be generated on the ARTIMout pin with minimum Core processing overhead.

The free running 8-bit counter is fed by the prescaler’s output, and is incremented on every rising edge of the clock signal.

When a counter overflow occurs, the counter is automatically reloadedwith thecontents oftheReload/Capture Register, ARCC, and ARTIMout is set. When the counter reaches the value contained in the compare register (ARCP), ARTIMout is reset.

On overflow, the OVF flag of the ARSC0 registeris set and an overflow interrupt request is generated if the overflow interrupt enable bit, OVIE, in the Mode Control Register (ARMC), is set. The OVF flag must be reset by the user software.

When the counterreaches the compare value,the CPF flag of the ARSC0 register is set and a compare interrupt request isgenerated, if the Compare Interrupt enable bit, CPIE, in the Mode Control Register (ARMC), is set. Theinterrupt service routine may then adjust thePWM period by loading a new value intoARCP. The CPF flag must be reset by user software.

The PWM signal is generated on the ARTIMout pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Reload/Capture register, ARRC. The duty cycle of the PWM signal is controlledby the Compare Register, ARCP.

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AUTO-RELOAD TIMER (Cont’d) Figure 27. AR Timer Block Diagram

DATA BUS

COMPARE

RELOAD/CAPTURE

DATA BUS

AR TIMER

VR01660A

TCLD

OVIE

PWMOE

OVF

LOAD

ARTIMout

SYNCHRO

ARTIMin

SL0-SL1

INT

PB6/

LOAD

U X

INT

AR PRESCALER

7-Bit

CC0-CC1

AR COUNTER

8-Bit

AR COMPARE

OVF

EIE

INTERRUPT

CPF

CPIE

CPF

DRB7

DDRB7

PB7/

PS0-PS2

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AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTIMout, the contents of the ARCP register must be greater thanthe contents of the ARRC register.

The maximum available resolution for the ARTIMout duty cycle is:

Resolution = 1/[255-(ARRC)]

Where ARRC is the content of the Reload/Capture register. The compare value loaded in the Compare Register, ARCP, must be in the range from (ARRC) to 255.

The ARTC counter is initialized by writing to the ARRC register and by then setting the TCLD (Timer Load) andthe TEN (TimerClock Enable) bits in the Mode Control register, ARMC.

Enabling and selection of the clock source is controlled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1. Theprescaler division ratio is selected by the PS0, PS1 and PS2 bits in the ARSC1 register.

In Auto-reload Mode, any of the three available clock sources can be selected: Internal Clock, Internal Clock divided by 3 or the clock signal present on the ARTIMin pin.

Figure 28. Auto-reload Timer PWM Function

COUNTER

COMPARE VALUE

RELOAD

PWM OUTPUT

255

000

VR001852

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AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation.Inthis

mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter isincremented on everyclock rising edge.

An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Control bits SL0, SL1 in the ARSC1 register. At the same time, the External Flag, EF, in the ARSC0 register is set and an external interrupt request is generated if the External Interrupt Enable bit, EIE, in the ARMC register, is set. The EF flag must be reset by user software.

Each ARTC overflow sets ARTIMout, while a match between the counter and ARCP (Compare Register) resets ARTIMout and sets the compare flag, CPF.A compare interrupt request is generated if the related compare interrupt enable bit, CPIE, isset. A PWM signal is generated on ARTIMout. The CPF flag must be reset by user software.

The frequency of the generated signal is determined by the prescaler setting. The duty cycle is determined by the ARCP register.

Initialization and reading of thecounter are identical tothe auto-reload mode(see previousdescription).

Enabling andselection of clock sources is controlled by the CC0 and CC1 bits in the AR StatusControl Register, ARSC1.

The prescaler division ratio is selected by programming the PS0, PS1 and PS2 bits in the ARSC1 Register.

In Capture mode, the allowed clock sources are the internalclock and the internal clock divided by 3; the external ARTIMin input pin should not be used asa clock source.

Capture Mode with Reset of counter and prescaler, and PWM Generation. This mode isidenti-

cal to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period measurement on the ARTIMin pin).

Load on External Input. The counter operates as a free running 8-bit counter fed by the prescaler.

the count is incremented on every clock rising edge.

Each counter overflow sets the ARTIMout pin. A match between the counter and ARCP (Compare Register) resets the ARTIMout pin and sets the compare flag, CPF. A compareinterrupt request is generated if the related compare interrupt enable bit, CPIE, is set. A PWM signal is generated on ARTIMout. The CPF flag must be reset by user software.

Initialization of the counter is as described in the previous paragraph. In addition, ifthe external ARTIMin input is enabled,an activeedge onthe input pin will copy the contents of the ARRC registerinto the counter, whether the counter is running or not.

Notes: The allowed AR Timer clock sources are the fol-

lowing:

The clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. For instance, the multiplexer setting should not be modified while the counter is counting.

Loading of the counter by any means (by auto-reload, through ARLR, ARRC or by the Core) resets the prescaler at the same time.

Care should be taken when boththeCapture interrupt and the Overflow interrupt are used. Capture and overflow are asynchronous. If the capture occurs when the Overflow Interrupt Flag, OVF, is high (between counteroverflow and the flag being reset by software, in the interruptroutine), the External Interrupt Flag, EF, may be cleared simultaneusly without the interrupt being taken into account.

The solution consists in resetting the OVF flag by writing 06h in the ARSC0 register. Thevalue ofEF is not affectedby this operation. If an interrupt has occured, it will be processed when the MCU exits from the interrupt routine (the second interrupt is latched).

AR Timer Mode Clock Sources

Auto-reload mode f

INT,fINT/3

, ARTIMin

Capture mode f

INT,fINT/3

Capture/Reset mode f

INT,fINT/3

External Load mode f

INT,fINT/3

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AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers AR Mode Control Register (ARMC)

Address: D5h — Read/Write Reset status:00h

The AR Mode Control Register ARMC is used to program the different operating modes of the AR Timer, to enable the clock and to initialize the counter. It can be read and written to by the Core and it is cleared on system reset (the AR Timer is disabled).

Bit 7 = TLCD:

Timer Load Bit.

This bit, when set, will cause the contents of ARRC register to be loaded into the counter and the contents of the prescaler register,ARPSC, are cleared in orderto initialize the timer before starting to count. This bit is write-only and any attempt to read it will yield a logical zero.

Bit 6 = TEN

: Timer Clock Enable.

This bit, when set, allows the timer to count. When cleared, it will stop the timer and freeze ARPSC and ARTSC.

Bit 5 = PWMOE:

PWM Output Enable.

This bit, when set, enables the PWM output on the ARTIMout pin. When reset, thePWM outputisdisabled.

Bit 4 = EIE:

External Interrupt Enable.

This bit, when set, enables the external interrupt request. When reset, the external interrupt request is masked. If EIE is set and the related flag, EF, in the ARSC0 register is also set, an interrupt request is generated.

Bit 3 = CPIE:

Compare Interrupt Enable.

This bit, when set, enables the compare interrupt request. If CPIE is reset, the compare interrupt request is masked. If CPIE is set and the related flag, CPF,in the ARSC0 register is also set, an interrupt request is generated.

Bit 2 = OVIE:

Overflow Interrupt

. This bit, when set, enables the overflow interrupt request. If OVIE is reset, the compare interrupt request is masked. If OVIE is set and the related flag, OVF in the

ARSC0 register is also set, an interrupt request is generated.

Bit 1-0= ARMC1-ARMC0:

Mode Control Bits 1-0

. These are the operating mode control bits. The following bit combinations will select the various operating modes:

AR Timer Status/Control Registers ARSC0 & ARSC1. Theseregisterscontain theAR Timer sta-

tus information bits and also allow the programming of clock sources, active edge and prescaler multiplexer setting.

ARSC0 register bits 0,1 and 2 containthe interrupt flags of theAR Timer. These bits are read normally. Each one may be reset by software. Writing a one does not affect thebit value.

AR Status Control Register 0 (ARSC0)

Address: D6h — Read/Clear

Bits 7-3 = D7-D3:

Unused

Bit 2=EF:

External Interrupt Flag.

This bit is set by any active edge on the external ARTIMin input pin. The flag is cleared bywriting a zero to theEF bit.

Bit 1 = CPF:

Compare Interrupt Flag.

This bit is set if the contents of the counter and the ARCP register areequal. The flag is cleared by writing a zero to the CPF bit.

Bit 0 = OVF:

Overflow InterruptFlag.

This bitis set by a transition of the counter from FFh to 00h (overflow). The flag is cleared by writing a zero to the OVF bit.

TCLD T EN PWMOE EI E CPIE OVIE ARMC1 ARMC0

ARMC1 ARMC0 Operating Mode

0 0 Auto-reload Mode 0 1 Capture Mode

Capture Mode with Reset of ARTC and ARPSC

Load on External Edge Mode

D7 D6 D5 D4 D3 EF CPF OVF

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AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1)

Address: D7h — Read/Write

Bist 7-5 = PS2-PS0:

Prescaler Division Selection

Bits 2-0.

These bits determine the Prescaler division ratio. The prescaler itself is not affected by these bits.Theprescalerdivision ratioislisted inthe following table:

Table 14. Prescaler Division Ratio Selection

Bit 4 = D4:

Reserved

. Mustbe kept reset.

Bit 3-2= SL1-SL0:

Timer InputEdgeControl Bits1-

These bits control theedgefunctionof theTimer inputpinfor externalsynchronization.IfbitSL0isreset, edgedetectionis disabled;ifsetedge detection is enabled.If bitSL1is reset,theARTimer inputpin is rising edge sensitive; if set,itis falling edge sensitive.

Bit 1-0 = CC1-CC0:

Clock Source Select Bit 1-0.

These bits select theclocksource for theARTimer through the AR Multiplexer. The programming of the clocksourcesisexplainedin thefollowingTable 15 :

Table 15. Clock Source Selection.

AR Load Register ARLR. The ARLR loadregister

is used to read or write the ARTC counter register “on the fly” (while it is counting). The ARLR register is not affected by system reset.

AR Load Register (ARLR)

Address: DBh — Read/Write

Bit 7-0 = D7-D0:

Load Register Data Bits.

These

are the load register data bits.

AR Reload/Capture Register. The ARRC reload/capture register is used to hold the auto-reload value which is automatically loaded into the counter when overflow occurs.

AR Reload/Capture (ARRC)

Address: D9h — Read/Write

Bit 7-0 = D7-D0:

Reload/Capture Data Bits

. These

are the Reload/Capture register data bits.

AR Compare Register. The CP compare register is used to holdthe compare value for the compare function.

AR Compare Register (ARCP)

Address: DAh — Read/Write

Bit 7-0 = D7-D0:

Compare Data Bits

. These are

the Compare register data bits.

PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0

PS2 PS1 PS0 ARPSC Division Ratio

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 2 4

8 16 32 64

128

SL1 SL0 Edge Detection

X 0 Disabled 0 1 Rising Edge 1 1 Falling Edge

CC1 CC0 Clock Source

00F

int

01F

int

Divided by 3 1 0 ARTIMin Input Clock 1 1 Reserved

D7 D6 D5 D4 D3 D2 D1 D0

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4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to digital converter with analoginputs asalternateI/O functions (the number of which is device dependent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock frequency of 8MHz).

The ADC converts the input voltage by a process of successive approximations, using a clock frequency derived from the oscillator with a division factor oftwelve. With an oscillator clock frequency less than 1.2MHz, conversion accuracy is decreased.

Selection of the input pin is done by configuring the related I/O line as an analog input via the Option and Data registers (refer to I/O ports description for additional information). Only one I/O line must be configured as an analog input at any time. The user must avoid any situation in which more than one I/O pin is selected as an analog input simultaneously, toavoid device malfunction.

The ADC uses two registers in the data space:the ADC data conversion register, ADR, which stores the conversion result, and the ADC control register, ADCR,used to program the ADC functions.

A conversionis started by writinga “1”to the Start bit (STA) in the ADC control register. This automatically clears (resets to “0”) the End Of Conversion Bit (EOC). When a conversion is complete, the EOC bit is automatically set to “1”, in order to flag that conversion is complete and that the data in the ADC data conversion registeris valid. Each conversion has to be separately initiated bywriting to the STA bit.

The STA bit is continuously scanned so that, ifthe user sets it to “1” while a previous conversion is in progress, a new conversion is started before completing the previous one. The start bit (STA) is a write onlybit, any attempt to read it will show a logical “0”.

The A/D converter features a maskable interrupt associated with the end of conversion. This interrupt is associated with interrupt vector #4 and occurs when the EOC bit is set (i.e. when a conversion is completed). The interrupt is masked using the EAI(interrupt mask) bit in the control register.

The power consumption of the device can be reduced by turning off the ADC peripheral. This is done by setting the PDS bit in the ADC control register to “0”. If PDS=“1”, the A/D is powered andenabled for conversion. This bit must be set at least one instruction before the beginningofthe conver-

sion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automatically disabled in WAIT mode.

During Reset, any conversion in progress is stopped, thecontrolregisterisresetto 40h and the ADC interrupt is masked (EAI=0).

Figure 29. ADC Block Diagram

4.4.1 Application Notes

The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed ±1/2 LSB for the optimum conversion accuracy. A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion.

When selected asan analog channel, the input pin is internally connected to a capacitor Cadof typically 12pF. For maximum accuracy, this capacitor must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 µs) after the channel has been selected. In worst case conditions, the impedance, ASI, of the analog voltage sourceis calculated using the following formula:

6.5µs=9xCadx ASI

(capacitor charged to over 99.9%), i.e. 30 kΩ including a 50% guardband. ASI can behigher ifC

has been charged for a longer period by adding instructions before the start of conversion (adding more than 26 CPU cycles is pointless).

CONTROL REGISTER

CONVERTER

VA00418

RESULT REGISTER

RESET

INTERRUPT CLOCK

AV AV

Ain

CORE

CONTROL SIGNALS

CORE

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A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the microprocessor, the user shouldnotswitch heavily loaded output signals during conversion, if high precision is required.Such switchingwill affect the supply voltages used as analog references.

The accuracy of the conversion depends on the quality of the power supplies (VDDand VSS). The user musttake special care to ensure a well regulated reference voltage is present on the VDDand VSSpins (power supply voltage variations mustbe less than5V/ms). This implies,in particular, that a suitable decoupling capacitor is used at the V

pin. The converter resolution is given by::

The Input voltage (Ain) which is to be converted must be constant for 1µs before conversion and remain constant during conversion.

Conversion resolution canbeimproved if the power supply voltage (VDD) to the microcontroller is lowered.

In orderto optimise conversion resolution,theuser can configure the microcontroller in WAIT mode, because this mode minimises noise disturbances and power supply variations due to output switching. Nevertheless, the WAIT instruction should be executed as soon as possible after the beginning of the conversion, because execution of theWAIT instruction may cause a small variation of the V

voltage. The negative effectofthisvariationisminimized at the beginning oftheconversion whenthe converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined.

The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. Indeed, only the ADC peripheral and the oscillator are thenstillworking. The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion. It should be noted that waking up the microcontroller could also be done using the Timer interrupt, but in this case the Timer will be working and the resulting noise could affect conversion accuracy.

One extra feature is available in the ADC to get a better accuracy. Infact, each ADC conversion has to be followed by a WAIT instruction to minimize

the noise during the conversion. But the first conversion step is performed before the execution of the WAIT when most of clocks signals are still enabled . The key is to synchronize the ADC start with the effective execution of the WAIT. This is achieved by setting ADC SYNC option. This way, ADC conversion starts in effective WAIT for maximum accuracy.

Note: With this extra option, it ismandatory to execute WAIT instruction just after ADCstart instruction. Insertion of any extra instruction may cause spurious interrupt request at ADC interrupt vector.

A/D Converter Control Register (ADCR)

Address: 0D1h — Read/Write

Bit 7 = EAI:

Enable A/D Interrupt.

If this bit is setto “1” the A/D interrupt is enabled, when EAI=0 the interrupt is disabled.

Bit 6 = EOC:

End of conversion. Read Only

. This read only bit indicates when a conversion has been completed. This bit is automatically reset to “0” when the STA bit is written.If the user is using the interrupt optionthen this bit can be used as an interrupt pending bit. Data in the data conversion register are valid only whenthis bit is set to“1”.

Bit 5 =STA

: Startof Conversion. Write Only

. Writing a “1” to this bitwill start aconversion on the selected channel and automatically reset to “0” the EOC bit. If the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. This bit is write only, any attempt to read it will show a logical zero.

Bit 4 = PDS

: Power Down Selection.

This bit activates the A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode).

Bit 3-0 = D3-D0. Not used

A/D Converter Data Register (ADR)

Address: 0D0h — Read only

Bit 7-0 = D7-D0

: 8Bit A/D Conversion Result.

DDVSS

–

256

----------------------------

EAI EOC STA PDS D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

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5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit isstored with thevalue of the bitwhen the SET or RES instruction is processed.

5.2 ADDRESSING MODES

The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spacesare available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plusthe data for immediate modeinstructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space containssix 12-bit RAMcells used tostack the return addresses for subroutines and interrupts.

Immediate. In the immediate addressing mode, the operand of the instruction follows the opcode location. Asthe operand is a ROM byte, theimmediate addressing mode is used to access constants which donot changeduringprogramexecution (e.g., a constant used to initialize a loop counter).

Direct. In the direct addressing mode, the address of the byte which is processed bythe instruction is stored in the location which follows the opcode. Direct addressing allowsthe user to directly address the 256bytesin Data Space memorywith a single two-byte instruction.

Short Direct. The core can address the four RAM registers X,Y,V,W (locations 80h, 81h,82h,83h) in the short-directaddressingmode. In this case, the instruction is only one byte and theselection of the location to be processed is contained in the opcode. Shortdirectaddressing is a subset of the direct addressing mode. (Note that 80h and 81h are also indirect registers).

Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained byconcatenating the four less significant

bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space.

An extended addressing mode instruction is twobyte long.

Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of

-15 to +16locations around the address of therelative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is

0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of thebranch.

Bit Direct. In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the bytein whichthe specified bit mustbe set or cleared. Thus,any bitin the 256 locations of Data space memory can beset or cleared.

Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by theassembler.

Indirect. In the indirect addressingmode, the byte processed by the register-indirect instruction is at the address pointed by the content ofone oftheindirect registers, XorY (80h,81h). Theindirect register is selected by thebit4 of the opcode. A register indirect instruction is one byte long.

Inherent. In the inherent addressing mode, all the information necessary toexecute the instruction is contained in the opcode. These instructions are one byte long.

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5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describethe different types.

All the instructions belonging to a given type are presented in individual tables.

Load & Store. These instructionsuse one,two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes.

For Load Immediate one operand can be any of the 256 data spacebyteswhile the other is always immediate data.

Table 16. Load & Store Instructions

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register

∆. Affected

* . Not Affected

Instruction Addressing Mode Bytes Cycles

Flags

LD A, X Short Direct 1 4 ∆ * LD A, Y Short Direct 1 4 ∆ * LD A, V Short Direct 1 4 ∆ * LD A, W Short Direct 1 4 ∆ * LD X, A Short Direct 1 4 ∆ * LD Y,A Short Direct 1 4 ∆ * LD V,A Short Direct 1 4 ∆ * LD W,A Short Direct 1 4 ∆ * LD A, rr Direct 2 4 ∆ * LD rr, A Direct 2 4 ∆ * LD A, (X) Indirect 1 4 ∆ * LD A, (Y) Indirect 1 4 ∆ * LD (X), A Indirect 1 4 ∆ * LD (Y), A Indirect 1 4 ∆ *

LDI A, #N Immediate 2 4 ∆ *

LDI rr, #N Immediate 3 4 * *

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ST62T52C ST62T62C/E62C

INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are

used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions oneoperand is alwaystheaccumulator while the other can be either a data space memorycon-

tent or an immediate value in relation with the addressing mode. InCLR, DEC, INC instructionsthe operand can be any of the 256 data space addresses. In COM, RLC,SLA the operand is always the accumulator.

Table 17. Arithmetic & Logic Instructions

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register

Instruction Addressing Mode Bytes Cycles

Flags

ADD A, (X) Indirect 1 4 ∆∆ ADD A, (Y) Indirect 1 4 ∆∆ ADD A, rr Direct 2 4 ∆∆ ADDI A, #N Immediate 2 4 ∆∆ AND A, (X) Indirect 1 4 ∆∆ AND A, (Y) Indirect 1 4 ∆∆ AND A, rr Direct 2 4 ∆∆ ANDI A, #N Immediate 2 4 ∆∆ CLR A Short Direct 2 4 ∆∆ CLR r Direct 3 4 * * COM A Inherent 1 4 ∆∆ CP A,(X) Indirect 1 4 ∆∆ CP A,(Y) Indirect 1 4 ∆∆ CP A,rr Direct 2 4 ∆∆ CPI A, #N Immediate 2 4 ∆∆ DEC X Short Direct 1 4 ∆ * DEC Y Short Direct 1 4 ∆ * DEC V Short Direct 1 4 ∆ * DEC W Short Direct 1 4 ∆ * DEC A Direct 2 4 ∆ * DEC rr Direct 2 4 ∆ * DEC (X) Indirect 1 4 ∆ * DEC (Y) Indirect 1 4 ∆ * INC X Short Direct 1 4 ∆ * INC Y Short Direct 1 4 ∆ * INC V Short Direct 1 4 ∆ * INC W Short Direct 1 4 ∆ * INC A Direct 2 4 ∆ * INC rr Direct 2 4 ∆ * INC (X) Indirect 1 4 ∆ * INC (Y) Indirect 1 4 ∆ * RLC A Inherent 1 4 ∆∆ SLA A Inherent 2 4 ∆∆ SUB A, (X) Indirect 1 4 ∆∆ SUB A, (Y) Indirect 1 4 ∆∆ SUB A, rr Direct 2 4 ∆∆ SUBI A, #N Immediate 2 4 ∆∆

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INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions

achieve a branch in the program when the selected conditionis met.

Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations.

Control Instructions. The control instructions control the MCU operations during program execution.

Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.

Table 18. Conditional Branch Instructions

Notes:

b. 3-bit address rr. Data space register e. 5 bitsigneddisplacement in the range -15 to +16<F128M> ∆ . Affected. The tested bit is shifted into carry. ee. 8 bit signed displacement inthe range -126 to +129 * . Not Affected

Table 19. Bit Manipulation Instructions

Notes:

b. 3-bit address; * . Not<M> Affected rr. Data space register;

Table 20. Control Instructions

Notes:

1. This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected. ∆ . Affected *. Not Affected

Table 21. Jump & Call Instructions

Notes:

abc. 12-bit address; * . Not Affected

Instruction Branch If Bytes Cycles

Flags

JRCe C=1 1 2 * * JRNC e C = 0 1 2 * * JRZe Z=1 1 2 * * JRNZ e Z = 0 1 2 * * JRR b,rr, ee Bit = 0 3 5 * ∆ JRS b, rr, ee Bit = 1 3 5 * ∆

Instruction Addressing Mode Bytes Cycles

Flags

SET b,rr Bit Direct 2 4 * * RES b,rr Bit Direct 2 4 * *

Instruction Addressing Mode Bytes Cycles

Flags

NOP Inherent 1 2 * * RET Inherent 1 2 * * RETI Inherent 1 2 ∆∆ STOP (1) Inherent 1 2 * * WAIT Inherent 1 2 * *

Instruction

Addressing Mode Bytes Cycles

Flags

CALL abc Extended 2 4 * * JP abc Extended 2 4 * *

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Opcode Map Summary. The following table contains an opcode map for the instructionsusedbytheST6

LOW

0000

0001

0010

0011

0100

0101

0110

0111

LOW

HI HI

0000

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD

0000

e abc e b0,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0001

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI

0001

e abc e b0,rr,ee e x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0010

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP

0010

e abc e b4,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI

0011

e abc e b4,rr,ee e a,x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0100

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD

0100

e abc e b2,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0101

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI

0101

e abc e b2,rr,ee e y e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0110

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC

0110

e abc e b6,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

0111

e abc e b6,rr,ee e a,y e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

1000

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD

1000

e abc e b1,rr,ee e # e (x),a

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1001

2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC

1001

e abc e b1,rr,ee e v e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

1010

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND

1010

e abc e b5,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI

1011

e abc e b5,rr,ee e a,v e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

1100

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB

1100

e abc e b3,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1101

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI

1101

e abc e b3,rr,ee e w e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

1110

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC

1110

e abc e b7,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

1111

e abc e b7,rr,ee e a,w e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviationsfor Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement imm Immediate b 3 Bit Address inh Inherent rr 1bytedataspace address ext Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address bt Bit Test ee 8 bit Displacement pcr Program Counter Relative ind Indirect

JRC

1 prc

Mnemonic

Addressing Mode

Bytes

Cycle Operand

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Opcode Map Summary (Continued)

LOW

1000

1001

1010

1011

1100

1101

1110

1111

LOW

HI HI

0000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD

0000

e abc e b0,rr e rr,nn e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind

0001

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

0001

e abc e b0,rr e x e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP

0010

e abc e b4,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

0011

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP

0011

e abc e b4,rr e x,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0100

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD

0100

e abc e b2,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

0101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD

0101

e abc e b2,rr e y e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC

0110

e abc e b6,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

0111

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC

0111

e abc e b6,rr e y,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD

1000

e abc e b1,rr e # e (y),a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

1001

2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

1001

e abc e b1,rr e v e rr,a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND

1010

e abc e b5,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1011

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND

1011

e abc e b5,rr e v,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1100

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB

1100

e abc e b3,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB

1101

e abc e b3,rr e w e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC

1110

e abc e b7,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1111

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC

1111

e abc e b7,rr e w,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviationsfor Addressing Modes: Legend:

JRC

1 prc

Mnemonic

Addressing Mode

Bytes

Cycle Operand

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6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product containsdevicesto protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages.

For proper operation it is recommended that V

and VObe higher than VSSand lower than VDD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (V

or VSS).

Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from:

Tj=TA + PD x RthJA

Where:TA = Ambient Temperature.

RthJA =Package thermal resistance (junc-

tion-to ambient). PD = Pint + Pport. Pint =IDD x VDD (chip internal power). Pport =Portpower dissipation (determined

by the user).

Notes:

- Stresses above thoselistedas “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of thedevice at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

- (1)Within these limits,clamping diodes are guarantee tobenot conductive. Voltages outside these limits are authorised aslong as injection current is kept withinthe specification.

Symbol Parameter Value Unit

Supply Voltage -0.3 to7.0 V

Input Voltage VSS- 0.3 toVDD+ 0.3

(1)

Output Voltage VSS- 0.3 toVDD+ 0.3

(1)

TotalCurrent into VDD(source) 80 mA

TotalCurrent out of VSS(sink) 100 mA

Tj Junction Temperature 150 °C

STG

Storage Temperature -60 to150 °C

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6.2 RECOMMENDED OPERATING CONDITIONS

Notes:

1. Care must betaken incase ofnegative current injection, where adaptedimpedance must be respected onanalog sources to not affectthe

A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.

2.An oscillator frequency above1MHz is recommended for reliable A/D results

Figure 30. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Operating Temperature

6 Suffix Version 1 Suffix Version 3 Suffix Version

-40 0

-40

85 70

125

°C

Operating Supply Voltage (Except ST626xB ROM devices)

OSC

=4MHz, 1 & 6 Suffix

OSC

=4MHz, 3 Suffix fosc= 8MHz ,1 & 6 Suffix fosc= 8MHz ,3 Suffix

3.0

3.6

4.5

6.0

Operating Supply Voltage (ST626xB ROM devices)

OSC

=4MHz, 1 & 6 Suffix f

OSC

=4MHz, 3 Suffix fosc= 8MHz ,1 & 6 Suffix fosc= 8MHz ,3 Suffix

3.0

4.0

4.5

6.0

OSC

Oscillator Frequency

(Except ST626xB ROM devices)

= 3.0V,1 & 6 Suffix

= 3.0V , 3 Suffix

= 3.6V , 1 & 6 Suffix

= 3.6V , 3 Suffix

0 0 0 0

4.0

8.0

4.0

MHz

Oscillator Frequency

(ST626xB ROM devices)

= 3.0V,1 & 6 Suffix

= 3.0V , 3 Suffix

= 4.0V , 1 & 6 Suffix

= 4.0V , 3 Suffix

0 0 0 0

4.0

8.0

4.0

MHz

INJ+

Pin Injection Current (positive) VDD= 4.5 to 5.5V +5 mA

INJ-

Pin Injection Current (negative) VDD= 4.5 to 5.5V -5 mA

2.5 3 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

Maximum FREQUENCY (MHz)

FUNCTIONALITY IS NOT

GUARANTEED IN

THIS AREA

3 Suffix version

1 & 6 Suffix version

3.6

3 Suffix version

ST626xB ROM devices

All devices except ST626xB ROM devices

1 & 6 Suffix

version

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6.3 DC ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

(1) Hysteresis voltage between switching levels (2) All peripherals running (3) All peripherals in stand-by

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Input Low Level Voltage All Input pins

x 0.3 V

Input High LevelVoltage All Input pins

x 0.7 V

Hys

Hysteresis Voltage

(1)

All Input pins

=5V

=3V

0.2

LVD Threshold in power-on 4.1 4.3

LVD threshold inpowerdown 3.5 3.8

Low Level Output Voltage All Output pins

VDD= 5.0V; IOL= +10µA V

= 5.0V; IOL= + 3mA

0.1

0.8 V

Low Level Output Voltage 30 mA Sink I/O pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= +7mA

= 5.0V; IOL= +15mA

0.1

0.8

1.3

High Level Output Voltage All Output pins

VDD= 5.0V; IOH= -10µA V

= 5.0V; IOH= -3.0mA

4.9

3.5

Pull-up Resistance

All Input pins 40 100 350

ΚΩ

RESET pin 150 350 900

Input Leakage Current All Input pins but RESET

VIN=VSS(No Pull-Up configured) V

IN=VDD

0.1 1.0 µA

Input Leakage Current RESET pin

IN=VSS

VIN=V

-8 -16 -30 10

Supply Current in RESET Mode

RESET=VSS

OSC

=8MHz

7mA

Supply Current in RUN Mode

(2)

VDD=5.0V f

INT

=8MHz 7 mA

Supply Current in WAIT Mode

(3)

VDD=5.0V f

INT

=8MHz 2.5 mA

Supply Current in STOP Mode, with LVD disabled

(3)

LOAD

=0mA

=5.0V

20 µA

Supply Current in STOP Mode, with LVD enabled

(3)

LOAD

=0mA

=5.0V

500

Retention EPROM Data Retention T

=55°C 10 years

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DC ELECTRICAL CHARACTERISTICS (Cont’d)

(TA= -40 to +85°C unless otherwise specified))

Note: (*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

1. Period for which V

has to be connected at 0V to allow internal Reset function at next power-up.

2 An oscillator frequency above 1MHz is recommended forreliable A/D results.

3. Measure performed with OSCin pin soldered on PCB, with anaround 2pF equivalent capacitance.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

LVD Threshold in power-on Vdn+50 mV 4.1 4.3 V

LVD threshold inpowerdown 3.6 3.8 Vup-50 mV V

Low Level Output Voltage All Output pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= + 5mA

= 5.0V; IOL= + 10mAv

0.1

0.8

1.2 V

Low Level Output Voltage 30 mA Sink I/O pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= +10mA

= 5.0V; IOL= +20mA

= 5.0V; IOL= +30mA

0.1

0.8

1.3

2.0

High Level Output Voltage All Output pins

VDD= 5.0V; IOH= -10µA V

= 5.0V; IOH= -5.0mA

4.9

3.5

Supply Current in STOP Mode, with LVD disabled

(*)

LOAD

=0mA

=5.0V

10 µA

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

REC

Supply Recovery Time

(1)

100 ms

WEE

EEPROM Write Time

=25°C

=85°C

=125°C

5 10 20

10 20 30

Endurance

(2)

EEPROM WRITE/ERASE Cycle QALOTAcceptance (25°C) 300,000 1 million cycles

Retention EEPROM Data Retention T

=55°C 10 years

LFAO

Internal frequency with LFAO active 200 400 800 kHz

OSG

Internal Frequency with OSG enabled

VDD=3V V

= 3.6V

= 4.5V

=6V

1 1 2 2

OSC

MHz

Internal frequency with RC oscillator and OSG disabled

2) 3)

VDD=5.0V (Except 626xB ROM) R=47kΩ R=100kΩ R=470kΩ

2.7

800

3.2

850

5.8

3.5

900

MHz MHz

kHz

VDD=5.0V (626xB ROM) R=10kΩ R=27kΩ R=100kΩ

2.4

1.8

800

3.1

2.2

980

3.8

2.5

1200

MHz MHz

kHz

Input Capacitance All Inputs Pins 10 pF

OUT

Output Capacitance All Outputs Pins 10 pF

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6.5 A/D CONVERTER CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

1. Noise at VDD, VSS <10mV

2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

6.6 TIMER CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

6.7 SPI CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Res Resolution 8 Bit

TOT

TotalAccuracy

(1) (2)

OSC

> 1.2MHz

OSC

> 32kHz

±2 ±4

LSB

Conversion Time

OSC

= 8MHz (TA<85°C)

OSC

= 4 MHz

140

µs

ZIR Zero Input Reading

Conversion result when V

IN=VSS

00 Hex

FSR Full Scale Reading

Conversion result when V

IN=VDD

FF Hex

Analog Input CurrentDuring Conversion

= 4.5V 1.0 µA

Analog Input Capacitance 2 5 pF

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Input Frequency on TIMER Pin MHz

Pulse Width at TIMER Pin

= 3.0V

>4.5V

125

µs ns

IINT

----------

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ST62T52C ST62T62C/E62C

Figure 31. Vol versus Iol on all I/O port at Vdd=5V

Figure 32. Vol versus Iol on all I/O port atT=25°C

Figure 33. Vol versus Iol for High sink (30mA) I/Oports at T=25°C

010203040

Iol (mA)

Vol (V)

T=-40°C T=25°C

T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

010203040

Iol (mA)

Vol (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curves represents typical variations and is given for guidance only

0 10203040

Iol (mA)

Vol (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curves represents typical variations and is given for guidance only

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ST62T52C ST62T62C/E62C

Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V

Figure 35. Voh versus Ioh on all I/O port at 25°C

Figure 36. Voh versus Ioh on all I/O port at Vdd=5V

0 10203040

Iol (mA)

Vol (V)

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

0 10203040

-2

Ioh (mA)

Voh (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curvesrepresents typical variations and is given for guidance only

0 10203040

-2

Ioh (mA)

Voh (V)

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

65/78

ST62T52C ST62T62C/E62C

Figure 37. Idd WAIT versus Vcc at 8 Mhz for OTP devices

Figure 38. Idd STOP versus Vcc for OTP devices

Figure 39. Idd STOP versus Vcc for ROM devices

This curves represents typical variations and is given for guidance only

0.5

1.5

2.5

Vdd

Idd WAIT(mA)

3V 4V 5V 6V

T=-40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

-2

Vdd

Idd STOP(µA)

3V 4V 5V 6V

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

-0.5

0.5

1.5

Vdd

Idd STOP(µA)

3V 4V 5V 6V

T = -40°C T=25°C T=95°C T = 125°C

66/78

ST62T52C ST62T62C/E62C

Figure 40. Idd WAIT versus Vcc at 8Mhz for ROM devices

Figure 41. Idd RUN versus Vcc at8 Mhz for ROM and OTP devices

Figure 42. LVD thresholds versus temperature

This curves represents typical variations and is given for guidanceonly

0.5

1.5

2.5

Vdd

Idd WAIT(mA)

3V 4V 5V 6V

T = -40°C T=25°C

T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

Vdd

Idd RUN (mA)

3V 4V 5V 6V

T=-40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

3.7

3.8

3.9

4.1

4.2

Temp

Vthresh.

-40°C25°C95°C125°C

Vup Vdn

67/78

ST62T52C ST62T62C/E62C

Figure 43. RC frequency versus Vcc for ROM ST626xB only

Figure 44. RC frequency versus Vcc (Except for ST626xB ROM devices)

This curves represents typical variations and is given for guidance only

3 3.5 4 4.5 5 5.5 6

0.1

MHz

VDD (volts)

Frequency

R=10K R=27K R=100K

This curves represents typical variations and is given for guidance only

3 3.5 4 4.5 5 5.5 6

0.1

MHz

VDD (volts)

Frequency

R=47K R=100K R=470K

68/78

ST62T52C ST62T62C/E62C

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA Figure 45. 16-Pin Plastic Dual In Line Package (B), 300-mil Width

Figure 46. 16-Pin Ceramic Side-Brazed Dual In-Line Package

Dim.

mm inches

Min Typ Max Min Typ Max

A 5.33 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195

b 0.36 0.56 0.014 0.022

b2 1.52 1.78 0.060 0.070

c 0.20 0.25 0.36 0.008 0.010 0.014

D 18.67 19.18 19.69 0.735 0.755 0.775

e 2.54 0.100

E1 6.10 6.35 7.11 0.240 0.250 0.280

L 2.92 3.30 3.81 0.115 0.130 0.150

Number of Pins

N 16

PDIP16

Dim.

mm inches

Min Typ Max Min Typ Max

A 3.78 0.149

A1 0.38 0.015

B 0.36 0.46 0.56 0.014 0.018 0.022

B1 1.14 1.37 1.78 0.045 0.054 0.070

C 0.20 0.25 0.36 0.008 0.010 0.014 D 19.86 20.32 20.78 0.782 0.800 0.818

D1 17.78 0.700

E1 7.04 7.49 7.95 0.277 0.295 0.313

e 2.54 0.100

G 6.35 6.60 6.86 0.250 0.260 0.270 G1 9.47 9.73 9.98 0.373 0.383 0.393 G2 1.02 0.040

L 2.92 3.30 3.81 0.115 0.130 0.150 S 1.27 0.050

Ø 4.22 0.166

Number of Pins

N16

CDIP16W

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ST62T52C ST62T62C/E62C

PACKAGE MECHANICAL DATA (Cont’d) Figure 47. 16-Pin Plastic Small Outline Package (M), 300-mil Width

Figure 1. 16-Pin Plastic Shrink Small Outline Package, 0.209” Width

THERMAL CHARACTERISTIC

Dim.

mm inches

Min Typ Max Min Typ Max

A 2.35 2.65 0.0926 0.1043

A1 0.10 0.0040

B 0.33 0.51 0.013 0.020 C 0.32 0.0125 D 10.10 10.50 0.3977 0.4133

E 7.40 7.60 0.2914 0.2992 e 1.27 0.050

H 10.01 10.64 0.394 0.419

h 0.25 0.74 0.010 0.029

K 0° 8° 0° 8°

L 0.41 1.27 0.016 0.050

G 0.10 0.004

Number of Pins

N16

SO16

Dim.

mm inches

Min Typ Max Min Typ Max

A 1.73 1.86 1.99 0.068 0.073 0.078

A1 0.05 0.13 0.21 0.002 0.005 0.008

B 0.25 0.38 0.010 0.015 C 0.09 0.20 0.004 0.008 D 6.07 6.20 6.33 0.239 0.244 0.249

E 7.65 7.80 7.90 0.301 0.307 0.311

E1 5.20 5.30 5.38 0.205 0.209 0.212

e 0.65 0.026 G 0.076 0.003 K 0° 4° 8° 0° 4° 8°

L 0.63 0.75 0.95 0.025 0.030 0.037

Number of Pins

N16

SSOP16

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

RthJA Thermal Resistance

PDIP16 55

°C/W

PSO16 75

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ST62T52C ST62T62C/E62C

7.2 ORDERING INFORMATION Table 22. OTP/EPROM VERSION ORDERING INFORMATION

Sales Type

Program

Memory (Bytes)

EEPROM (Bytes) Temperature Range Package

ST62E62CF1 1836 EPROM 64 0 to +70°C CDIP16W ST62T52CM6

ST62T52CM3

1836 OTP None

-40 to+ 85°C

-40 to + 125°C

PSO16

ST62T62CM6 ST62T62CM3

1836 OTP 64

-40 to+ 85°C

-40 to + 125°C

PSO16

ST62T52CB6 ST62T52CB3

1836 OTP None

-40 to+ 85°C

-40 to + 125°C

PDIP16

ST62T62CB6 ST62T62CB3

1836 OTP 64

-40 to+ 85°C

-40 to + 125°C

PDIP16

ST62T52CN6 ST62T52CN3

1836 OTP None

-40 to+ 85°C

-40 to + 125°C

SSOP16

ST62T62CN6 ST62T62CN3

1836 OTP 64

-40 to+ 85°C

-40 to + 125°C

SSOP16

November 1999 71/78

Rev. 2.7

ST62P52C ST62P62C

8-BIT FASTROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER AND EEPROM

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM: 64 bytes(none on ST62T52C)

■ 9 I/Opins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 5 I/Olines can sinkupto30mA todriveLEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timerwith 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator SafeGuard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 4 analog inputs

■ On-chip Clockoscillator canbe drivenbyQuartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port)

DEVICE SUMMARY

(See end of Datasheet for Ordering Information)

PDIP16

PSO16

SSOP16

DEVICE

ROM

(Bytes)

EEPROM

ST62P52C 1836 ST62P62C 1836 64

72/78

ST62P52C ST62P62C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION The ST62P52C and ST62P62C are the Factory

Advanced Service Technique ROM (FASTROM)

version of ST62T52C and ST62T62C OTP devices.

They offer the same functionality as OTPdevices, selecting as FASTROM options the options defined in the programmable option byte of the OTP version.

1.2 ORDERING INFORMATION

The following section deals with the procedure for transfer ofcustomer codes to STMicroelectronics.

1.2.1 Transfer of Customer Code

Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes mustbe set to FFh.

The selected options are communicated to STMicroelectronics using the correctly filled OPTION LIST appended.

1.2.2 Listing Generation and Verification

When STMicroelectronics receives the user’s ROM contents, a computer listing is generated from it. This listing refers exactly to the ROM contents and options which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listingforms apartofthecontractual agreement for the production of the specific customer MCU.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Table 1. ROM Memory Map for ST62P52C/P62C

Table 2. FASTROM version Ordering Information

(*) Advanced information

Device Address Description

0000h-087Fh 0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Sales Type ROM EEPROM (Bytes) Temperature Range Package

ST62P52CM1/XXX ST62P52CM6/XXX ST62P52CM3/XXX (*)

1836 Bytes None

0to+70°C

-40 to + 85°C

-40 to + 125°C PSO16

ST62P62CM1/XXX ST62P62CM6/XXX ST62P62CM3/XXX (*)

1836 Bytes 64

0to+70°C

-40 to + 85°C

-40 to + 125°C

ST62P52CB1/XXX ST62P52CB6/XXX ST62P52CB3/XXX (*)

1836 Bytes None

0to+70°C

-40 to + 85°C

-40 to + 125°C

PDIP16

ST62P62CB1/XXX ST62P62CB6/XXX ST62P62CB3/XXX (*)

1836 Bytes 64

0to+70°C

-40 to + 85°C

-40 to + 125°C

ST62P52CN1/XXX ST62P52CN6/XXX ST62P52CN3/XXX (*)

1836 Bytes None

0to+70°C

-40 to + 85°C

-40 to + 125°C

SSOP16

ST62P62CN1/XXX ST62P62CN6/XXX ST62P62CN3/XXX (*)

1836 Bytes 64

0to+70°C

-40 to + 85°C

-40 to + 125°C

73/78

ST62P52C ST62P62C

ST62P52C and ST62P62C FASTROMMICROCONTROLLER OPTION LIST

Customer . . . . . ....................

Address . . . . . ....................

.........................

Contact . . . . . ....................

Phone No . . . . . ....................

Reference . . . . . ....................

STMicroelectronics references Device: [ ] ST62P52C [ ] ST62P62C Package: [ ] Dual in Line Plastic [ ] SmallOutline Plasticwith condionning:

[ ] Standard (Stick) [ ] Tape & Reel

[ ]Shrink Small Outline Plastic

Temperature Range: [ ] 0°Cto+70°C[]-40°Cto+85°C[]-40°C to + 125°C

Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator

[ ] RC Network

Watchdog Selection: [ ] Software Activation

[ ] Hardware Activation

Power on Reset Delay [ ] 32768cycle delay

[ ] 2048 cycle delay

Readout Protection: [ ] Disabled

[ ] Enabled

External STOP Mode Control [ ] Enabled

[ ] Disabled

PB2-PB3 Pull-Up at RESET [ ] Enabled

[ ] Disabled

LVD Reset [ ] Enabled

[ ] Disabled

ADC Synchro [ ] Enabled

[ ] Disabled

Oscillator Safe Guard [ ] Enabled

[ ] Disabled

Comments : Supply Operating Range in the application: Oscillator Fequency in the application:

Notes . . . . . ....................

Signature . . .. . ....................

Date . . . . . ....................

74/78

ST62P52C ST62P62C

Notes:

November 1999 75/78

Rev. 2.7

ST6252C ST6262B

8-BIT ROM MCUs WITH A/D CONVERTER,

SAFE RESET AUTO-RELOAD TIMER, ROM AND EEPROM

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM: 64 bytes(none on ST62T52C)

■ 9 I/Opins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 5 I/Olines can sinkupto30mA todriveLEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timerwith 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator SafeGuard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 4 analog inputs

■ On-chip Clockoscillator canbe drivenbyQuartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port)

DEVICE SUMMARY

(See end of Datasheet for Ordering Information)

PDIP16

PSO16

SSOP16

DEVICE

ROM

(Bytes)

EEPROM LVD & OSG

ST6252C 1836 - Yes ST6262B 1836 64 No

76/78

ST6252C ST6262B

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6252C and ST6262B are mask programmed ROM version of ST62T52C and ST62T62C OTP devices.

They offer the same functionality as OTPdevices, selecting as ROM options the options defined in the programmableoptionbyte of the OTP version, except the LVD &OSGoptions that are not available on the ST6262B ROMdevice.

Figure 1. Programming wave form

1.2 ROM READOUT PROTECTION

If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to prevent any access to theprogram memory content.

In case the user wants to blow this fuse, highvoltage must be applied onthe TEST pin.

Figure 2. Programming Circuit

Note: ZPD15 is used for overvoltage protection

0.5s min

TEST

14V typ

TEST

100mA

4mA typ

VR02001

max

150 µstyp

VR02003

TEST

100nF

47mF

PROTECT

100nF

ZPD15 15V

14V

77/78

ST6252C ST6262B

ST6252C and ST6262B MICROCONTROLLER OPTION LIST

Customer . . . . . ....................

Address . . . . . ....................

.........................

Contact . . . . . ....................

Phone No . . . . . ....................

Reference . . . . . ....................

STMicroelectronics references Device: [ ] ST6252C [ ] ST6262B Package: [ ] Dual in Line Plastic [ ] SmallOutline Plasticwith condionning:

[ ] Standard (Stick) [ ] Tape & Reel

[ ]Shrink Small Outline Plastic Temperature Range: [ ] 0°Cto+70°C[]-40°Cto+85°C[]-40°C to + 125°C Special Marking: [ ] No [ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ” Authorized characters are letters, digits, ’.’,’-’, ’/’ and spaces only. Maximum character count: DIP16: 9

SO16: 5

Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator

[ ] RC Network

Watchdog Selection: [ ] Software Activation

[ ] Hardware Activation

Power on Reset Delay [ ] 32768cycle delay

[ ] 2048 cycle delay

ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)

[ ] Enabled (Fuse can be blown by the customer)

Note: No part is delivered with protected ROM.

The fuse must be blown for protection to be effective. External STOP Mode Control [ ] Enabled [ ] Disabled PB2-PB3 Pull-Up at RESET [ ] Enabled [ ] Disabled LVD Reset* [ ] Enabled [ ] Disabled ADC Synchro* [ ] Enabled [ ] Disabled Oscillator Safe Guard* [ ] Enabled [ ] Disabled

*ST6252C only

Comments : Supply Operating Range in the application: Oscillator Fequency in the application:

Notes . . . . . ....................

Signature . . .. . ....................

Date . . . . . ....................

78/78

ST6252C ST6262B

1.3 ORDERING INFORMATION

The following section deals with the procedure for transfer ofcustomer codes to STMicroelectronics.

1.3.1 Transfer of Customer Code

Customer code is made up of the ROM contents and the list of the selected mask options. The ROM contents are to be sent on diskette, or by electronic means, withthe hexadecimal file generated by the development tool. All unused bytes must be set to FFh.

The selected mask options are communicated to STMicroelectronics using the correctly filled OPTION LIST appended.

1.3.2 Listing Generation and Verification

When STMicroelectronics receives the user’s ROM contents, a computer listing is generated

from it. Thislisting refersexactlytothemaskwhich will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Table 1. ROM Memory Map for ST6252C/62B

Table 2. ROM version Ordering Information

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of useof suchinformation nor forany infringement ofpatents or otherrights ofthird parties which may resultfrom itsuse. No license is granted by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval ofSTMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys alicense under the Philips I2C Patent. Rights to use these components in an

C system is granted provided that the system conforms to the I2C Standard Specification asdefined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France -Germany - Hong Kong - India - Italy -Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

Device Address Description

0000h-087Fh 0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Sales Type ROM EEPROM (Bytes) Temperature Range Package

ST6252CB1/XXX ST6252CB6/XXX ST6252CB3/XXX

1836 Bytes None

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

PDIP16

ST6252CM1/XXX ST6252CM6/XXX ST6252CM3/XXX

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

PSO16

ST6252CN1/XXX ST6252CN6/XXX ST6252CN3/XXX

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

SSOP16

ST6262BB1/XXX ST6262BB6/XXX ST6262BB3/XXX

1836 Bytes 64

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

PDIP16

ST6262BM1/XXX ST6262BM6/XXX ST6262BM3/XXX

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

PSO16

ST6262BN1/XXX ST6262BN6/XXX ST6262BN3/XXX

0 to +70°C

-40 to+ 85°C

-40 to + 125°C

SSOP16

Datasheet ST62T62CM6, ST62T62CM3, ST62T62CB6, ST62T62CB3, ST62T52CM6 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual