Datasheet ST62T60CB3, ST62T60CM6, ST62T60CM3, ST62T60CB6, ST62T53CM6 Datasheet (SGS Thomson Microelectronics)

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November 1999 1/86

Rev. 2.6

ST62T53C/T60C/T63C

ST62E60C

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM:64/128bytes(noneonST62T53C)

■ User Programmable Options

■ 13 I/O pins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 6 I/Olinescan sink up to 30mA to drive LEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator SafeGuard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 7 analog inputs

■ 8-bit Synchronous Peripheral Interface (SPI)

■ On-chip Clockoscillator can be driven by Quartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port).

DEVICE SUMMARY

DEVICE OTP (Bytes)

EPROM

(Bytes)

EEPROM

ST62T53C 1836 - ST62T60C 3884 - 128 ST62T63C 1836 - 64 ST62E60C - 3884 128

PDIP20

PSO20

CDIP20W

(See endof Datasheet for Ordering Information)

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Table of Contents

Document

Page

ST62T53C/T60C/T63C/ST62E60C . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . .. . . . ................................................ 5

1.1 INTRODUCTION . . . . . .. . .. . . ............................................. 5

1.2 PIN DESCRIPTIONS . . . . . . ................................................6

1.3 MEMORY MAP . . . . . . . . . . ................................................7

1.3.1 Introduction . . . ..................................................... 7

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . ................................. 8

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . ................................ 9

1.3.4 Stack Space . . . . . . . . . . . . ............................................9

1.3.5 Data Window Register (DWR) . ........................................ 10

1.3.6 Data RAM/EEPROM Bank Register (DRBR) . .. . .. . . .. . . . . . . . . . . . . . . . . . . . . 11

1.3.7 EEPROM Description . . . . . . . . . . . . . . .. . . . . ........................... 12

1.4 PROGRAMMING MODES . . . . . .. . .. . . . . . . . . .. . . . . . . . . . .. . . . . .. . . . . . . . . . . . . 14

1.4.1 Option Bytes . . . . . . . . . . . . . . .. . . . . . . . ............................... 14

1.4.2 EPROM Erasing .................................................... 15

2 CENTRAL PROCESSING UNIT . . ............................................... 16

2.1 INTRODUCTION . . . . . .. . .. . . ............................................16

2.2 CPU REGISTERS . . . .................................................... 16

3 CLOCKS, RESET, INTERRUPTS AND POWERSAVING MODES . .................... 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . ........................................... 18

3.1.1 Main Oscillator . .. . . . . . . .. . .. . . . . . . ................................. 18

3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . 19

3.1.3 Oscillator Safe Guard . . . . . ........................................... 19

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.1 RESET Input . . .................................................... 23

3.2.2 Power-on Reset .................................................... 23

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . .. ................................. 24

3.2.4 LVD Reset . . . . .. . . . ...............................................24

3.2.5 Application Notes . . . ................................................ 24

3.2.6 MCU Initialization Sequence . . . . . . . . .................................. 25

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . .................................. 27

3.3.1 Digital Watchdog Register (DWDR) . . . . . . .. . . . . .. . .. . . .. . . . . . . . . . . . . . . . . 29

3.3.2 Application Notes . . . ................................................ 29

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.4.1 Interrupt request . ...................................................31

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . .. ................................. 32

3.4.3 Interrupt Option Register(IOR) . . . . . . . . . . . . . . . . . . . . . . . . . ............... 33

3.4.4 Interrupt sources . . . . . . . . . . . ........................................33

3.5 POWER SAVING MODES . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 35

3.5.1 WAIT Mode ....................................................... 35

3.5.2 STOP Mode . .. . . .. . ...............................................35

3.5.3 Exit from WAIT and STOP Modes . . . . .................................. 36

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Page

4 ON-CHIP PERIPHERALS . . . .. . . . . . . ........................................... 37

4.1 I/O PORTS . . . . . . .. . . .. . . . . . . ........................................... 37

4.1.1 Operating Modes . . . . . . .. . . . . . . . . . . . . . . . . ........................... 38

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . 39

4.1.3 AR Timer Alternatefunction Option . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . 41

4.1.4 SPI Alternate function Option . . ........................................41

4.2 TIMER . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ................................. 43

4.2.1 Timer Operation . . . . . . . .. . . . . . . . . . . . . ............................... 44

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . ................................44

4.2.3 Application Notes . . . ................................................ 44

4.2.4 Timer Registers . . . . . ...............................................45

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . .............................. 46

4.3.1 AR Timer Description . . . . . . . . ........................................46

4.3.2 Timer Operating Modes . . .. . .. . . .. . .................................. 46

4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . ................................. 50

4.4 A/D CONVERTER (ADC) . . ............................................... 52

4.4.1 Application Notes . . . ................................................ 52

4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . .. . . . . . . ...........54

4.5.1 SPI Registers . . . . . . . ...............................................55

4.6 SPI TIMING DIAGRAMS . . . . . . . ........................................... 57

5 SOFTWARE . . . . . . . . . . . . . . . . . ............................................... 59

5.1 ST6 ARCHITECTURE . ................................................... 59

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . .................................. 59

5.3 INSTRUCTION SET . . . . . . . ............................................... 60

6 ELECTRICAL CHARACTERISTICS . .. . . . . . . . . . . . . . .............................. 65

6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................ 65

6.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 66

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........67

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 68

6.5 A/D CONVERTERCHARACTERISTICS . .. . . . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . .. . 69

6.6 TIMER CHARACTERISTICS . . . . ...........................................69

6.7 SPI CHARACTERISTICS . . ............................................... 69

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . ........................... 69

7 GENERAL INFORMATION . . .. . . . . . . ........................................... 75

7.1 PACKAGE MECHANICALDATA . . . . . . .. . . . . . . . . . ........................... 75

7.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 76

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Table of Contents

Document

Page

ST62P53C/P60C/P63C . . . . .............................77

1 GENERAL DESCRIPTION . .. . . . ..................................................78

1.1 INTRODUCTION . . . . . .. . .. . . ...............................................78

1.2 ORDERING INFORMATION . . . . . . . . . . . . . ..................................... 78

1.2.1 Transfer of Customer Code . . . . . . . . . . .................................... 78

1.2.2 Listing Generation and Verification . . . . .................................... 78

ST6253C/60B/63B .....................................81

1 GENERAL DESCRIPTION . .. . . . ..................................................82

1.1 INTRODUCTION . . . . . .. . .. . . ...............................................82

1.2 ROM READOUT PROTECTION .. . .. . . . . . . . ...................................82

1.3 ORDERING INFORMATION . . . . . . . . . . . . . ..................................... 84

1.3.1 Transfer of Customer Code . . . . . . . . . . .................................... 84

1.3.2 Listing Generation and Verification . . . . .................................... 84

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ST62T53C/T60C/T63C ST62E60C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62T53C, ST62T60C, ST62T63C and ST62E60C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.

The ST62E60C isthe erasable EPROM versionof the ST62T60C device, which may be used to emulate the ST62T53C, ST62T60C and ST62T63C devices, as well as the respective ST6253C, ST6260B and ST6263B ROM devices.

OTP and EPROM devices are functionally identical. The ROM basedversions offer the same functionality selecting as ROM options the options de-

fined in the programmable option byte of the OTP/ EPROM versions.

OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide rangeof applications where frequent code changes, multiple code versions or last minute programmability are required.

These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability (except ST62T53C), a serial port communication interface, an 8-bit A/D Converter with 7 analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, applianceand industrial applications.

Figure 1. Block Diagram

TEST

NMI INTERRUPT

PROGRAM

STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6

POWER

SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

8-BIT

A/D CONVERTER

PA0..PA3 / Ain

PB0..PB3 / 30 mA Sink

DDVSS

OSCin OSCout RESET

WATCHDOG

MEMORY

PB6 / ARTimin / 30 mA Sink

PORT C

PC2 / Sin / Ain PC3 / Sout / Ain

SPI (SERIAL

PERIPHERAL

INTERFACE)

AUTORELOAD

TIMER

PC4 / Sck / Ain

PB7 / ARTimout / 30 mA Sink

128 Bytes

1836 bytesOTP 3884 bytesOTP

3884 bytesEPROM

(ST62T53C,T63C)

(ST62T60C)

(ST62E60C)

DATA EEPROM

64 Bytes

128 Bytes

(ST62T60C/E60C)

(ST62T63C)

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ST62T53C/T60C/T63C ST62E60C

1.2 PIN DESCRIPTIONS VDDand VSS. Power is supplied to the MCU via

these two pins. VDDis the power connection and VSSis the ground connection.

OSCin and OSCout. These pins are internally connected tothe on-chip oscillatorcircuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active-low RESET pin is used to restart themicrocontroller.

TEST/VPP. The TEST must be held at VSSfor nor- mal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/ OTP programming Mode is entered.

NMI. TheNMI pin provides thecapability for asynchronous interruption,by applying anexternal non maskable interrupt to the MCU. The NMI input is falling edge sensitive. It is providedwith anon-chip pullup resistor (if option has been enabled), and Schmitt triggercharacteristics.

PA0-PA3. These 4 lines are organized as one I/O port (A). Each line may be configured under software controlas inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pulloutputs, analog inputs for the A/D converter.

PB0-PB3. These 4 lines are organized as one I/O port (B). Each line may be configured under software controlas inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pulloutputs. PB0-PB3 can also sink 30mA for direct LED driving.

PB6/ARTIMin, PB7/ARTIMout.These pins are either Port B I/O bits or the Input and Outputpins of the AR TIMER. To be used as timerinput function PB6 has to be programmed as input with or without pull-up. A dedicated bit inthe ARTIMER Mode Control Register sets PB7as timer output function. PB6-PB7 can also sink 30mA for direct LED driving.

PC2-PC4. These 3 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output. PC2-PC4 can also be used as respectively Data in, Data out and Clock I/O pins for the on-chip SPI to carry the synchronous serial I/O signals.

Figure 2. ST62T53C/T60C/T63C/E60C Pin

Configuration

1 2 3 4 5 6 7 8 9

PB0 PB1

/TEST

PB2 PB3

Ain/PA0

PC2 / Sin / Ain

RESET

PA1/Ain

ARTIMin/PB6

ARTIMout/PB7

PC3 / Sout / Ain PC4 / Sck / Ain NMI

OSCin

OSCout

PA2/Ain

PA3/Ain

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ST62T53C/T60C/T63C ST62E60C

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in thesethree memory spacesis described in the following paragraphs.

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.

Figure 3. Memory Addressing Diagram

PROGRAM SPACE

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

DATA RAM

BANK SELECT

WINDOW SELECT

RAM

X REGISTER Y REGISTER V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW

RAM / EEPROM BANKING AREA

000h

03Fh 040h

07Fh 080h 081h 082h 083h 084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

MEMORY

DATA READ-ONLY

MEMORY

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed viathe 12-bit ProgramCounter register (PC register).

1.3.2.1 Program Memory Protection

The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

Figure 4. ST62E60C/T60C Program

Memory Map

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Once the Readout Protectionis activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protectionset can thereforenot be accepted.

Figure 5. ST62T53C/T63C Program

Memory Map

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP/EPROM)

3872 BYTES

0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

0080h

(*) Reserved areas should be filled with 0FFh

007Fh

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP)

1824 BYTES

0F9Fh 0FA0h 0FEFh

0FF0h

0FF7h

0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

087Fh

(*) Reserved areas should be filled with0FFh

0880h

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d)

1.3.3 Data Space

Data Spaceaccommodates all the data necessary for processingthe user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/ EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T53C, T60C, T63C and ST62E60Cdevices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register).

Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as wellas thecurrent program counter contents.

Table 1. Additional RAM/EEPROM Banks

Table 2. ST62T53C, T60C, T63C and ST62E60C Data Memory Space

Device RAM EEPROM

ST62T53C 1 x 64 bytes -

ST62T60C/E60C 1 x 64 bytes 2 x 64bytes

ST62T63C 1 x 64 bytes 1 x 64bytes

RAM and EEPROM

000h

03Fh

DATA ROM WINDOW AREA

040h

07Fh X REGISTER 080h Y REGISTER 081h V REGISTER 082h

W REGISTER 083h

DATA RAM 60 BYTES

084h

0BFh

PORT A DATA REGISTER 0C0h PORT B DATA REGISTER 0C1h

PORT C DATA REGISTER 0C2h

RESERVED 0C3h PORT A DIRECTION REGISTER 0C4h PORT B DIRECTION REGISTER 0C5h PORT C DIRECTIONREGISTER 0C6h

RESERVED 0C7h

INTERRUPT OPTION REGISTER 0C8h*

DATA ROM WINDOW REGISTER 0C9h*

RESERVED

0CAh

0CBh PORT A OPTION REGISTER 0CCh PORT B OPTION REGISTER 0CDh PORT C OPTION REGISTER 0CEh

RESERVED 0CFh

A/D DATA REGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER PRESCALER REGISTER 0D2h

TIMER COUNTER REGISTER 0D3h

TIMER STATUS CONTROL REGISTER 0D4h

AR TIMER MODE CONTROL REGISTER 0D5h AR TIMERSTATUS/CONTROLREGISTER1 0D6h AR TIMERSTATUS/CONTROLREGISTER2 0D7h

WATCHDOG REGISTER 0D8h

AR TIMERRELOAD/CAPTURE REGISTER 0D9h

AR TIMERCOMPARE REGISTER 0DAh

AR TIMER LOAD REGISTER 0DBh

OSCILLATOR CONTROL REGISTER 0DCh*

MISCELLANEOUS 0DDh

RESERVED

0DEh 0DFh

SPI DATA REGISTER 0E0h

SPI DIVIDER REGISTER 0E1h

SPI MODE REGISTER 0E2h

RESERVED

0E3h 0E7h

DATA RAM/EEPROM REGISTER 0E8h*

RESERVED 0E9h

EEPROM CONTROL REGISTER

(except ST62T53C)

0EAh

RESERVED

0EBh 0FEh

ACCUMULATOR 0FFh

* WRITE ONLY REGISTER

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d)

1.3.5 Data Window Register (DWR)

TheData read-only memorywindowislocatedfrom address 0040h toaddress 007Fh in Data space. It allows directreading of 64consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memoryby writingthe appropriate code inthe Data Window Register (DWR).

The DWR can beaddressed like any RAM location in theData Space,it is however a write-only register andtherefore cannotbe accessed using singlebit operations. This register is used to position the 64-byte read-onlydata window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the registeraddress given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 6 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Data Window Register (DWR)

Address: 0C9h — Write Only

Bits 6, 7= Not used. Bit 5-0 = DWR6-DWR0:

Data read-only memory

Window Register Bits.

These are the Data readonly memory Window bits that correspond to the upper bits of the dataread-only memory space.

Caution:

This register is undefined on reset. Neither read nor single bit instructionsmay beused to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot saveand then restore the register’s previous contents. If it is impossible to avoid writing to the DWRduring the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also writeto the image register. The image register must be written first so that, if aninterrupt occurs between the two instructions, the DWR is not affected.

Figure 6. Data read-only memory Window Memory Addressing

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

765432 0

543210

READ

67891011

VR01573C

DATA SPACE ADDRESS

59h

000

Example:

(DWR)

DWR=28h

1100000001

ROM

ADDRESS:A19h

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d)

1.3.6 Data RAM/EEPROM Bank Register (DRBR)

Address: E8h — Write only

Bit 7-5= These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2. Bit 3-2- Reserved. These bits are not used. Bit 1 - DRBR1. This bit, when set, selects

EEPROM Page 1, when available. Bit 0 - DRBR0. This bit, when set, selects

EEPROM Page 0, when available. The selection of the bank is madebyprogramming

the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1.No more than onebank should be set at a time.

The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space.The bank number hasto beloaded in the DRBRregister and the instruction has to point

to the selectedlocation as if it was in bank 0 (from 00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs.

Notes : Care is requiredwhen handling the DRBR register

as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Care must also be taken not to change the E

PROM page (when available) when the parallel writing mode is set for theE PROM, as defined in EECTL register.

Table 3. Data RAM Bank Register Set-up

---

DRBR

DRBR1DRBR

DRBR ST62T53C ST62T60C/E60C ST62T63C

00 None None None

01 Not Available EEPROM Page 0 EEPROM Page 0

02 Not Available EEPROM Page 1 Not Available

08 Not Available Not Available Not Available

10h RAM Page 2 RAM Page 2 RAM Page 2

other Reserved Reserved Reserved

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage.

Data spacefrom 00h to 3Fh is paged as described in Table 4. EEPROM locations are accessed directly by addressing these paged sections of data space.

The EEPROM does notrequire dedicated instructions forreadorwrite access.Once selected viathe Data RAM Bank Register, the active EEPROM page is controlledby the EEPROM Control Register (EECTL),which is described below.

Bit E20FFof the EECTL registermust beresetprior to any write or read access to the EEPROM. If no bank hasbeen selected, or if E2OFF is set, any access is meaningless.

Programming must be enabled by setting the E2ENA bitof the EECTL register.

The E2BUSY bit of the EECTL register is setwhen the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless.

Provided E2OFFand E2BUSY are reset, an EEPROM location is read just like any other data location, alsoin terms of accesstime.

Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed andpower consumption advantages, the latter being particularly important in battery powered circuits).

General Notes: Data should be written directly to the intended ad-

dress in EEPROM space.There is nobuffer memory between data RAM andthe EEPROM space.

When the EEPROM is busy (E2BUSY = “1”) EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 arereserved and must never be set.

Care is required whendealing withthe EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine.

If it is impossible to avoid writing to this register within an interrupt service routine, animage of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected.

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest

power-consumption.

Dataspace addresses. Banks 0 and 1.

Byte 0 1234567 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h

Up to8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP(Cont’d) Additional Notes on Parallel Mode:

If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. After the ROW addressis latched,the MCUcan only “see” the selected EEPROM row and any attempt to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2 is set.

As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in allor in part ofthe ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 andaccesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected.

Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must setthe E2PAR2bit betweentwo parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycleand the E2PAR1 bitwill be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low.The E2PAR1 bitcan be setby the user, only if the E2ENA and E2PAR2 bits are also set.

Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set.

EEPROM Control Register (EECTL) Address: EAh — Read/Write Reset status: 00h

Bit 7 =D7:

Unused.

Bit6 = E2OFF:

Stand-byEnable Bit.

WRITE ONLY. Ifthisbitis setthe EEPROM isdisabled(anyaccess will bemeaningless)and thepower consumptionof the EEPROM is reduced to its lowest value.

Bit 5-4 = D5-D4:

Reserved.

MUST bekept reset.

Bit 3 =E2PAR1:

Parallel Start Bit.

WRITE ONLY. OnceinParallelMode,assoonastheuser software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. Thisbit is internally reset at the end of the programming procedure. Note that less than 8 bytescan bewritten ifrequired, theundefined bytes being unaffected by the parallelprogrammingcycle;this is explainedin greater detail in the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2:

Parallel Mode En. Bit.

WRITE ONLY. This bitmust be set by theuser programin order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytesare considered asa row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 arethe changing bits, as illustrated in Table 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged.

Bit 1 = E2BUSY:

EEPROM Busy Bit.

READ ONLY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The userprogram shouldtest it before any EEPROM read orwrite operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed.

Bit 0 =E2ENA:

EEPROM Enable Bit.

WRITE ONLY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.

The EEPROM is disabled as soon as a STOP instruction is executed in order to achieve the lowest power-consumption.

E2O

D5 D4

E2PAR1E2PAR2E2BUSYE2E

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ST62T53C/T60C/T63C ST62E60C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configurationcapability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chipreset is activated.

It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING modeof the programmer.

The option bytes are located in a non-user map. No address has to bespecified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D13. Reserved. Must be cleared. ADC SYNCHRO.When set, an A/D conversion is

started upon WAIT instruction execution, in order to reduce supply noise.When this bit is low, an A/ D conversion is started as soon as the STA bit of the A/D Converter Control Registeris set.

D11. Reserved,must be set to one. D10. Reserved,must be cleared. NMI PULL.

NMI Pull-Up

. This bit must be set high to configure the NMI pin with a pull-up resistor. When itis low, no pull-up is provided.

LVD.

LVD RESETenable.

When this bitis set, safe

RESET is performed by MCU when the supply

voltage is too low. When this bit is cleared, only power-on reset or external RESETare active.

PROTECT.

Readout Protection.

This bitallows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

EXTCNTL.

External STOP MODE control.

. When EXTCNTL is high, STOP mode is available with watchdog active by setting NMI pin to one. When EXTCNTL is low, STOP mode is not available with the watchdog active.

PB2-3 PULL. When set this bit removespull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.

PB0-1 PULL. When set this bit removespull-up at reset on PB0-PB1 pins. When cleared PB0-PB1 pins have an internal pull-up resistor at reset.

WDACT. This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low.

DELAY. This bit enables the selection of the delay internally generated after the internal reset (external pin, LVD, or watchdog activated) is released. When DELAY is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when DELAY is high.

OSCIL.

Oscillator selection

. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided.

OSGEN.

Oscillator Safe Guard

. This bit must be set high to enable the Oscillator Safe Guard. When this bit is low, the OSG is disabled.

The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode).

PROTECT

EXTC-

NTL

PB2-3

PULL

PB0-1

PULL

WDACT

DE-

LAY

OSCIL OSGEN

15 8

---

ADC

SYNCHRO

NMI

PULL

LVD

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ST62T53C/T60C/T63C ST62E60C

PROGRAMMING MODES (Cont’d)

1.4.2 EPROM Erasing

The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is exposed tolight with a wavelengths shorterthan approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the MCUs packages be coveredby an opaquelabel to

prevent unintentional erasure problems when testing the application in suchan environment.

The recommended erasure procedure of the MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A. The integrated dose (i.e.U.V. intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000µW/cm2power rating. The ST62E60C should be placed within 2.5cm(1Inch) of the lamp tubes during erasure.

16/86

ST62T53C/T60C/T63C ST62E60C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPUCoreof ST6 devicesis independentofthe I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 7; the controller being externally linked to both the Reset and Oscillator circuits, while thecore is linkedto thededicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

TheST6FamilyCPUcorefeatures sixregistersand three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They canalso be accessed with the direct, shortdirect, orbit direct addressing modes. Accordingly, the ST6 instruction set can usethe indirect registers as any other register of the data space.

Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locationsat addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

Figure 7. ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

17/86

ST62T53C/T60C/T63C ST62E60C

CPU REGISTERS (Cont’d)

However, if theprogram space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC.The program counter can be changedin the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- Reset PC= Reset vector

- RET & RETIinstructionsPC= Pop (stack)

- Normal instructionPC= PC + 1

Flags (C, Z). TheST6 CPU includes three pairs of flags (Carryand Zero), eachpair beingassociated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation,another pair is usedduring Interrupt mode (CI, ZI), anda third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching andthus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction;it also participates inthe rotate left instruction.

The Zero flag isset ifthe result of the lastarithmetic or logical operation was equal to zero; otherwise itis cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interruptor a RETI instructions occurs. As the NMI mode is

automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When asubroutine call (or interrupt request)occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its “deepest” position if morethan 6 nested calls or interrupts areexecuted, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and aRET orRETI isexecuted. In this case the nextinstruction will be executed.

Figure 8. ST6 CPU Programming Mode

SHORT

DIRECT

ADDRESSING

MODE

VREGISTER

W REGISTER

PROGRAMCOUNTER

SIX LEVELS

STACKREGISTER

CZNORMAL FLAGS

INTERRUPTFLAGS

NMI FLAGS

INDEX

VA000 4 23

b0b11

ACCUM ULATO R

Y REG. POINTER

X REG. POINTER

18/86

ST62T53C/T60C/T63C ST62E60C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillatorwhich can be driven byan external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor (R

NET

). In addition, a Low FrequencyAuxiliary Oscillator (LFAO)can be switched in for security reasons, to reduce powerconsumption, orto offerthe benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automatically limits the internal clock frequency (f

INT

)asa function of VDD, inorder toguarantee correct operation. These functions are illustrated in Figure 2, Figure 3, Figure 4 and Figure 5.

A programmabledivider on F

INT

is also provided in order to adjust the internal clock of theMCU to the best power consumption and performance tradeoff.

Figure 1 illustrates various possible oscillator configurations using anexternal crystal or ceramic resonator, an external clock input, anexternal resistor (R

NET

), or the lowest cost solution using only the LFAO. CL1anCL2shouldhave acapacitancein the range 12 to22 pF foran oscillatorfrequency inthe 4-8 MHz range.

The internal MCU clock frequency (f

INT

) is divided by 12to drivethe Timer, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 4.

With an 8MHz oscillator frequency, thefastest machine cycle is therefore 1.625µs.

A machine cycleis the smallest unit of time needed to executeanyoperation(for instance,toincrement the Program Counter). An instruction may require two, four, or five machine cycles forexecution.

3.1.1 Main Oscillator

The oscillatorconfigurationmay bespecified byselectingtheappropriate option.WhentheCRYSTAL/ RESONATORoptionisselected,itmustbeusedwith a quartz crystal,a ceramic resonator oran external signalprovidedontheOSCinpin.WhentheRCNETWORK option is selected, the system clockis generated by an external resistor.

The main oscillator can be turned off (when the OSG ENABLED option isselected) by setting the OSCOFF bit of the ADC Control Register. The Low Frequency Auxiliary Oscillator isautomatically started.

Figure 9. Oscillator Configurations

INTEGRATED CLOCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

out

L1n

ST6xxx

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

OSC

out

NET

ST6xxx

RC NETWORK

RC NETWORK option

19/86

ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/DConverter Control Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the softwareinstruction at f

LFAO

clock frequency.

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without anyexternal components.Lastly, itacts as a safetyoscillator in caseof main oscillator failure.

This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically startsone of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillatordefective, no clock circuitry provided, main oscillator switched off...).

User code,normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f

LFAO

frequency.The A/D converter accuracy is decreased, since the internal frequency is below 1MHz.

At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay untilthe Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

ADCR

Address: 0D1h — Read/Write

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

ADC ControlRegister

. These bits are reserved for

ADC Control. Bit 2 = OSCOFF. When low, this bit enables main

oscillator torun. The mainoscillator is switched off when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affordsdrastically increasedoperational integrity in ST62xx devices. The OSG circuit provides three basic func-

tions: it filtersspikes from theoscillator lines which would result inover frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumptionor to provide afixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct operation even if the power supply should drop.

The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewed as a filter whose cross-over frequency is device dependent.

Spikes on the oscillatorlines result in an effectively increased internal clock frequency.In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The OSG filters out such spikes (as illustrated in Figure

2). In all cases, when the OSG isactive, the maximum internal clock frequency, f

INT

, is limited to

OSG

, which is supply voltage dependent. This re-

lationship is illustrated in Figure 5. When the OSG is enabled, the Low Frequency

Auxiliary Oscillator maybe accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figure 3).

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on VDD), and below f

OSG

: the maximum authorised frequen-

cy with OSG enabled. Note. The OSGshould be used wherever possible

as it provides maximumsafety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency to f

OSG

Warning: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and amaximum value and is not accurate.

For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature).

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

20/86

ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d) Figure 10. OSG FilteringPrinciple

Figure 11. OSG Emergency Oscillator Principle

(1)

VR001932

(3)

(2)

(4)

(1) (2)

(3) (4)

Maximum Frequency for the device to work correctly Actual Quartz Crystal Frequency at OSCin pin Noise from OSCin

Resulting Internal Frequency

Main

VR001933

Internal

Emergency

Oscillator

Frequency

Oscillator

21/86

ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d) Oscillator ControlRegisters

Address: DCh — Write only Reset State: 00h

Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. Must be kept

cleared. Bit 2. Reserved. Must be kept low. RS1-RS0. These bits select the division ratio of

the OscillatorDivider in order to generate the internal frequency. The following selctions are available:

Note: Care is required when handling the OSCR register as some bits are write only. For this reason, it isnot allowed to change the OSCR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to OSCR it mustwrite also tothe imageregister. The image register must be written first, so if an interrupt occurs between the two instructions the OSCR is notaffected.

----

OSCR

- RS1 RS0

RS1 RS0 Division Ratio

0 0 1 1

0 1 0 1

1 2 4 4

22/86

ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d) Figure 12. Clock Circuit Block Diagram

Figure 13. Maximum Operating Frequency (f

MAX

) versus Supply Voltage (VDD)

Notes:

1. In this area, operation is guaranteed at the quartz crystal frequency.

2. When the OSG is disabled, operation in this area isguaranteed at the crystal frequency. When the OSGis enabled, operation in this area isguaranteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

area is guaranteed at the quartz crystalfrequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a f

OSG.

4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f

OSG.

MAIN

OSCILLATOR

OSG

LFAO

U X

Core

:13

:12

TIMER 1

Watchdog

POR

INT

Main Oscillator off

OSCILLATOR

DIVIDER RS0,RS1

2.5 3.6 4 4.5 5 5.5 6

Maximum FREQUENCY (MHz)

SUPPLY VOLTAGE (V

)

FUNCTIONALITY IS NOT

OSG

Min (at 85°C)

GUARANTEED

IN THIS AREA

VR01807J

OSG

Min (at 125°C)

23/86

ST62T53C/T60C/T63C ST62E60C

3.2 RESETS

The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-onReset; – by the digital Watchdog peripheral timing out. – by LowVoltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used toreset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDDhas completed its rising phase and that theoscillator is running correctly (normal RUN or WAIT modes). The MCU is keptin the Reset state as long as the RESET pin is held low.

If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN modeonly), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET pinactivation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU by detecting around 2V a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon aninternal delayis initiated, inorder to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence

is executed immediately following the internal delay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (presenting oscillation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performances.

Figure 14. Reset and Interrupt Processing

INT LATCH CLEARED

NMI MASK SET

RESET

( IF PRESENT )

SELECT

NMI MODE FLAGS

IS RESET STILL

PRESENT?

YES

PUT FFEH

ON ADDRESS BUS

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

LOAD PC

VA000427

24/86

ST62T53C/T60C/T63C ST62E60C

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE RESET is effective as well in Power-on phase as in power supply drop with different reference val-

ues, allowing hysteresiseffect. Referencevalue in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start’s running and sinking current on the supply.

As long as the supply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU: RESET active below the voltage reference, and running mode over the voltage reference as shown on the Figure 15, that represents a powerup, power-down sequence.

Note: When the RESET state is controlled by one of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET pin is tied to low logiclevel.

Figure 15. LVD Reset on Power-on and Power-down (Brown-out)

3.2.5 Application Notes

No external resistor is required between VDDand the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to VDDmust be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired structure).

RESET

VR02106A

time

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RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in programROM starting at address 0FFEh). A jump tothe beginning ofthe user programmust be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in NonMaskable Interrupt mode; thisprevents the initialisation routinefrom being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. Ifno pending interrupt is present at theend of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETIinstruction. If, however, a pending interrupt is present, it will be serviced.

Figure 16. Reset and Interrupt Processing

Figure 17. Reset Block Diagram

RESET

VECTOR

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION

ROUTINE

VA00181

RESET

ESD

POWER

WATCHDOG RESET

COUNTER

RESET

ST6 INTERNAL RESET

OSC

RESET

ON RESET

LVD RESET

VR02107A

AND. Wired

1) Resistive ESD protection. Value not guaranteed.

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RESETS (Cont’d) Table 5. Register Reset Status

Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control

AR TIMER Mode Control Register AR TIMER Status/Control 0 Register AR TIMER Status/Control 1 Register AR TIMER Compare Register

Miscellaneous Register SPI Registers SPI DIV Register SPI MOD Register SPI DSR Register

0DCh 0EAh 0C0h to 0C2h 0C4h to 0C6h 0CCh to 0CEh 0C8h 0D4h

0D5h 0D6h 0D7h

0DDh 0E0h to 0E2h 0E1h 0E2h 0E0h

00h 00h 00h 00h 00h 00h 00h

00h 00h 00h 00h

Undefined

EEPROM disabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled

AR TIMER stopped

SPI Output not connected to PC3 SPI disabled SPI disabled SPI disabled SPI disabled

X, Y, V, W, Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A/D Result Register AR TIMER Load Register AR TIMER Reload/Capture Register

080H TO 083H 0FFh 084h to 0BFh 0E8h 0C9h 00h to 03Fh 0D0h 0DBh 0D9h

Undefined

As written if programmed

TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A/D Control Register

0D3h 0D2h 0D8h 0D1h

FFh 7Fh FEh

40h

Max count loaded

A/D in Standby

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3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recoveryfrom software upsets.

The Watchdog circuitgenerates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. Inthe eventof a software mishap (usually caused by externally generated interference), the userprogram will no longerbehave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind.

Watchdog behaviour is governed by two options, known as “WATCHDOG ACTIVATION” (i.e. HARDWARE or SOFTWARE) and “EXTERNAL STOP MODE CONTROL” (see Table6).

In the SOFTWARE option, the Watchdog is disabled until bit Cof the DWDR registerhas been set.

When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog is permanently enabled. Sincethe oscillator will run continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown.

However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMIpin is high, the Watchdog counter is frozen and the CPU enters STOP mode.

When the MCU exits STOPmode (i.e. when aninterrupt is generated), the Watchdog resumes its activity.

Table 6. Recommended Option Choices

Functions Required Recommended Options

Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”

Stop Mode “SOFTWARE WATCHDOG”

Watchdog “HARDWARE WATCHDOG”

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DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are allset to“1”, thus selecting the longest Watchdog timer period. This time period can be set to the user’s requirements by setting theappropriate value for bits T0 to T5 in the DWDR register. The SR bit mustbe set to “1”, since itis this bit which generates the Reset signal when it changes to “0”; clearing this bit would generate an immediate Reset.

It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 toT5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physicalcounter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timerdowncounter is illustrated in Figure 18.

Only the 6 most significant bitsmay be usedto define the time period, since it is bit 6 which triggers the Reset when it changes to “0”. This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of8MHz, this is equivalent to timer periods ranging from 384µs to 24.576ms).

Figure 18. Watchdog Counter Control

WATCHDOG CONTROL REGISTER

WATCHDOG COUNTER

OSC÷12

RESET

VR02068A

÷2

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DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR)

Address: 0D8h — Read/Write Reset status:1111 1110b

Bit 0 = C:

Watchdog Control bit

If thehardware option is selected, this bit is forced high andthe user cannot change it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU).

When C is kept low the counter can be used as a 7-bit timer.

This bitis cleared to “0” on Reset. Bit 1 = SR:

Software Reset bit

This bittriggers a Reset when cleared. When C =“0” (Watchdog disabled) it is the MSB of

the 7-bit timer. This bitis set to “1” on Reset. Bits 2-7= T5-T0:

Downcounter bits

It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB.

These bits are set to “1” on Reset.

3.3.2 Application Notes

The Watchdog plays an important supporting role in the highnoise immunityof ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability.

When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTROL should be preferred, as it provides maximum security,especially during power-on.

When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP modeto beentered when the MCU is idle.

The NMI pin can be connected to an I/O line (see Figure 19)to allow its state to becontrolled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption.

When software activation is selected and the Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember thatthe bits are in reverse order).

The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure theWatchdog has not been unexpectedly activated, the following instructions should be executed within the first 27 instructions:

jrr 0, WD, #+3 ldi WD, 0FDH

T0 T1 T2 T3 T4 T5 SR C

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DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog.

In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first 27 instructions following Watchdog activation (software mode), or within the first 27 instructions executed followinga Reset (hardware activation).

It shouldbe notedthat when the GEN bit islow (interrupts disabled), the NMI interrupt is active but cannot cause a wake up fromSTOP/WAIT modes.

Figure 19. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature

Figure 20. Digital Watchdog Block Diagram

NMI

SWITCH

I/O

VR02002

RSFF

DATA BUS

VA00010

-2

-12

OSCILLATOR

RESET

WRITE

RESET

DB0

DB1.7 SETLOAD

-2

SET

CLOCK

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3.4 INTERRUPTS

The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains aJump instruction to the associated interrupt service routine. These vectors are located in Program space(see Table 7).

When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC registeris loaded with the addressof the interrupt vector (i.e. of the Jump instruction), which then causes a Jumpto the relevant interrupt service routine, thus servicing the interrupt.

Interrupt sourcesare linked to eventseither onexternal pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggeredthe interrupt.

The Non Maskable Interrupt requesthas the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority ofeach interrupt source is fixed.

Table 7. Interrupt Vector Map

3.4.1 Interrupt request

All interrupt sources but the Non Maskable Interrupt source canbe disabled by setting accordingly the GEN bitof theInterrupt Option Register (IOR). This GEN bitalso defines if an interrupt source,including the Non Maskable Interrupt source, canrestart theMCU from STOP/WAIT modes.

Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat-

ically resetby the core atthe beginning of the nonmaskable interrupt service routine.

Interrupt request from source #1 can be configured either as edge or level sensitive by setting accordingly the LES bit of the InterruptOption Register (IOR).

Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly theESB bit ofthe Interrupt Option Register (IOR).

Interrupt request from sources #3 & #4 are level sensitive.

In edge sensitive mode, alatch is set when aedge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine before being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored.

Storage of interruptrequests is not available in level sensitive mode. To be taken into account, the low level must bepresent on the interrupt pin when the MCU samples the line after instruction execution.

At the end of every instruction, the MCUtests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead.

Table 8. Interrupt Option Register Description

Interrupt Source Priority Vector Address

Interrupt source #0 1 (FFCh-FFDh) Interrupt source #1 2 (FF6h-FF7h) Interrupt source #2 3 (FF4h-FF5h) Interrupt source #3 4 (FF2h-FF3h) Interrupt source #4 5 (FF0h-FF1h)

GEN

SET Enable all interrupts CLEARED Disable allinterrupts

ESB

SET

Rising edge mode oninterrupt source #2

CLEARED

Falling edge mode on interrupt source #2

LES

SET

Level-sensitive mode on interrupt source #1

CLEARED

Falling edge mode on interrupt source #1

OTHERS NOT USED

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INTERRUPTS (Cont’d)

3.4.2 Interrupt Procedure

The interrupt procedure is very similarto a callprocedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. There are separate setsof processorflags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved.

The following list summarizes the interrupt procedure:

MCU

– The interrupt is detected. – The C and Z flags are replaced by the interrupt

flags (orby the NMI flags).

– The PC contents are stored in the first level of

the stack.

– The normalinterrupt lines are inhibited (NMI still

active). – The first internal latch is cleared. – TheassociatedinterruptvectorisloadedinthePC.

WARNING: In some circumstances, when a maskable interrupt occurs while the ST6 core is in NORMAL mode and especially during the execution of an ”ldi IOR, 00h” instruction (disabling all maskable interrupts):if the interrupt arrives during the first 3 cycles of the ”ldi” instruction (which is a 4-cycle instruction) the corewill switch to interrupt mode BUTthe flags CN andZN willNOT switch to the interruptpair CI and ZI.

User

– User selected registers are saved within the in-

terrupt service routine (normally on a software

stack). – Thesource of the interruptis found bypolling the

interrupt flags (if more than onesource is associ-

ated with the same vector). – The interrupt is serviced. – Return from interrupt (RETI)

MCU

– Automaticallythe MCU switches back to the nor-

mal flagset (or the interrupt flag set) and pops the previous PC value from the stack.

The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). Theuser should save theregisters which are usedwithin the interrupt routine in a software stack. After the RETI instruction is executed, the MCU returns tothe main routine.

Figure 21. Interrupt Processing Flow Chart

INSTRU CTION

FETCH

INSTRU CTION

EXECUT E

INSTRUCTION

WAS

THE INS TRUCTION

ARETI

CLEAR

INTERR UPT MASK

SELECT

PROGRAM FLAGS

”POP”

THE STACKED PC

CHEC K IF TH ERE IS

AN INTERRUP T REQUEST

AND INTE RRU PT MASK

SELECT

INTER NALMODE FLAG

PUSH THE

PC IN TO THE STACK

LOAD PC FROM

INTERR UPT VECTOR

(FFC/FFD)

SET

INTERRUPT MASK

YES

IS THE CORE

ALREADY I N

NORMAL MODE?

VA000014

YES

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INTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register(IOR)

The Interrupt Option Register (IOR) is used to enable/disable theindividual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations.

Address: 0C8h — Write Only Reset status:00h

Bit 7, Bits 3-0 =

Unused

Bit 6 = LES:

Level/Edge Selection bit

When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive modefor interrupt request is selected.

Bit 5 =ESB:

Edge Selection bit

The bit ESB selects the polarity of the interrupt source #2.

Bit 4= GEN:

Global Enable Interrupt

. When this bit is set to one, all interrupts are enabled.When this bit is cleared to zero all the interrupts (excluding NMI) are disabled.

When the GEN bit is low, the NMI interrupt is active but cannot cause a wakeup from STOP/WAIT modes.

This register is cleared on reset.

3.4.4 Interrupt sources

Interrupt sources available on these MCUs are summarized in the Table 9 with associated mask bit to enable/disable the interrupt request.

Table 9. Interrupt Requests and Mask Bits

- LES ESB GEN - - - -

Peripheral Register

Address Register

Mask bit Masked Interrupt Source

Interrupt

vector

GENERAL IOR C8h GEN

All Interrupts, excluding NMI

TIMER TSCR1 D4h ETI TMZ: TIMER Overflow Vector 4 A/D CONVERTER ADCR D1h EAI EOC: End of Conversion Vector 4

AR TIMER ARMC D5h

OVIE CPIE EIE

OVF: AR TIMER Overflow CPF: Successful compare EF: Active edge on ARTIMin

Vector 3

SPI SPIMOD E2h SPIE SPRUN: End of Transmission Vector 2 Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin Vector 1 Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin Vector 1 Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin Vector 2

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INTERRUPTS (Cont’d) Figure 22. Interrupt Block Diagram

Start

QCLK

CLR

MUX

IOR REG. C8H, bit 6

IOR REG. C8H, bit 5

CLR

CLK Q

Start

TIMER1

CPIE

CPF

TMZ

ETI

INT #4 (FF0,1)

INT #3 (FF2,3)

INT #2 (FF4,5)

INT #1 (FF6,7)

RESTART FROM

STOP/WAIT

AR TIMER

EIE

OVF

OVIE

VA0426K

PBE

Bits

PORT B

PORT A

PBE

SINGLE BIT ENABLE

FROM REGISTER PORT A,B,C

PORT C

SPINT bit

Start

QCLK

CLR

Bit GEN (IOR Register)

NMI (FFC,D)

NMI

ADC

EOC

EAI

SPIE bit

SPIDIV Register

SPIMOD Register

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3.5 POWER SAVING MODES

The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs.

3.5.1 WAIT Mode

The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a “software frozen” state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active.

WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, whilenot losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering theWAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal.

If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the Watchdog), theMCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU’s behaviour depends on thestate

of the processor coreprior tothe WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary.

3.5.2 STOP Mode

If the Watchdog is disabled,STOP modeis available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontrollercan be considered as being “frozen”, no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exitthe STOP state.

If the STOP state is exited dueto a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generated.

This case will be described in the following paragraphs. The processor core generates a delay after occurrence ofthe interrupt request, in order to wait for complete stabilisation ofthe oscillator, before executing the first instruction.

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POWER SAVING MODE (Cont’d)

3.5.3 Exit from WAIT and STOP Modes

The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that the restartsequence depends on theoriginal state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type.

Interrupts do not affect the oscillator selection.

3.5.3.1 Normal Mode

If the MCU was in themain routinewhen theWAIT or STOP instruction was executed, exit from Stop or Waitmode will occuras soon asan interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing noother interrupts are pending.

3.5.3.2 Non Maskable Interrupt Mode

If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, theMCU exitsfrom the Stop orWait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generated.

3.5.3.3 Normal Interrupt Mode

If theMCU wasin interrupt modebefore the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered:

– If the interruptis a normal one, the interrupt rou-

tine in which the WAIT or STOP mode was entered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority.

– Inthe event of a non-maskable interrupt,the

non-maskable interruptservice routine is processed first,then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction.The MCU remains in normalinterrupt mode.

Notes:

To achieve the lowest power consumption during RUN or WAITmodes, the user programmust take care of:

– configuring unusedI/Osas inputs withoutpull-up

(these should be externally tied to well defined logic levels);

– placing all peripherals in their power down

modes before entering STOP mode;

When the hardware activated Watchdog is selected, or whenthe software Watchdog is enabled,the STOP instruction is disabled and a WAIT instruction will beexecuted in its place.

If all interrupt sources are disabled (GEN low),the MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-upsignal.

The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.

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4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be individually programmed as any ofthe following input or output configurations:

– Input withoutpull-up or interrupt – Input withpull-up and interrupt – Input withpull-up, but without interrupt – Analog input – Push-pull output – Open drain output The lines are organised as bytewise Ports. Each port is associated with 3 registers in Data

space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A Data, Direction and Option registers are associated with the PA0 line of Port A).

The DATA registers (DRx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be readto get the effective logic levels of the pins, but they can

be also written by user software, in conjunction with the related option registers, to select the different input mode options.

Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration.

The Data Direction registers (DDRx) allow the data direction (input or output) of each pin to be set.

The Option registers (ORx) are used to select the different port options available both in input and in output mode.

All I/O registers can be read or written to just as any other RAMlocation in Data space, so no extra RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/Oregisters are cleared andthe input mode withpull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.

Figure 23. I/O Port Block Diagram

RESET

CONTROLS

OUT

SHIFT

DATA

DIRECTION

OPTION

INPUT/OUTPUT

TO INTERRUPT

TO ADC

VA00413

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I/O PORTS (Cont’d)

4.1.1 Operating Modes

Each pinmay be individually programmed asinput or output with various configurations.

This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option registers (OR). Table 10 illustrates the various port configurations which can be selected byuser software.

4.1.1.1 Input Options

Pull-up, High Impedance Option. All input lines can be individually programmed with or withoutan internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state.

4.1.1.2 Interrupt Options

All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software as described in the Interrupt Chapter for each port.

4.1.1.3 Analog Input Options

Some pins can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter.

ONLY ONE

pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.

Table 10. I/O Port Option Selection

Note: X= Don’t care

DDR OR DR Mode Option

0 0 0 Input With pull-up, no interrupt 0 0 1 Input No pull-up, nointerrupt 0 1 0 Input With pull-up and with interrupt 0 1 1 Input Analog input (when available) 1 0 X Output Open-drain output (20mA sink when available) 1 1 X Output Push-pull output (20mA sink when available)

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I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence

Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure

24. All other transitions are potentially risky and should be avoided when changing the I/O operating mode, as itis mostlikely that undesirable sideeffects will be experienced, such asspurious interrupt generation or two pins shorted together by the analog multiplexer.

Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since theseinstructions make animplicit read and write back of the entire register. In port input mode,however, the data registerreads from the inputpins directly, and not fromthe data register latches. Sincedata registerinformation ininput mode isused toset thecharacteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, itis better to limit the use of single bit instructions on data registers to when the whole (8-bit)port is in output mode. In the case ofinputs orof mixed inputs and

outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be writtento the port data register:

SET bit, datacopy LD a, datacopy LD DRA, a

Warning: Care must also be taken to not use instructions that act on a whole port register (INC, DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction).

The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels.

The user must takecare not to switch outputswith heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion.

Figure 24. Diagram showingSafe I/O State Transitions

Note *. xxx = DDR, OR, DR Bits respectively

Interrupt pull-up

Output Open Drain

Output Push-pull

Input pull-up (Reset state)

Input

Analog

Output

Open Drain

Output

Push-pull

Input

010*

000

100

110

011

001

101

111

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I/O PORTS (Cont’d) Table 11. I/O Port Option Selections

Note 1. Provided the correct configuration has been selected.

MODE AVAILABLE ON

(1)

SCHEMATIC

Input

PA0-PA3 PB0-PB3, PB6-PB7 PC2-PC4

Input

with pull up

PA0-PA3 PB0-PB3, PB6-PB7 PC2-PC4

Input

with pull up

with interrupt

PA0-PA3 PB0-PB3, PB6-PB7 PC2-PC4

Analog Input

PA0-PA3 PC2-PC4

Open drain output

5mA

Open drain output

30mA

PA0-PA3 PC2-PC4

PB0-PB3, PB6-PB7

Push-pull output

5mA

Push-pull output

30mA

PA0-PA3 PC2-PC4

PB0-PB3, PB6-PB7

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

Data out

ADC

Data out

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I/O PORTS (Cont’d)

4.1.3 AR Timer Alternate function Option

When bitPWMOE of register ARMC islow, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high, ARTIMout/PB7isthe PWMoutput, independently of the port registers configuration.

ARTIMin/PB6 is connected to the AR Timer input. It is configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 asAR Timer input, it mustbe configuredas inputthrough DDRB.

4.1.4 SPI Alternate function Option

PC2/PC4 are used as standard I/O as long as bit SPCLK of the SPI Mode Register is kept low. When PC2/Sin isconfigured as input,it isautomatically connected to the SPI shift register input, independent of the state at SPCLK.

PC3/SOUT is configured as SPI push-pull output by setting bit 0 of the Miscellaneous register (address DDh), regardless of the state of Port C registers. PC4/SCK is configured as push-pull output clock (master mode) by programming it as pushpull output through DDRC register and by setting bit SPCLK of the SPI Mode Register.

PC4/SCK isconfigured asinputclock (slave mode) by programming it as input through DDRC register and by clearing bit SPCLKof theSPI Mode Register. With this configuration, PC4 cansimultaneously be used as an input.

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I/O PORTS (Cont’d) Figure 25. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer

MUX

PP/OD

OUT

CLOCK IN

SPI

MUX

OUT

TIMER 1

MUX

AR TIMER

ARTIMout

ARTIMin

PWMOE

PP/OD

PC3/Sout

PC2/Sin

PC4/SCK

PC1/TIM1

ARTIMin

ARTIMout

VR0C1661

MISC.

CLOCK OUT

SPCLK MOD REGISTER

MUX

TOUT

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4.2 TIMER

The MCU features an on-chip Timer peripheral, consisting ofan 8-bit counter witha 7-bit programmable prescaler,giving a maximum count of 215.

Figure 26 shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counterregister, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bitprescaler canbe read in the PSC register at address 0D2h. The control logic device is managed in the TSCR register asdescribed in thefollowing paragraphs.

The 8-bit counter is decrement by the output (rising edge) coming from the7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero)bit in the TSCR is set. If the ETI (Enable TimerInterrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used toexit the MCU from WAIT mode.

The prescaler input is the internal frequency (f

INT

) divided by 12. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR (see Figure 12), the clock input of the timer/counter register is multiplexed to different sources. For division factor 1, theclock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler registeris connected to the clock input of TCR. This bit changesits state at half the frequency of the prescaler input clock.For factor4, bit 1of the PSC is connected to the clock input of TCR, and so forth. The prescaler initializebit, PSI, in the TSCR register must be set to allow the prescaler (and hence the counter) to start. If it is cleared, all the prescaler bits are set and the counter is inhibited from counting. The prescaler can be loaded with any value between0 and 7Fh,if bitPSI is set. The prescaler tap is selected by means of the PS2/PS1/PS0 bits in the control register.

Figure 27 illustrates the Timer’s working principle.

Figure 26. Timer Block Diagram

DATA BUS

8-BIT

COUNTER

STATUS/CONTROL

INTERRUPT

LINE

VR02070A

6 5 4

3 2 1 0

SELECT

1OF7

b7 b6 b5 b4 b3 b2 b1 b0

TMZ ETI D5 D4 PSI PS2 PS1 PS0

INT

PSC

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TIMER (Cont’d)

4.2.1 Timer Operation

The Timer prescaler is clocked by the prescaler clock input(f

INT

÷ 12).

The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high.

4.2.2 Timer Interrupt

When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request associated with Interrupt Vector #3 is generated. When the counter decrements to

zero, the TMZ bit in the TSCR register is set to one.

4.2.3 Application Notes

TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared. This means that the Timer is stopped (PSI=“0”) and the timer interrupt is disabled.

Figure 27. Timer Working Principle

BIT0 BIT1 BIT2 BIT3 BIT6BIT5BIT4

CLOCK

7-BIT PRESCALER

8-1 MULTIPLEXER

8-BIT COUNTER

BIT0 BIT1

BIT2

BIT3 BIT4 BIT5

BIT6

BIT7

10234

PS0 PS1 PS2

VA00186

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TIMER (Cont’d)

A write to the TCR register will predominate over the 8-bit counterdecrement to 00h function, i.e.if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time.

4.2.4 Timer Registers Timer Status Control Register (TSCR)

Address: 0D4h — Read/Write

Bit 7 = TMZ:

Timer Zero bit

A low-to-high transition indicates that the timer count register has decrement to zero. This bit must becleared by user software before starting a new count.

Bit 6 = ETI:

Enable Timer Interrup

When set, enables the timer interrupt request (vector #3). If ETI=0 the timer interrupt isdisabled. If ETI=1 and TMZ=1 an interrupt request is generated.

Bit 5 = D5:

Reserved

Must be set to “1”. Bit 4 = D4 Do not care. Bit 3 = PSI:

Prescaler Initialize Bit

Used to initialize the prescalerand inhibitits counting. When PSI=“0” the prescaler is set to 7Fh and the counteris inhibited.When PSI=“1”the prescaler is enabled to count downwards. As long as

PSI=“0” both counter and prescaler are not running.

Bit 2, 1, 0 = PS2, PS1, PS0:

Prescaler Mux. Se-

lect.

These bits select the division ratio of the pres-

caler register.

Table 12. Prescaler Division Factors

Timer Counter Register (TCR)

Address: 0D3h — Read/Write

Bit 7-0 = D7-D0:

Counter Bits.

Prescaler Register PSC

Address: 0D2h — Read/Write

Bit 7 =D7: Always read as ”0”. Bit 6-0 = D6-D0: PrescalerBits.

TMZ ETI D5 D4 PSI PS2 PS1 PS0

PS2 PS1 PS0 Divided by

0001 0012 0104 0118 10016 10132 11064 1 1 1 128

D7 D6 D5 D4 D3 D2 D1 D0

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4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip peripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f

INT,fINT/3

or an external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ARSC1, an output pin, ARTIMout, and an input pin, ARTIMin, allow the Auto-Reload Timer to be used in4 modes:

– Auto-reload (PWMgeneration), – Output compareand reload on external event

(PLL),

– Inputcapture and output compare fortime meas-

urement.

– Input captureand output compare for period

measurement.

The AR Timer can be usedto wakethe MCU from WAIT mode either with an internal or with an external clock. It also can be used to wake the MCU from STOP mode, if used with an external clock signal connected to the ARTIMin pin. A Load register allows the program to read and write the counter onthe fly.

4.3.1 AR Timer Description

The AR COUNTER is an 8-bit up-counter incremented ontheinput clock’s rising edge. The counter is loaded from the ReLoad/Capture Register, ARRC, for auto-reload or capture operations, as well as for initialization. Direct access to the AR counter is not possible; however, by reading or writing the ARLR load register, it is possible to read or write the counter’s contents on thefly.

The AR Timer’s input clock can beeither the internal clock (from the Oscillator Divider), the internal clock divided by 3, or the clock signal connected to the ARTIMin pin. Selection between these clock sources is effected by suitably programming bits CC0-CC1 of theARSC1 register.The output of the AR Multiplexer feeds the 7-bit programmable AR Prescaler, ARPSC, which selects one of the 8 available taps of the prescaler, as defined by PSC0-PSC2 in the AR Mode Control Register. Thus the division factor of the prescalercan be set to 2n (where n = 0, 1,..7).

The clock input tothe ARcounter is enabled bythe TEN (Timer Enable) bit in the ARMC register. When TEN isreset, the AR counter is stopped and

the prescaler and counter contents are frozen. When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset.

The AR counter may also be initialized by writing to the ARLR load register, which also causes an immediate copy of the value tobe placed in the AR counter, regardless of whether the counter is running or not. Initialization of the counter, by either method, will also clearthe ARPSC register, whereupon counting will start from a known value.

4.3.2 Timer Operating Modes

Four different operating modes are available for the AR Timer:

Auto-reload Mode with PWM Generation. This mode allows a Pulse Width Modulated signal to be generated on the ARTIMout pin with minimum Core processing overhead.

The free running 8-bit counter is fed by the prescaler’s output, and is incremented on every rising edge of the clock signal.

When a counter overflow occurs, the counter is automatically reloadedwith thecontents ofthe Reload/Capture Register, ARCC, and ARTIMout is set. When the counter reaches the value contained in the compare register (ARCP), ARTIMout is reset.

On overflow, the OVF flag of the ARSC0 registeris set and an overflow interrupt request is generated if the overflow interrupt enable bit, OVIE, in the Mode Control Register (ARMC), is set. The OVF flag must be reset by the user software.

When the counterreaches thecompare value, the CPF flag of the ARSC0 register is set and a compare interrupt request isgenerated, if the Compare Interrupt enable bit, CPIE, in the Mode Control Register (ARMC), is set. Theinterrupt service routine may then adjust thePWM period by loading a new value intoARCP. TheCPF flag must be reset by user software.

The PWM signal is generated on the ARTIMout pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Reload/Capture register, ARRC. The duty cycle of the PWM signal is controlledby theCompare Register, ARCP.

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AUTO-RELOAD TIMER (Cont’d) Figure 28. AR Timer Block Diagram

DATA BUS

COMPARE

RELOAD/CAPTURE

DATA BUS

AR TIMER

VR01660A

TCLD

OVIE

PWMOE

OVF

LOAD

ARTIMout

SYNCHRO

ARTIMin

SL0-SL1

INT

PB6/

LOAD

U X

INT

AR PRESCALER

7-Bit

CC0-CC1

AR COUNTER

8-Bit

AR COMPARE

OVF

EIE

INTERRUPT

CPF

CPIE

CPF

DRB7

DDRB7

PB7/

PS0-PS2

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AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTIMout, the contents of the ARCP register must be greater thanthe contents of the ARRC register.

The maximum available resolution for the ARTIMout duty cycle is:

Resolution = 1/[255-(ARRC)]

Where ARRC is the content of the Reload/Capture register. The compare value loaded in the Compare Register, ARCP, must be in the range from (ARRC) to 255.

The ARTC counter is initialized by writing to the ARRC register and by then setting theTCLD (Timer Load) andthe TEN (Timer Clock Enable) bits in the Mode Control register, ARMC.

Enabling and selection of the clock source is controlled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1. Theprescaler division ratio is selected by the PS0, PS1 and PS2 bits in the ARSC1 register.

In Auto-reload Mode, any of the three available clock sources can be selected: Internal Clock, Internal Clock divided by 3 or the clock signal present on the ARTIMin pin.

Figure 29. Auto-reload Timer PWM Function

COUNTER

COMPARE VALUE

RELOAD

PWM OUTPUT

255

000

VR001852

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AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation.Inthis

mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter isincremented onevery clock risingedge.

An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Control bits SL0, SL1 in the ARSC1 register. At the same time, the External Flag, EF, in the ARSC0 register is set and an external interrupt request is generated if the External Interrupt Enable bit, EIE, in the ARMC register, is set. The EF flag must be reset by user software.

Each ARTC overflow sets ARTIMout, while a match between the counter and ARCP (Compare Register) resets ARTIMout and sets the compare flag, CPF.A compareinterrupt request isgenerated if the related compare interrupt enable bit, CPIE, isset. A PWM signalis generated on ARTIMout. The CPF flag must be reset by user software.

The frequency of the generated signal is determined by the prescaler setting. The duty cycle is determined by the ARCP register.

Initialization and reading of thecounter are identical tothe auto-reload mode (see previousdescription).

Enabling andselection of clock sources is controlled by the CC0 and CC1 bits in the ARStatus Control Register, ARSC1.

The prescaler division ratio is selected by programming the PS0, PS1 and PS2 bits in the ARSC1 Register.

In Capture mode, the allowed clock sources are the internalclock and the internal clock divided by 3; the external ARTIMin input pin should not be used asa clock source.

Capture Mode with Reset of counter and prescaler, and PWM Generation. This mode is identi-

cal to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period measurement on the ARTIMin pin).

Load on External Input. Thecounter operates as a free running 8-bit counter fed by the prescaler.

the count is incremented on every clock rising edge.

Each counter overflow sets the ARTIMout pin. A match between the counter and ARCP (Compare Register) resets the ARTIMout pin and sets the compare flag, CPF. A compareinterrupt request is generated if the related compare interrupt enable bit, CPIE, is set. A PWM signal is generated on ARTIMout. The CPF flag must be reset by user software.

Initialization of the counter is as described in the previous paragraph. In addition, ifthe externalARTIMin input is enabled,an active edge on the input pin will copy the contents ofthe ARRC register into the counter, whether the counter is runningor not.

Notes: The allowed AR Timer clock sources are the fol-

lowing:

The clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. For instance, the multiplexer setting should not be modified while the counter is counting.

Loading of the counter by any means (by auto-reload, through ARLR, ARRC or by the Core) resets the prescaler at the same time.

Care should be taken when boththe Capture interrupt and the Overflow interrupt are used. Capture and overflow are asynchronous. If the capture occurs when the Overflow Interrupt Flag, OVF, is high (between counteroverflow and the flagbeing reset by software, in the interruptroutine), the External Interrupt Flag, EF, may be cleared simultaneusly without the interrupt being taken into account.

The solution consists in resetting the OVF flag by writing 06h in the ARSC0 register. Thevalue of EF is not affectedby this operation. If aninterrupt has occured, it will be processed when the MCU exits from the interrupt routine (the second interrupt is latched).

AR Timer Mode Clock Sources

Auto-reload mode f

INT,fINT/3

, ARTIMin

Capture mode f

INT,fINT/3

Capture/Reset mode f

INT,fINT/3

External Load mode f

INT,fINT/3

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AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers AR Mode Control Register (ARMC)

Address: D5h — Read/Write Reset status:00h

The AR Mode Control Register ARMC is used to program the different operating modes of the AR Timer, to enable the clock and to initialize the counter. It can be read and written to by the Core and it is cleared on system reset (the AR Timer is disabled).

Bit 7 = TLCD:

Timer Load Bit.

This bit, when set, will cause the contents of ARRC register to be loaded into the counter and the contents of the prescaler register,ARPSC, are cleared in order to initialize the timer before starting to count. This bit is write-only and any attempt to read it will yield a logical zero.

Bit 6 = TEN

: Timer Clock Enable.

This bit, when set, allows the timer to count. When cleared, it will stop the timer and freeze ARPSC and ARTSC.

Bit 5 = PWMOE:

PWM Output Enable.

This bit, when set, enables the PWM output on the ARTIMout pin. When reset, thePWM output is disabled.

Bit 4 = EIE:

External Interrupt Enable.

This bit, when set, enables the external interrupt request. When reset, the external interrupt request is masked. If EIE is set and the related flag, EF, in the ARSC0 register is also set, an interrupt request is generated.

Bit 3 = CPIE:

Compare Interrupt Enable.

This bit, when set, enables the compare interrupt request. If CPIE is reset, the compare interrupt request is masked. If CPIE is set and the related flag, CPF,in the ARSC0 register is also set, an interrupt request is generated.

Bit 2 = OVIE:

Overflow Interrupt

. This bit, when set, enables the overflow interrupt request. If OVIE is reset, the compare interrupt request is masked. If OVIE is set and the related flag, OVF in the

ARSC0 register is also set, an interrupt request is generated.

Bit 1-0= ARMC1-ARMC0:

Mode Control Bits 1-0

. These are the operating mode control bits. The following bit combinations will select the various operating modes:

AR Timer Status/Control Registers ARSC0 & ARSC1. Theseregisters contain the AR Timer sta-

tus information bits and also allow the programming of clock sources, active edge and prescaler multiplexer setting.

ARSC0 register bits 0,1 and 2 containthe interrupt flags of theAR Timer. Thesebits are read normally. Each one may be reset by software. Writing a one does not affect thebit value.

AR Status Control Register 0 (ARSC0)

Address: D6h — Read/Clear

Bits 7-3 = D7-D3:

Unused

Bit 2= EF:

External Interrupt Flag.

This bit is set by any active edge on the external ARTIMin input pin. The flag is cleared bywriting a zero to the EF bit.

Bit 1 = CPF:

Compare Interrupt Flag.

This bit is set if the contents of the counter and the ARCP register areequal. The flag is cleared by writing a zero to the CPF bit.

Bit 0 = OVF:

Overflow InterruptFlag.

This bitis set by a transition of the counter from FFh to 00h (overflow). The flag is cleared by writing a zero to the OVF bit.

TCLD TEN PWMOE EIE CP IE OV IE AR MC1 ARMC0

ARMC1 ARMC0 Operating Mode

0 0 Auto-reload Mode 0 1 Capture Mode

Capture Mode with Reset of ARTC and ARPSC

Load on External Edge Mode

D7 D6 D5 D4 D3 EF CPF OVF

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AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1)

Address: D7h — Read/Write

Bist 7-5 = PS2-PS0:

Prescaler Division Selection

Bits 2-0.

These bits determine the Prescaler division ratio. The prescaler itself is not affected by these bits.Theprescaler division ratioislistedinthe following table:

Table 13. Prescaler Division Ratio Selection

Bit 4 = D4:

Reserved

. Mustbe kept reset.

Bit 3-2= SL1-SL0:

Timer InputEdgeControl Bits 1-

These bits control theedge function of the Timer inputpinforexternalsynchronization. IfbitSL0isreset, edgedetectionis disabled;ifset edge detection is enabled.If bit SL1is reset,theAR Timerinput pin is rising edge sensitive; if set,it is fallingedge sensitive.

Bit 1-0 = CC1-CC0:

Clock Source Select Bit 1-0.

These bits select theclock source for theAR Timer through the AR Multiplexer. The programming of the clocksources isexplainedin thefollowing Table 14:

Table 14. Clock Source Selection.

AR Load Register ARLR. The ARLR loadregister

is used to read or write the ARTC counter register “on the fly” (while it is counting). The ARLR register is not affected by system reset.

AR Load Register (ARLR)

Address: DBh — Read/Write

Bit 7-0 = D7-D0:

Load Register Data Bits.

These

are the load register data bits.

AR Reload/Capture Register. The ARRC reload/ capture register is used to hold the auto-reload value whichis automatically loaded into the counter when overflow occurs.

AR Reload/Capture (ARRC)

Address: D9h — Read/Write

Bit 7-0 = D7-D0:

Reload/Capture Data Bits

. These

are the Reload/Capture register data bits.

AR Compare Register. The CP compare register is used to holdthe compare value for the compare function.

AR Compare Register (ARCP)

Address: DAh — Read/Write

Bit 7-0 = D7-D0:

Compare Data Bits

. These are

the Compare register data bits.

PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0

PS2 PS1 PS0 ARPSC Division Ratio

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 2 4

8 16 32 64

128

SL1 SL0 Edge Detection

X 0 Disabled 0 1 Rising Edge 1 1 Falling Edge

CC1 CC0 Clock Source

00F

int

01F

int

Divided by 3 1 0 ARTIMin Input Clock 1 1 Reserved

D7 D6 D5 D4 D3 D2 D1 D0

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4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to digital converter with analoginputs asalternate I/O functions (the number of which is device dependent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock frequency of 8MHz).

The ADC converts the input voltage by a process of successive approximations, using a clock frequency derived from the oscillator with a division factor oftwelve. With an oscillator clock frequency less than 1.2MHz, conversion accuracy is decreased.

Selection of the input pin is done by configuring the related I/O line as an analog input via the Option and Data registers (refer to I/O ports description for additional information). Only one I/O line must be configured as an analog input atany time. The user must avoid any situation in which more than one I/O pin is selected as an analog input simultaneously, toavoid device malfunction.

The ADC uses two registers in the data space:the ADC data conversion register, ADR, which stores the conversion result, and the ADC control register, ADCR,used to program the ADC functions.

A conversionis started by writinga “1” to theStart bit (STA) in the ADC control register. This automatically clears (resets to “0”) the End Of Conversion Bit (EOC). When a conversion is complete, the EOC bit is automatically set to “1”, in order to flag that conversion is complete and that the data in the ADC data conversion registeris valid. Each conversion has to be separately initiated bywriting to the STA bit.

The STA bit is continuously scanned so that, ifthe user sets it to “1” while a previous conversion is in progress, a new conversion is started before completing the previous one. The start bit (STA) is a write onlybit, anyattempt toread it will show a logical “0”.

The A/D converter features a maskable interrupt associated with the end of conversion. This interrupt is associated with interrupt vector #4 and occurs when the EOC bit is set (i.e. when a conversion is completed). The interrupt is masked using the EAI(interrupt mask) bit in the control register.

The power consumption of the device can be reduced by turning off the ADC peripheral. This is done by setting the PDS bit in theADC control register to “0”. If PDS=“1”, the A/D is powered andenabled for conversion. This bit must be set at least one instruction before the beginningof the conver-

sion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automatically disabled in WAIT mode.

During Reset, any conversion in progress is stopped, thecontrol register is reset to 40h and the ADC interrupt is masked (EAI=0).

Figure 30. ADC Block Diagram

4.4.1 Application Notes

The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed ±1/2 LSB for the optimum conversion accuracy. A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion.

When selected asan analog channel, the input pin is internally connected to a capacitor Cadof typically 12pF. For maximum accuracy, this capacitor must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 µs) after the channel has been selected. In worst case conditions, the impedance, ASI, of the analog voltage sourceis calculatedusing the following formula:

6.5µs=9xCadx ASI

(capacitor charged to over 99.9%), i.e. 30 kΩ including a 50% guardband. ASI can behigher if C

has been charged for a longer period by adding instructions before the start of conversion (adding more than 26 CPU cycles is pointless).

CONTROL REGISTER

CONVERTER

VA00418

RESULT REGISTER

RESET

INTERRUPT CLOCK

AV AV

Ain

CORE

CONTROL SIGNALS

CORE

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A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the microprocessor, the user should not switch heavilyloaded output signals during conversion, if high precision is required.Such switchingwill affectthe supply voltages used as analog references.

The accuracy of the conversion depends on the quality of the power supplies (VDDand VSS). The user musttake special care to ensure a well regulated reference voltage is present on the VDDand VSSpins (power supply voltage variations mustbe less than5V/ms). This implies, in particular, that a suitable decoupling capacitor is used at the V

pin. The converter resolution is given by::

The Input voltage (Ain) which is to be converted must be constant for 1µs before conversion and remain constant during conversion.

Conversion resolution canbe improved ifthe power supply voltage (VDD) to the microcontroller is lowered.

In orderto optimise conversion resolution, the user can configure the microcontroller in WAIT mode, because this mode minimises noise disturbances and power supply variations due to output switching. Nevertheless, the WAIT instruction should be executed as soon as possible after the beginning of the conversion, because execution of theWAIT instruction may cause a small variation of the V

voltage. The negative effectof this variation is minimized at the beginning ofthe conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined.

The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. Indeed, only the ADC peripheral and the oscillator are thenstill working. The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion. It should be noted that waking up the microcontroller could also be done using the Timer interrupt, but in this case the Timer will be working and the resulting noise could affect conversion accuracy.

One extra feature is available in the ADC to get a better accuracy. Infact, eachADC conversion has to be followed by a WAIT instruction to minimize

the noise during the conversion. But the first conversion step is performed before the execution of the WAIT when most of clocks signals are still enabled . The key is to synchronize the ADC start with the effective execution of the WAIT. This is achieved by setting ADC SYNC option. This way, ADC conversion starts in effective WAIT for maximum accuracy.

Note: With this extra option, it ismandatory to execute WAIT instruction just after ADCstart instruction. Insertion of any extra instruction may cause spurious interrupt request at ADC interrupt vector.

A/D Converter Control Register (ADCR)

Address: 0D1h — Read/Write

Bit 7 = EAI:

Enable A/D Interrupt.

If this bit is setto “1” the A/D interrupt is enabled, when EAI=0 the interrupt is disabled.

Bit 6 = EOC:

End of conversion. Read Only

. This read only bit indicates when a conversion has been completed. This bit is automatically reset to “0” when the STA bit is written. If the user is using the interrupt optionthen this bit can beused as an interrupt pending bit. Data in the data conversion register are valid only whenthis bit is set to “1”.

Bit 5 =STA

: Startof Conversion. Write Only

. Writing a “1” to this bitwill start a conversion onthe selected channel and automatically reset to “0” the EOC bit. If the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. This bit is write only, any attempt to read it will show a logical zero.

Bit 4 = PDS

: Power Down Selection.

This bit activates the A/D converter if setto “1”.Writing a “0” to this bit will put the ADC in power down mode (idle mode).

Bit 3-0 = D3-D0. Not used

A/D Converter Data Register (ADR)

Address: 0D0h — Read only

Bit 7-0 = D7-D0

: 8Bit A/D Conversion Result.

DDVSS

–

256

----------------------------

EAI EOC STA PDS D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

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4.5 SERIAL PERIPHERAL INTERFACE(SPI)

The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industrystandard SPI specifications. The SPI interface may also implement asynchronous data transfer, in which case processor overhead is limited to data transfer from or tothe shift register on an interrupt driven basis.

The SPI may be controlled by simple user software to perform serial data exchange with lowcost external memory, or with serially controlled peripherals to drive displays, motorsor relays.

The SPI’s shift register is simultaneously fed by the Sin pin and feeds the Sout pin, thus transmission and reception are essentially the same process. Suitable setting of the number of bits in the data frame can allow filtering of unwanted leading data bits in the incoming data stream.

The SPI comprises an 8-bit Data/Shift Register, DSR, a Divide register, DIV, a Mode Control Register MOD, and a Miscellaneous register, MISCR.

The SPI may be operated either in Mastermode or in Slave mode.

Master mode is defined by the synchronous serial clock being supplied by the MCU, by suitably programming the clock divider (DIV register). Slave

mode is defined by the serial clock being supplied externally on the SCK pin by the external Master device.

For maximum versatility the SPI may be programmed to sample data either onthe rising or on the falling edge of SCK,with or without phase shift (clock Polarity and Phase selection).

The Sin, Sout and SCK signals are connected as alternate I/O pin functions.

For serial input operation, Sin must be configured as an input. For serial output operation,Sout is selected as an output by programming Bit 0 of the Miscellaneous Register: clearing this bit will set the pin as a standard I/O line, while setting the bit will select the Sout function.

An interrupt request may be associated with the end of a transmission or reception cycle; this is defined by programming the number of bits in the data frame and by enabling the interrupt. This request is associated with interrupt vector #2, and can be masked by programming the SPIE bit of the MOD register. Since the SPI interrupt is “ORed” with the port interrupt source, an interrupt flag bit isavailable inthe DIV register allowing discrimination of the interrupt request.

Figure 31. SPI Block Diagram

SPI

SCK

FILTER

Sin

Sout

CPU CYCLE CLOCK

CLOCK

DATA BUS

VR001693

SHIFT

FILTER

DIVIDER

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.5.1 SPI Registers SPI Mode Control Register (MOD)

Address: E2h — Read/Write Reset status:00h

The MOD register defines and controls the transmission modesand characteristics.

This register is read/write and all bits are cleared at reset. Setting SPSTRT = 1 and SPIN = 1 is not allowed andmust be avoided.

Bit 7 = SPRUN:

SPI Run

. This bit is the SPI activity flag. Thiscan be used in either transmit orreceive modes; it is automatically cleared bythe SPI at the end of a transmission or reception and generates an interrupt request (providing that theSPIE Interrupt Enable bit is set). TheCore can stop transmission or reception at any time by resetting the SPRUN bit; this will also generate an interrupt request (providing that the SPIE Interrupt enable bit is set). The SPRUN bit canbe usedas astart condition parameter, in conjunction with the SPSTRT bit, when an external signal is present on the Sin pin. Note that a rising edge is then necessary to initiate reception; this may require external data inversion. This bit can be used to poll the end of reception or transmission.

Bit 6 = SPIE:

SPI Interrupt Enable

. This bit is the SPI Interrupt Enable bit. If thisbit is set the SPI interrupt (vector #2) is enabled, when SPIE is reset, the interruptis disabled.

Bit 5 = CPHA:

Clock Phase Selection

. This bit selects the clock phase of the clock signal. If this bit is cleared to zero the normal state is selected; in this case Bit7 of the data frameis present on Sout pin as soon as the SPI Shift Register is loaded. If this bit is setto onethe shifted state’ is selected; in this case Bit7 of data frame is present onSout pin on the first fallingedge ofShift Registerclock. The polarity relation and the division ratio between Shift Register and SPI base clock are also programmable; refer to DIV register and Timing Diagrams for more information.

Bit 4= SPCLK:

Base Clock Selection

This bit selects the SPI base clock source. It is either the core cycle clock (f

INT

/13) (Master mode) or the signal provided at SCK pin by an external device (slave mode). If SPCLK islow andthe SCK

pin is configured as input, the slave mode is selected. If SPCLK ishigh, the SCK pin is automaticcally configured as push pull output and the master mode is selected. In this case, the phase and polarity of the clock are controlled by CPOL and CPHA.

Note: When the master mode is enabled, it is mandatory to configure PC4 in input mode through the i/o port registers.

Bit 3 =SPIN:

Input Selection

This bit enables the transfer of the data input to the Shift Register in receive mode. If this bit is cleared the Shift Register input is 0. If this bit is set, the Shift Register input corresponds to the input signal present on the Sin pin.

Bit 2 =SPSTRT:

Start Selection

This bit selects the transmission or reception start mode. If SPSTRT is cleared,the internal start condition occurs as soon as the SPRUN bit is set. If SPSTRT is set, the internal start signal is the logic “AND” between the SPRUN bit and the external signal present on the Sinpin; in this case transmission will start after the latest of both signals providing that the first signal isstill present (note that this implies a rising edge). After the transmission orrecetion has been started, itwill continue even if the Sin signal is reset.

Bit 1 =EFILT:

Enable Filters

This bit enables/disables the input noise filters on the Sin and SCK inputs.If it is cleared to zero the filters are enabled, if set to one the filters are disabled. These noise filterswill eliminateany pulse on Sin and SCK with a pulse width smaller than one to two Core clock periods (depending on the occurrence of the signal edge with respect to the Core clock edge). For example, if the ST6260B/ 65B runs with an 8MHz crystal, Sin and SCK will be delayed by 125 to 250ns.

Bit 0 =CPOL:

Clock Polarity

This bitcontrols the relationship between the data on the Sin and Sout pins and SCK. The CPOL bit selects the clock edge which capturesdata and allows it to change state. It has the greatest impact on the first bit transmitted (the MSB) as it does (or does not) allow a clock transition before the first data capture edge.

Refer to the timingdiagrams at the end of this section for additional details. These showthe relationship betweenCPOL, CPHA and SCK, andindicate the active clock edges and strobe times.

SPR U N SPIE CPHA SPCL K SPIN SPSTR T EFILT CPO L

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d) SPI DIV Register (DIV)

Address: E1h — Read/Write Reset status:00h

The SPIDIV register defines the transmission rate and frameformat and contains the interrupt flag.

Bits CD0-CD2, DIV3-DIV6 are read/write while SPINT can be read and cleared only. Write access is not allowed ifSPRUN intheMOD register is set.

Bit 7 =SPINT:

Interrupt Flag.

If SPIEbit=1, SPINT is automaticallyset to one by the SPIat the end of a transmission or reception and an interrupt request canbe generated depending on the stateof the interrupt mask bit in the MOD control register. This bit is write and read and must be cleared by user software at the end of the interrupt service routine.

Bit 6-3 = DIV6-DIV3:

Burst Mode Bit Clock Period

Selection.

Define the number of shift register bits that are transmitted or received in a frame. The available selections are listed in Table 16. The normal maximum setting is 8 bits, since the shift register is 8bits wide. Note that bysetting agreater number of bits, in conjunction with the SPIN bit in the MODregister, unwanted data bits may befiltered fromthe data stream.

Bit 2-0 = CD2-CD0:

Base/Bit Clock Rate Selec-

tion

. Define the division ratio between the core

clock (f

INT

divided by 13)and the clock supplied to

the Shift Register in Master mode.

Table 15. Base/Bit Clock Ratio Selection

Note: For example, when an 8MHz CPU clock is

used, asynchronous operation at 9600 Baud is possible (8MHz/13/64). Other Baud rates are available by proportionally selecting division factors depending on CPU clock frequency.

Data setup time on Sin is typically250ns min, while data holdtime is typically 50ns min.

SPI Data/Shift Register (SPIDSR)

Address: E0h — Read/Write Reset status: XXh

SPIDSR is read/write, however write access is not allowed if the SPRUN bit of Mode Control register is set to one.

Data is sampled into SPDSR on theSCK edge determined by the CPOL and CPHA bits. The affect of these settingis shown in thefollowing diagrams.

The Shift Register transmits and receives the Most Significant Bit first.

Bit 7-0 = DSR7-DSR0:

Data Bits.

These are the

SPI shift register databits.

Miscellaneous Register (MISCR)

Address: DDh — Write only Reset status: xxxxxxxb

Bit 7-1 = D7-D1:

Reserved.

Bit 0 = D0:

Bit 0.

This bit, when set, selects the Sout pin as the SPI output line. When this bit is cleared, Sout acts as a standard I/O line.

SPINT DOV6 DIV5 DIV4 DIV3 CD2 CD1 CD0

CD2-CD0 Divide Ratio (decimal)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 256

DIV6-DIV3 Number of bits sent

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Reserved (not to be used) 1 2 3 4 5 6 7 8 9  10  11  Refer to the 12  description of the 13  DIV6-DIV3 bits in 14  the DIV Register 15 

D7 D6 D5 D4 D3 D2 D1 D0

-------D0

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.6 SPI Timing Diagrams Figure 32. CPOL = 0 Clock Polarity Normal, CPHA = 0Phase Selection Normal

Figure 33. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal

SPRUN

Sout

Sin

b7 b6 b5 b4 b3 b2 b1 b0

VR001694

SCK

Sampling

SPRUN

SCK

Sout

Sin

b7 b6 b5 b4 b3 b2 b1 b0

VR0A1694

Sampling

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

Figure 34. CPOL = 0 Clock Polarity Normal, CPHA = 1Phase Selection Shifted

Figure 35. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted

SPRUN

SCK

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0B1694

Sin

Sampling

SPRUN

SCK

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0C1694

Sin

Sampling

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5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit isstored with the value of the bit when the SET or RES instruction is processed.

5.2 ADDRESSING MODES

The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spacesare available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plusthe datafor immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/ Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAMcells used tostack the return addresses forsubroutines and interrupts.

Immediate. In the immediate addressing mode, the operand of the instruction follows the opcode location. Asthe operandis aROM byte, the immediate addressing mode is used to access constants which donot changeduring program execution (e.g., a constant used to initialize a loop counter).

Direct. In the direct addressing mode, the address of the byte which is processed bythe instruction is stored in the location which follows the opcode. Direct addressing allowsthe userto directly address the 256bytes in Data Space memory with asingle two-byte instruction.

Short Direct. The core can address the four RAM registers X,Y,V,W (locations 80h, 81h,82h, 83h) in the short-directaddressing mode. In this case, the instruction is only one byte and theselection of the location to be processed is contained in the opcode. Shortdirect addressing is a subset of the direct addressing mode. (Note that 80h and 81h are also indirect registers).

Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained byconcatenating thefour less significant

bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space.

An extended addressing mode instruction is twobyte long.

Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of

-15 to +16locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is

0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of thebranch.

Bit Direct. In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the bytein whichthe specified bit mustbe set or cleared. Thus,any bitin the256 locations of Data space memory can beset or cleared.

Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by theassembler.

Indirect. In the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, Xor Y (80h,81h).The indirect register is selected by thebit 4 ofthe opcode.A register indirect instruction is one byte long.

Inherent. In the inherent addressing mode, all the information necessary toexecute theinstruction is contained in the opcode. These instructions are one byte long.

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5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They canbe divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describethe different types.

All the instructions belonging to a given type are presented in individual tables.

Load & Store. These instructionsuse one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memoryusing one of the addressing modes.

For Load Immediate one operand can be any of the 256 data spacebytes while theother is always immediate data.

Table 17. Load & Store Instructions

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register

∆. Affected

* . Not Affected

Instruction Addressing Mode Bytes Cycles

Flags

LD A, X Short Direct 1 4 ∆ * LD A, Y Short Direct 1 4 ∆ * LD A, V Short Direct 1 4 ∆ * LD A, W Short Direct 1 4 ∆ * LD X, A Short Direct 1 4 ∆ * LD Y, A Short Direct 1 4 ∆ * LD V,A Short Direct 1 4 ∆ * LD W, A Short Direct 1 4 ∆ * LD A, rr Direct 2 4 ∆ * LD rr, A Direct 2 4 ∆ * LD A, (X) Indirect 1 4 ∆ * LD A, (Y) Indirect 1 4 ∆ * LD (X), A Indirect 1 4 ∆ * LD (Y), A Indirect 1 4 ∆ *

LDI A, #N Immediate 2 4 ∆ *

LDI rr, #N Immediate 3 4 * *

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INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are

used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions oneoperand is alwaysthe accumulator while the other can be either a data space memorycon-

tent or an immediate value in relation with the addressing mode. InCLR, DEC,INC instructions the operand can be any of the 256 data space addresses. In COM, RLC,SLA the operand is always the accumulator.

Table 18. Arithmetic & Logic Instructions

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register

Instruction Addressing Mode Bytes Cycles

Flags

ADD A, (X) Indirect 1 4 ∆∆ ADD A, (Y) Indirect 1 4 ∆∆ ADD A, rr Direct 2 4 ∆∆ ADDI A, #N Immediate 2 4 ∆∆ AND A, (X) Indirect 1 4 ∆∆ AND A, (Y) Indirect 1 4 ∆∆ AND A, rr Direct 2 4 ∆∆ ANDI A, #N Immediate 2 4 ∆∆ CLR A Short Direct 2 4 ∆∆ CLR r Direct 3 4 * * COM A Inherent 1 4 ∆∆ CP A, (X) Indirect 1 4 ∆∆ CP A, (Y) Indirect 1 4 ∆∆ CP A, rr Direct 2 4 ∆∆ CPI A, #N Immediate 2 4 ∆∆ DEC X Short Direct 1 4 ∆ * DEC Y Short Direct 1 4 ∆ * DEC V Short Direct 1 4 ∆ * DEC W Short Direct 1 4 ∆ * DEC A Direct 2 4 ∆ * DEC rr Direct 2 4 ∆ * DEC (X) Indirect 1 4 ∆ * DEC (Y) Indirect 1 4 ∆ * INC X Short Direct 1 4 ∆ * INC Y Short Direct 1 4 ∆ * INC V Short Direct 1 4 ∆ * INC W Short Direct 1 4 ∆ * INC A Direct 2 4 ∆ * INC rr Direct 2 4 ∆ * INC (X) Indirect 1 4 ∆ * INC (Y) Indirect 1 4 ∆ * RLC A Inherent 1 4 ∆∆ SLA A Inherent 2 4 ∆∆ SUB A, (X) Indirect 1 4 ∆∆ SUB A, (Y) Indirect 1 4 ∆∆ SUB A, rr Direct 2 4 ∆∆ SUBI A, #N Immediate 2 4 ∆∆

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INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions

achieve a branch in the program when the selected condition is met.

Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations.

Control Instructions. The control instructions control the MCU operations during program execution.

Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.

Table 19. Conditional Branch Instructions

Notes:

b. 3-bit address rr. Data space register e. 5 bit signed displacement inthe range -15 to +16<F128M> ∆ . Affected. The tested bit is shifted into carry. ee. 8 bit signed displacement inthe range -126to +129 * . Not Affected

Table 20. Bit Manipulation Instructions

Notes:

b. 3-bit address; * . Not<M> Affected rr. Data space register;

Table 21. Control Instructions

Notes:

1. This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected. ∆ . Affected *. Not Affected

Table 22. Jump & Call Instructions

Notes:

abc. 12-bit address; * . Not Affected

Instruction Branch If Bytes Cycles

Flags

JRCe C=1 1 2 * * JRNC e C = 0 1 2 * * JRZe Z=1 1 2 * * JRNZ e Z = 0 1 2 * * JRR b,rr, ee Bit = 0 3 5 * ∆ JRS b, rr, ee Bit = 1 3 5 * ∆

Instruction Addressing Mode Bytes Cycles

Flags

SET b,rr Bit Direct 2 4 * * RES b,rr Bit Direct 2 4 * *

Instruction Addressing Mode Bytes Cycles

Flags

NOP Inherent 1 2 * * RET Inherent 1 2 * * RETI Inherent 1 2 ∆∆ STOP (1) Inherent 1 2 * * WAIT Inherent 1 2 * *

Instruction

Addressing Mode Bytes Cycles

Flags

CALL abc Extended 2 4 * * JP abc Extended 2 4 * *

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Opcode Map Summary. The following table contains an opcode map for the instructionsused by the ST6

LOW

0000

0001

0010

0011

0100

0101

0110

0111

LOW

HI HI

0000

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD

0000

e abc e b0,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0001

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI

0001

e abc e b0,rr,ee e x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0010

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP

0010

e abc e b4,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI

0011

e abc e b4,rr,ee e a,x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0100

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD

0100

e abc e b2,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0101

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI

0101

e abc e b2,rr,ee e y e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

0110

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC

0110

e abc e b6,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

0111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

0111

e abc e b6,rr,ee e a,y e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

1000

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD

1000

e abc e b1,rr,ee e # e (x),a

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1001

2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC

1001

e abc e b1,rr,ee e v e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

1010

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND

1010

e abc e b5,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI

1011

e abc e b5,rr,ee e a,v e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

1100

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB

1100

e abc e b3,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1101

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI

1101

e abc e b3,rr,ee e w e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

1110

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC

1110

e abc e b7,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

1111

e abc e b7,rr,ee e a,w e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement imm Immediate b 3 Bit Address inh Inherent rr 1byte dataspace address ext Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address bt Bit Test ee 8 bit Displacement pcr Program Counter Relative ind Indirect

JRC

1 prc

Mnemonic

Addressing Mode

Bytes

Cycle Operand

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Opcode Map Summary (Continued)

LOW

1000

1001

1010

1011

1100

1101

1110

1111

LOW

HI HI

0000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD

0000

e abc e b0,rr e rr,nn e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind

0001

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

0001

e abc e b0,rr e x e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP

0010

e abc e b4,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

0011

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP

0011

e abc e b4,rr e x,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0100

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD

0100

e abc e b2,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

0101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD

0101

e abc e b2,rr e y e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

0110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC

0110

e abc e b6,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

0111

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC

0111

e abc e b6,rr e y,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD

1000

e abc e b1,rr e # e (y),a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

1001

2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

1001

e abc e b1,rr e v e rr,a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND

1010

e abc e b5,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1011

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND

1011

e abc e b5,rr e v,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1100

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB

1100

e abc e b3,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB

1101

e abc e b3,rr e w e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

1110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC

1110

e abc e b7,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

1111

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC

1111

e abc e b7,rr e w,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviations for Addressing Modes: Legend:

JRC

1 prc

Mnemonic

Addressing Mode

Bytes

Cycle Operand

65/86

ST62T53C/T60C/T63C ST62E60C

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product containsdevices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages.

For proper operation it is recommended that V

and VObe higher than VSSand lower than VDD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (V

or VSS).

Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from:

Tj=TA + PD x RthJA

Where:TA = Ambient Temperature.

RthJA =Package thermal resistance (junc-

tion-to ambient). PD = Pint + Pport. Pint =IDD x VDD (chip internal power). Pport =Portpower dissipation (determined

by the user).

Notes:

- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of thedevice at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

- (1)Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection current is kept withinthe specification.

Symbol Parameter Value Unit

Supply Voltage -0.3 to7.0 V

Input Voltage VSS- 0.3 toVDD+ 0.3

(1)

Output Voltage VSS- 0.3 toVDD+ 0.3

(1)

TotalCurrent into VDD(source) 80 mA

TotalCurrent out ofVSS(sink) 100 mA

Tj Junction Temperature 150 °C

STG

Storage Temperature -60 to150 °C

66/86

ST62T53C/T60C/T63C ST62E60C

6.2 RECOMMENDED OPERATING CONDITIONS

Notes:

1. Care must be taken in case ofnegative current injection, where adapted impedance must be respected on analog sources to not affect the

A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.

2.An oscillator frequency above 1MHz is recommended forreliable A/D results

Figure 36. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)

The shaded area is outside the recommended operating range; device functionality is notguaranteed under these conditions.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Operating Temperature

6 Suffix Version 1 Suffix Version 3 Suffix Version

-40 0

-40

85 70

125

°C

Operating Supply Voltage (Except ST626xB ROM devices)

OSC

=4MHz, 1 & 6 Suffix

OSC

=4MHz, 3 Suffix fosc= 8MHz ,1 & 6 Suffix fosc= 8MHz ,3 Suffix

3.0

3.6

4.5

6.0

Operating Supply Voltage (ST626xB ROM devices)

OSC

=4MHz, 1 & 6 Suffix f

OSC

=4MHz, 3 Suffix fosc= 8MHz ,1 & 6 Suffix fosc= 8MHz ,3 Suffix

3.0

4.0

4.5

6.0

OSC

Oscillator Frequency

(Except ST626xB ROM devices)

= 3.0V,1 & 6 Suffix

= 3.0V , 3 Suffix

= 3.6V , 1 & 6 Suffix

= 3.6V , 3 Suffix

0 0 0 0

4.0

8.0

4.0

MHz

Oscillator Frequency

(ST626xB ROM devices)

= 3.0V,1 & 6 Suffix

= 3.0V , 3 Suffix

= 4.0V , 1 & 6 Suffix

= 4.0V , 3 Suffix

0 0 0 0

4.0

8.0

4.0

MHz

INJ+

Pin Injection Current (positive) VDD= 4.5 to 5.5V +5 mA

INJ-

Pin Injection Current (negative) VDD= 4.5 to 5.5V -5 mA

2.5 3 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

Maximum FREQUENCY (MHz)

FUNCTIONALITY IS NOT

GUARANTEED IN

THIS AREA

3 Suffix version

1 & 6 Suffix version

3.6

3 Suffix version

ST626xB ROM devices

All devices except ST626xB ROM devices

1 & 6 Suffix

version

67/86

ST62T53C/T60C/T63C ST62E60C

6.3 DC ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

(1) Hysteresis voltage between switching levels (2) All peripherals running (3) All peripherals in stand-by

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Input Low Level Voltage All Input pins

x 0.3 V

Input High LevelVoltage All Input pins

x 0.7 V

Hys

Hysteresis Voltage

(1)

All Input pins

=5V

=3V

0.2

LVD Threshold in power-on 4.1 4.3

LVD threshold in powerdown 3.5 3.8

Low Level Output Voltage All Output pins

VDD= 5.0V; IOL= +10µA V

= 5.0V; IOL= + 3mA

0.1

0.8 V

Low Level Output Voltage 30 mA Sink I/O pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= +7mA

= 5.0V; IOL= +15mA

0.1

0.8

1.3

High Level Output Voltage All Output pins

VDD= 5.0V; IOH= -10µA V

= 5.0V; IOH= -3.0mA

4.9

3.5

Pull-up Resistance

All Input pins 40 100 350

ΚΩ

RESET pin 150 350 900

Input Leakage Current All Input pins but RESET

VIN=VSS(No Pull-Up configured) V

IN=VDD

0.1 1.0 µA

Input Leakage Current RESET pin

IN=VSS

VIN=V

-8 -16 -30 10

Supply Current in RESET Mode

RESET=VSS

OSC

=8MHz

7mA

Supply Current in RUN Mode

(2)

VDD=5.0V f

INT

=8MHz 7 mA

Supply Current in WAIT Mode

(3)

VDD=5.0V f

INT

=8MHz 2.5 mA

Supply Current in STOP Mode, with LVD disabled

(3)

LOAD

=0mA

=5.0V

20 µA

Supply Current in STOP Mode, with LVD enabled

(3)

LOAD

=0mA

=5.0V

500

Retention EPROM Data Retention T

=55°C 10 years

68/86

ST62T53C/T60C/T63C ST62E60C

DC ELECTRICAL CHARACTERISTICS (Cont’d)

(TA= -40 to +85°C unless otherwise specified))

Note: (*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

1. Period for which V

has to be connected at 0V to allow internal Reset function at next power-up.

2 An oscillator frequency above 1MHz is recommended for reliable A/D results.

3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

LVD Threshold in power-on Vdn+50 mV 4.1 4.3 V

LVD threshold in powerdown 3.6 3.8 Vup-50 mV V

Low Level Output Voltage All Output pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= + 5mA

= 5.0V; IOL= + 10mAv

0.1

0.8

1.2 V

Low Level Output Voltage 30 mA Sink I/O pins

= 5.0V; IOL= +10µA

= 5.0V; IOL= +10mA

= 5.0V; IOL= +20mA

= 5.0V; IOL= +30mA

0.1

0.8

1.3

2.0

High Level Output Voltage All Output pins

VDD= 5.0V; IOH= -10µA V

= 5.0V; IOH= -5.0mA

4.9

3.5

Supply Current in STOP Mode, with LVD disabled

(*)

LOAD

=0mA

=5.0V

10 µA

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

REC

Supply Recovery Time

(1)

100 ms

WEE

EEPROM Write Time

=25°C

=85°C

=125°C

5 10 20

10 20 30

Endurance

(2)

EEPROM WRITE/ERASE Cycle QALOTAcceptance (25°C) 300,000 1 million cycles

Retention EEPROM Data Retention T

=55°C 10 years

LFAO

Internal frequency with LFAO active 200 400 800 kHz

OSG

Internal Frequency with OSG enabled

VDD=3V V

= 3.6V

= 4.5V

=6V

1 1 2 2

OSC

MHz

Internal frequency with RC oscillator and OSG disabled

2) 3)

VDD=5.0V (Except 626xB ROM) R=47kΩ R=100kΩ R=470kΩ

2.7

800

3.2

850

5.8

3.5

900

MHz MHz

kHz

VDD=5.0V (626xB ROM) R=10kΩ R=27kΩ R=100kΩ

2.4

1.8

800

3.1

2.2

980

3.8

2.5

1200

MHz MHz

kHz

Input Capacitance All Inputs Pins 10 pF

OUT

Output Capacitance All Outputs Pins 10 pF

69/86

ST62T53C/T60C/T63C ST62E60C

6.5 A/D CONVERTER CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Notes:

1. Noise at VDD, VSS <10mV

2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

6.6 TIMER CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

6.7 SPI CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

(TA= -40 to +125°C unless otherwise specified)

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Res Resolution 8 Bit

TOT

TotalAccuracy

(1) (2)

OSC

> 1.2MHz

OSC

> 32kHz

±2 ±4

LSB

Conversion Time

OSC

= 8MHz (TA<85°C)

OSC

= 4 MHz

140

µs

ZIR Zero Input Reading

Conversion result when V

IN=VSS

00 Hex

FSR Full Scale Reading

Conversion result when V

IN=VDD

FF Hex

Analog Input CurrentDuring Conversion

= 4.5V 1.0 µA

Analog Input Capacitance 2 5 pF

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Input Frequency on TIMER Pin MHz

Pulse Width at TIMER Pin

= 3.0V

>4.5V

125

µs ns

IINT

----------

70/86

ST62T53C/T60C/T63C ST62E60C

Figure 37. Vol versus Iol on all I/O port at Vdd=5V

Figure 38. Vol versus Iol on all I/O port atT=25°C

Figure 39. Vol versus Iol for High sink (30mA) I/Oports at T=25°C

010203040

Iol (mA)

Vol (V)

T=-40°C T=25°C

T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

010203040

Iol (mA)

Vol (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curves represents typical variations and is givenfor guidance only

0 10203040

Iol (mA)

Vol (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curves represents typical variations and is given for guidance only

71/86

ST62T53C/T60C/T63C ST62E60C

Figure 40. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V

Figure 41. Voh versus Ioh on all I/O port at 25°C

Figure 42. Voh versus Ioh on all I/O port at Vdd=5V

0 10203040

Iol (mA)

Vol (V)

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

0 10203040

-2

Ioh (mA)

Voh (V)

Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V

This curvesrepresents typical variations andis given for guidance only

0 10203040

-2

Ioh (mA)

Voh (V)

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

72/86

ST62T53C/T60C/T63C ST62E60C

Figure 43. Idd WAIT versus Vcc at 8 Mhz for OTP devices

Figure 44. Idd STOP versus Vcc for OTP devices

Figure 45. Idd STOP versus Vcc for ROM devices

This curves represents typical variations and is given for guidance only

0.5

1.5

2.5

Vdd

Idd WAIT(mA)

3V 4V 5V 6V

T=-40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

-2

Vdd

Idd STOP(µA)

3V 4V 5V 6V

T = -40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

-0.5

0.5

1.5

Vdd

Idd STOP(µA)

3V 4V 5V 6V

T = -40°C T=25°C T=95°C T = 125°C

73/86

ST62T53C/T60C/T63C ST62E60C

Figure 46. Idd WAIT versus Vcc at 8Mhz for ROM devices

Figure 47. Idd RUN versus Vcc at8 Mhz for ROM and OTP devices

Figure 48. LVD thresholds versus temperature

This curves represents typical variations and is given for guidance only

0.5

1.5

2.5

Vdd

Idd WAIT(mA)

3V 4V 5V 6V

T = -40°C T=25°C

T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

Vdd

Idd RUN (mA)

3V 4V 5V 6V

T=-40°C T=25°C T=95°C T = 125°C

This curves represents typical variations and is given for guidance only

3.7

3.8

3.9

4.1

4.2

Temp

Vthresh.

-40°C25°C95°C125°C

Vup Vdn

74/86

ST62T53C/T60C/T63C ST62E60C

Figure 49. RC frequency versus Vcc for ROM ST626xB only

Figure 50. RC frequency versus Vcc (Except for ST626xB ROM devices)

This curves represents typical variations and is given for guidance only

3 3.5 4 4.5 5 5.5 6

0.1

MHz

VDD (volts)

Frequency

R=10K R=27K R=100K

This curves represents typical variations and is given for guidance only

3 3.5 4 4.5 5 5.5 6

0.1

MHz

VDD (volts)

Frequency

R=47K R=100K R=470K

75/86

ST62T53C/T60C/T63C ST62E60C

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA Figure 51. 20-Pin Plastic Dual In-Line Package, 300-mil Width

Figure 52. 20-Pin Ceramic Side-Brazed Dual In-Line Package

Dim.

mm inches

Min Typ Max Min Typ Max

A 5.33 0.210

A2 2.92 3.30 4.95 0.115 0.130 0.195

b 0.36 0.46 0.56 0.014 0.018 0.022

b2 1.14 1.52 1.78 0.045 0.060 0.070

c 0.20 0.25 0.36 0.008 0.010 0.014

D 24.89 26.92 0.980 1.060

e 2.54 0.100

E1 6.10 6.35 7.11 0.240 0.250 0.280

L 2.92 3.30 3.81 0.115 0.130 0.150

Number of Pins

N 20

PDIP20

Dim.

mm inches

Min Typ Max Min Typ Max

A 3.63 0.143

A1 0.38 0.015

B 3.56 0.46 0.56 0.140 0.018 0.022

B1 1.14 12.70 1.78 0.045 0.500 0.070

C 0.20 0.25 0.36 0.008 0.010 0.014 D 24.89 25.40 25.91 0.980 1.000 1.020

D1 22.86 0.900

E1 6.99 7.49 8.00 0.275 0.295 0.315

e 2.54 0.100

G 6.35 6.60 6.86 0.250 0.260 0.270 G1 9.47 9.73 9.98 0.373 0.383 0.393 G2 1.14 0.045

L 2.92 3.30 3.81 0.115 0.130 0.150 S 12.70 0.500

Ø 4.22 0.166

Number of Pins

N20

CDIP20W

76/86

ST62T53C/T60C/T63C ST62E60C

PACKAGE MECHANICAL DATA (Cont’d) Figure 53. 20-Pin Plastic Small Outline Package, 300-mil Width

7.2 ORDERING INFORMATION Table 23. OTP/EPROM VERSION ORDERING INFORMATION

Sales Type

Program

Memory (Bytes)

EEPROM (Bytes) Temperature Range Package

ST62T53CB6 ST62T53CB3

1836 (OTP) -

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST62T53CM6 ST62T53CM3

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST62T60CB6 ST62T60CB3

3884 (OTP) 128

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST62T60CM6 ST62T60CM3

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST62T63CB6

1836 (OTP) 64 -40 to+ 85°C

PDIP20 ST62T63CM6 PSO20 ST62E60CF1 3884 (EPROM) 128 0 to +70°C CDIP20

Dim.

mm inches

Min Typ Max Min Typ Max

A 2.35 2.65 0.0926 0.1043

A1 0.10 0.0040

B 0.33 0.51 0.0130 0.0200 C 0.32 0.0125 D 4.98 13.00 0.1961 0.5118 E 7.40 7.60 0.2914 0.2992 e 1.27 0.050 H 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 K 0° 8° 0° 8° L 0.41 1.27 0.016 0.050 G 0.10 0.004

Number of Pins

N20

SO20

November 1999 77/86

Rev. 2.6

ST62P53C/P60C/P63C

8-BIT FASTROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM:64/128bytes(noneonST62P53C)

■ User Programmable Options

■ 13 I/O pins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 6 I/Olines can sink up to 30mA todrive LEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ Oscillator SafeGuard

■ Low Voltage Detector for Safe Reset

■ 8-bit A/D Converter with 7 analog inputs

■ 8-bit Synchronous Peripheral Interface (SPI)

■ On-chip Clockoscillator can be driven by Quartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port).

DEVICE SUMMARY

DEVICE ROM (Bytes) EEPROM

ST62P53C 1836 ST62P60C 3884 128 ST62P63C 1836 64

PDIP20

PSO20

(See endof Datasheet for Ordering Information)

78/86

ST62P53C/P60C/P63C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62P53C, ST62P60C and ST62P63C are the Factory Advanced Service Technique ROM (FASTROM) versions of ST62T53C, ST6260B and ST62T63C OTP devices.

They offer the same functionality as OTPdevices, selecting as FASTROM options the options defined in the programmable option byte of the OTP version.

1.2 ORDERING INFORMATION

The following section deals with the procedure for transfer ofcustomer codes to STMicroelectronics.

1.2.1 Transfer of Customer Code

Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes mustbe set to FFh.

The selected options are communicated to STMicroelectronics using the correctly filled OPTION LIST appended.

1.2.2 Listing Generation and Verification

When STMicroelectronics receives the user’s ROM contents, a computer listing is generated from it. This listing refers exactly to the ROM con-

tents and options which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listingforms a part of the contractual agreement for the production of the specific customer MCU.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Table 1. ROM Memory Map for ST62P60C

Table 2. ROM Memory Map for ST62P53C/P63C

Table 3. FASTROM version Ordering Information

(*) Advanced information

Device Address Description

0000h-007Fh

0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Sales Type ROM (Bytes) EEPROM (Bytes) Temperature Range Package

ST62P53CB1/XXX ST62P53CB6/XXX ST62P53CB3/XXX (*)

1836 -

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST62P53CM1/XXX ST62P53CM6/XXX ST62P53CM3/XXX (*)

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST62P60CB1/XXX ST62P60CB6/XXX ST62P60CB3/XXX (*)

3884 128

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST62P60CM1/XXX ST62P60CM6/XXX ST62P60CM3/XXX (*)

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST62P63CB1/XXX ST62P63CB6/XXX ST62P63CB3/XXX (*)

1836 64

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST62P63CM1/XXX ST62P63CM6/XXX ST62P63CM3/XXX (*)

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

79/86

ST62P53C/P60C/P63C

ST62P53C, ST62P60C and ST62P63C FASTROM MICROCONTROLLER OPTION LIST

Customer . . . . . .. . . . . .. . . . . . . . . . . . . . . . .

Address . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

.............................

Contact . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

Phone No . . . . . .. . . . . .. . . . . . . . . . . . . . . . .

Reference . . . . . . .. . .. . . . . . . . .. . . . . . . . . .

STMicroelectronics references Device: [ ] ST62P53C [ ] ST62P60C [ ] ST62P63C Package: [ ] Dual in Line Plastic[ ] Small Outline Plastic with conditioning

[ ]Standard (Stick) [ ]Tape & Reel

Temperature Range: [ ] 0°Cto+70°C[]-40°Cto+85°C []-40°C to + 125°C

Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator

[ ] RC Network

Watchdog Selection: [ ] Software Activation (STOP mode available)

[ ] Hardware Activation (no STOP mode)

Power on Reset Delay [ ] 32768 cycle delay

[ ] 2048 cycle delay

PB0..PB1 Pull-Up at RESET [ ] Enabled

[ ] Disabled

PB2..PB3 Pull-Up at RESET [ ] Enabled

[ ] Disabled

Readout Protection: [ ] Enabled

[ ] Disabled

External STOP Mode Control [ ] Enabled

[ ] Disabled

LVD Reset [ ] Enabled

[ ] Disabled

ADC Synchro [ ] Enabled

[ ] Disabled

Oscillator Safe Guard [ ] Enabled

[ ] Disabled

Comments : Supply Operating Range in the application: Oscillator Fequency in the application:

Notes . . . .. . . . . . . . . . . . . . .. . . . . . . . . .

Signature . . . .. . . . . . . . . . . . . . .. . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

80/86

ST62P53C/P60C/P63C

Notes:

November 1999 81/86

Rev. 2.6

ST6253C/60B/63B

8-BIT ROM MCUs WITH A/D CONVERTER,

SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ DataEEPROM:64/128bytes(noneon ST6253C)

■ User Programmable Options

■ 13 I/O pins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 6 I/Olines can sink up to 30mA todrive LEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ 8-bit A/D Converter with 7 analog inputs

■ 8-bit Synchronous Peripheral Interface (SPI)

■ On-chip Clockoscillator can be driven by Quartz

Crystal Ceramic resonator or RCnetwork

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a parallel port).

DEVICE SUMMARY

DEVICE ROM (Bytes) EEPROM LVD & OSG

ST6253C 1836 - Yes

ST6260B 3884 128 No ST6263B 1836 64 No

PDIP20

PSO20

(See endof Datasheet for Ordering Information)

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ST6253C/60B/63B

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6253C, ST6260B and ST6263B are mask programmed ROM versions of ST62T53C, ST6260B and ST62T63C OTP devices.

They offer the same functionality as OTPdevices, selecting as ROM options the options defined in the programmableoption byte of the OTP version, except the LVD &OSG options thatare not available on the ST6260B/63B ROM device.

Figure 1. Programming wave form

1.2 ROM READOUT PROTECTION

If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to prevent any access to theprogram memory content.

In case the user wants to blow this fuse, highvoltage must be applied onthe TEST pin.

Figure 2. Programming Circuit

Note: ZPD15 is used for overvoltage protection

0.5s min

TEST

14V typ

TEST

100mA

4mA typ

VR02001

max

150 µstyp

VR02003

TEST

100nF

47mF

PROTECT

100nF

ZPD15 15V

14V

83/86

ST6253C/60B/63B

ST6253C, ST6260B and ST6263B MICROCONTROLLER OPTION LIST

Customer . . . . . .. . . . . .. . . . . . . . . . . . . . . . .

Address . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

.............................

Contact . . . . . . . . . . . .. . . . . . . . . . . . . . . . .

Phone No . . . . . .. . . . . .. . . . . . . . . . . . . . . . .

Reference . . . . . . .. . .. . . . . . . . .. . . . . . . . . .

STMicroelectronics references Device: [ ] ST6253C [] ST6260B [ ] ST6263B Package: [ ] Dual in Line Plastic[ ] Small Outline Plastic with conditioning

[ ]Standard (Stick)

[ ]Tape & Reel Temperature Range: [ ] 0°Cto+70°C[]-40°Cto+85°C []-40°C to + 125°C Special Marking: [ ] No [ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ” Authorized characters are letters, digits, ’.’,’-’, ’/’ and spaces only. Maximum character count: DIP28: 10

SO28: 8

Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator

[ ] RC Network

Watchdog Selection: [ ] Software Activation (STOP mode available)

[ ] Hardware Activation (no STOP mode)

Power on Reset Delay [ ] 32768 cycle delay

[ ] 2048 cycle delay PB0..PB1 Pull-Up at RESET [ ] Enabled [ ] Disabled PB2..PB3 Pull-Up at RESET [ ] Enabled [ ] Disabled ROM Readout Protection: [ ] Standard (Fuse cannot be blown)

[ ] Enabled (Fuse can be blown by the customer)

Note: Nopart is delivered with protected ROM.

The fuse must be blown for protection to be effective. External STOP Mode Control [ ] Enabled [ ]Disabled LVD Reset* [ ] Enabled [ ] Disabled ADC Synchro* [ ] Enabled [ ] Disabled Oscillator Safe Guard* [ ] Enabled [ ]Disabled

*ST6253C only

Notes . . . .. . . . . . . . . . . . . . .. . . . . . . . . .

Signature . . . .. . . . . . . . . . . . . . .. . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

84/86

ST6253C/60B/63B

1.3 ORDERING INFORMATION

The following section deals with the procedure for transfer ofcustomer codes to STMicroelectronics.

1.3.1 Transfer of Customer Code

Customer code is made up of the ROM contents and the listof the selectedmask options. The ROM contents are to be sent on diskette,or by electronic means, with the hexadecimal file generated by the development tool.All unused bytes must be set to FFh.

The selected mask options are communicated to STMicroelectronics using the correctly filled OPTION LIST appended.

1.3.2 Listing Generation and Verification

WhenSTMicroelectronicsreceives theuser’sROM contents, a computer listing is generated from it. This listing refers exactly to the mask which will be used to produce the specified MCU. The listing is then returnedto thecustomer who must thoroughly check, complete,sign andreturn it to STMicroelectronics. Thesigned listing forms a part of the con-

tractual agreement for the creation of the specific customer mask.

The STMicroelectronics Sales Organization will be pleased toprovide detailed information on contractual points.

Table 1. ROM Memory Map for ST6260B

Table 2. ROM Memory Map for ST6253C/63B

Device Address Description

0000h-007Fh

0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

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ST6253C/60B/63B

ORDERING INFORMATION (Cont’d) Table 3. ROM version Ordering Information

Sales Type ROM (Bytes) EEPROM (Bytes) Temperature Range Package

ST6253CB1/XXX ST6253CB6/XXX ST6253CB3/XXX

1836 -

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST6253CM1/XXX ST6253CM6/XXX ST6253CM3/XXX

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST6260BB1/XXX ST6260BB6/XXX ST6260BB3/XXX

3884 128

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST6260BM1/XXX ST6260BM6/XXX ST6260BM3/XXX

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

ST6263BB1/XXX ST6263BB6/XXX ST6263BB3/XXX

1836 64

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PDIP20

ST6263BM1/XXX ST6263BM6/XXX ST6263BM3/XXX

0to+70°C

-40 to+ 85°C

-40 to+ 125°C

PSO20

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ST6253C/60B/63B

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of useof such information nor for any infringement of patents or otherrights of third parties which may result from itsuse. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys alicense under the Philips I2C Patent. Rights to use these components in an

C system is granted provided that the system conforms to the I2C Standard Specification asdefined by Philips.

STMicroelectronics Group of Companies

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http://www.st.com

Datasheet ST62T60CB3, ST62T60CM6, ST62T60CM3, ST62T60CB6, ST62T53CM6 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual