Datasheet ST62T10CM6, ST62T20CM6, ST62T20CM3, ST62T20CB6, ST62T20CB3 Datasheet (SGS Thomson Microelectronics)

September 1998 1/70

Rev. 2.6

ST62T08C/T0 9C

ST62T10C/T20C/E20C

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS

■

3.0 to 6.0V Supply Operating Range

■

8 MHz Maximum Clock Frequency

■

-40 to +125°C Operating Temperature Range

■

Run, Wait and Stop Modes

■

5 Interrupt Vectors

■

Look-up Table capability in Program Memory

■

Data Storage in Program Memory:
User selectable size

■

Data RAM: 64bytes

■

User Programmable Options

■

12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62T08C)

■

4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly

■

8-bit Timer/Counter with 7-bit programmable
prescaler

■

Digital Watchdog

■

Oscillator Safe Guard

■

Low Voltage Detector for Safe Reset

■

8-bit A/D Converter with up to 8 analog inputs

■

On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network

■

Power-on Reset

■

One external Non-Maskable Interrupt

■

ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)

DEVICE SUMMARY

PDIP20

PSO20

CDIP20W

(See end of Datasheet for Ordering Information)

DEVICE

OTP

(Bytes)

EPROM

(Bytes)

I/O Pins

Analog

inputs

ST62T08C 1036 - 12 ­ST62T09C 1036 - 12 4
ST62T10C 1836 - 12 8
ST62T20C 3884 - 12 8
ST62E20C - 3884 12 8

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Table of Contents

70

Document

Page

90

ST62T08C/T09C/ST62T10C/T20C/E20C . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 14

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.2 Low Frequency Au xiliar y Os cillat or (LFA O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.3 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.5 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ST62P08C/P09C/ST62P10C/P20C . . . . . . . . . . . . . . . . . . . . . . 61

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

ST6208C/09C/ST6210C/20C . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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ST62T08C/T09C ST62T10C/T20C/E20 C

1 GENERAL DESCRIPTIO N

1.1 INTRODUCTION

The ST62T08C,T09C,T10C,T20C and ST62E20C
devices are low cost members of the ST62xx 8-bit
HCMOS family of microcontrollers, which is target­ed at low to medium complexity applications. All
ST62xx devices are based on a building block ap­proach: a common core is surrounded by a
number of on-chip peripherals.

The ST62E20C is the erasable EPROM version of
the ST62T08C,T09C,T10C and T20C device,
which may be used to emulate the
ST62T08C,T09C,T10C and T20C device, as well
as the respective ST6208C,09C,10C,20C ROM
devices.

OTP and E PROM dev ices are func tionally identi­cal. The ROM based versions offer the same func-

tionality selecting as ROM opt ions t he op tio ns de­fined in the programmable option bytes of the
OTP/EPROM versions.

OTP devices offer all the advant ages of user pro­grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code chang es, mul tiple code vers ions or
last minute programmability are required.

These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program­mable prescaler,an 8-bit A/ D Co nve rter with u p t o
8 analog inputs and a Digital Watchdog timer,
making them well suited for a wide range of auto­motive, appliance and industrial applications.

Figure 1. Bloc k D ia gram

TEST

NMI

INTERRUPT

PROGRAM

1836 Bytes

PC

STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6

POWER
SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM
64 Bytes

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

PP

3884 Bytes

(ST62T10C)

(ST62T20C, E20C)

8-BIT

A/D CONVERTER

PA0..PA3 (20mA Sink)

TIMER

V

DDVSS

OSCin O SCou t RESET

WATCHDOG

:

MEMORY

PB0..PB7 / Ain (*)

1036 Byt es

(ST62T08C,T09C)

(*) Analog input availability depend on versions

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ST62T08C/T09C ST62T10C/T20C /E20C

1.2 PIN DESCRIPTIONS
V

DD

and V

SS

. Power is supplied to the MCU via

these two pins. V

DD

is the power conn ection and

V

SS

is the ground connection.

OSCin and OSCout.

These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the O SCout pin is
the output pin.

RESET

. The active-low RESET pin is used to re­start the microcontroller. Internal pull-up is p rovid­ed at this pin.

TEST/V

PP

.

The TEST must be held a t V

SS

for nor­mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.

NMI.

The NMI pin provides the capability for asyn­chronous interruption, by applying an external non
maskable interrupt to the MCU. The NM I input is
falling edge sensitive. The user can select as op­tion the availability of an on-chip pull-up at this pin.

TIMER.

This is the timer I/O pin. In input mode it is
connected to the prescaler and acts as external
timer clock input or as control gate input for the in­ternal timer clock. In output mode the timer pin out­puts the data bit when a time-out occurs. The user
can selec t as option the availability of an on-chip
pull-up at this pin.

PA0-PA3.

These 4 lines are organized as one I/O
port (A). Each line may be configu red under soft­ware control as inputs with or without internal pull­up resistors, interrupt generating inputs with pull-

up resistors, open-drain or push-pull outputs. PA0­PA3 can also sink 20mA for direct LED driving.

PB0-PB7.

These 8 lines are organized as one I/O
port (B). Each line may be configured under soft­ware control as inputs with or without internal pull­up resistors, interrupt generating inputs with pull­up resistors, open-drain or push-pull outputs. PB0­PB3 can be u sed as analog inp ut to the A /D con­verter on the ST62T10C , T20C and E20C, while
PB4-PB7 can be used as analog inputs for the A/D
converter on the ST62T09C, T10C, T20C and
E20C.

Figure 2. ST62T08C,T09C, T10C, T20C and
E20C Pin Configurat io n

1
2
3
4
5
6
7
8
9

10

11

12

13

14

15

16

17

18

19

20

V

DD

TIMER

OSCin

OSCout

NMI

V

PP

/TEST

RESET
Ain*/PB7
Ain*/PB6
Ain*/PB5

V

SS

PA0/20 mA Sink
PA1/20 mA Sink
PA2/20 mA Sink
PA3/20 mA Sink

PB0/Ain*
PB1/Ain*
PB2/Ain*
PB3/Ain*
PB4/Ain*

*Analog input availability depend on device

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ST62T08C/T09C ST62T10C/T20C/E20 C

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.

Briefly, Program space contains user program
code in OTP and user vectors; Data space con­tains user data in RAM and in OTP, and Stack
space accommodat es six levels of stack for sub­routine and interrupt service routine nesting.

Figure 3. Me m ory A ddressing D iagram

PROGRAM SPAC E

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

DATA RAM

BANK SELECT

WINDOW SELECT

RAM

X REGISTER
Y REGISTER
V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW

RAM / EEPROM
BANKING AREA

000h

03Fh

040h

07Fh

080h

081h

082h

083h

084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

MEMORY

MEMORY

DATA READ-ONLY

MEMORY

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ST62T08C/T09C ST62T10C/T20C /E20C

MEMORY MAP

(Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be
executed, the data required for immediate ad­dressing mode instructions, the reserved factory
test area and the user v ectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register)Program Memory Protection.

The Program Mem ory in O TP o r EP ROM devices
can be protected against external readout of mem­ory by selecting the READOUT PROTECTION op­tion in the option byte.

In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.

Note:

Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac­cepted.

Figure 4. Program Memo ry Map

(*) Reserved areas should be filled with 0FFh

0000h

0AFFh
0B00h

0B9Fh

NOT IMPLEMENTED

RESERVED

*

USER

PROGRAM MEMORY

(OTP)

1024 BYTES

0BA0h

0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh

RESERVED

*

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

0000h

07Fh

USER

PROGRAM MEMORY

(OTP/EPROM)

3872 BYTES

080h

0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h

0FFBh
0FFCh
0FFDh
0FFEh
0FFFh

RESERVED

*

RESERVED

*

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

RESERVED

*

0000h

07FFh
0800h

087Fh

NOT IMPLEMENTED

RESERVED

*

USER

PROGRAM MEMORY

(OTP)

1824 BYTES

0880h

0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h

0FFBh
0FFCh
0FFDh
0FFEh
0FFFh

RESERVED

*

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

ST62T08C,T 09C ST62T10C ST62T20C,E20C

95

8/70

ST62T08C/T09C ST62T10C/T20C/E20 C

MEMORY MAP

(Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary
for processing the user program. This space com­prises the RAM resource, the proces sor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory cons equently con­tains the program code to be executed, as well as
the constants and look-up tables required by the
application.

The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM

In ST6208C/09C/10C/20C devices, the data
space includes 60 bytes of RAM , the ac cumu lator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe­ripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).

1.3.4 Stack Space

Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.

Table 1. ST6208C/09C/10C/20C Data Memory
Space

RESERVED

000h
03Fh

DATA RO M WINDOW A REA

64 BYTES

040h

07Fh
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h

W REGISTER 083h

DATA RAM 60 BYTES

084h

0BFh

PORT A DATA REGISTER 0C0h
PORT B DATA REGISTER 0C1h

RESERVED 0C2h

RESERVED 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h

RESERVED 0C6h

RESERVED 0C7h

INTERRUP T OP T ION REGISTER 0C8h*
DATA ROM WINDOW REGISTER 0C9h*

RESERVED

0CAh

0CBh
PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh

RESERVED 0CEh
RESERVED 0CFh

A/D DATA REG I ST ER(ex ce pt ST62T08C) 0D0h

A/D CONTROL REGISTER (except ST62T08C) 0D1h

TIMER PRESCALER REGISTER 0D2h

TIMER COUNTER REGISTER 0D3h

TIMER S TA T US CO NT ROL REGIST E R 0D4h

RESERVED

0D5h
0D6h
0D7h

WATCHD O G REG I ST ER 0D8h

RESERVED

0D9h
0FEh

ACCUMULATOR 0FFh

* WRITE ONLY REGISTE R

96

9/70

ST62T08C/T09C ST62T10C/T20C /E20C

MEMORY MAP

(Cont’d)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat­ed anywhere in program memory, between ad­dress 0000h and 0FFFh (top memory address de­pends on the specific device). All the program
memory can therefore be used to store ei ther in­structions or read-only data. Indeed, the window
can be moved i n steps of 64 byt es along the pro­gram memory by writing the appropriate code in the
Data Window Register (DWR).

The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis­ter and therefore cannot be accessed using single­bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program me mory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat­ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load­ed in the DWR register, the physical location a d­dressed in program memory is 00h. The DWR reg­ister is not cleared on reset, therefore it m ust be
written to prior to the first access to the Data read­only memory window area.

Data Wind ow R eg ist er (DWR)

Address: 0C9h — Write Only

Bits 6, 7 = Not used.
Bit 5-0 =

DWR5-DWR0:

Data read-only memory

Window Register Bits.

These are the Data read­only memory Window bits that correspond to the
upper bits of the data read-only memory space.

Caution:

This register is undefined on reset. Nei­ther read nor single bit instructions may be used to
address this register.

Note:

Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should no t be changed while exe­cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ­ing to the DWR during the interrupt service routine,
an image of the regi ster must be sav ed in a R AM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in­terrupt occurs between the two instructions, the
DWR is not affected.

Figure 5. Data read-only memory Window Memo ry Add ressi ng

70

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

765432 0

543210

543210

READ

1

67891011

0

1

VR01573C

12

1

0

DATA SPACE ADDRESS

:

:

59h

000

0

1

00

1

11

Example:

(DWR)

DWR=28h

1100000001

ROM

ADDRESS:A19h

11

13

0

1

97

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ST62T08C/T09C ST62T10C/T20C/E20 C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capabili­ty to the MCUs. Option byte’s content is automati­cally read, and the selected options enabled, when
the chip reset is activated.

It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro­grammer.

The option bytes are located in a non-user m ap.
No address has to be specified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D10.

Reserved. Must be cleared

EXTCNTL.

External STOP MODE control.

. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one.. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.

LVD.

LVD RESET enable.

When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.

PROTECT

.

Readout Protection.

This bit allows the
protection of the software contents aga inst p iracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.

OSCIL

.

Oscillator selection

. When this bit is low,
the oscillator must b e controlled by a quartz crys­tal, a ceramic resonator or an ex ternal frequenc y.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.

D5.

Reserved. Must be cleared to zero.

D4.

Reserved. Must be set to one.

NMI P U L L.

NMI Pull-Up

. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided

.

TIM PULL .

TIM Pull-Up

. This bit must be set hi gh
to configure the TIME R pi n wi th a pull-up resistor.
When it is low, no pull-up is provided

.

WDACT

. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation i s sele cted when WDAC T
is low.

OSGEN

.

Oscillator Safe Guard

. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.

The Option byte is writt en duri ng programming ei­ther by using the PC menu (PC driven M ode) or
automatically (stand-alone mode)

70

PRO­TECT

OSCIL - -

NMI

PULL

TIM

PULL

WDACT

OS-

GEN

15 8

------

EXTC-

NTL

LVD

98

11/70

ST62T08C/T09C ST62T10C/T20C /E20C

PROGRA MMING MODES

(Cont’d)

1.4.2 Program Memory

EPROM/OTP programming mode is set by a
+12.5V voltage ap plied to the T EST/V

PP

pin. The
programming flow of the
ST62T08C,T09C,T10C,T20C/E20C is described
in the User Manual of the EPROM Programming
Board.

Table 2. ST62T08C, T09C Program Memory Map

Table 3. ST62T10C Program Memory Map

Table 4. ST62T20C,E20C Program Memory Map

Note

: OTP/EPROM dev ices can be programmed
with the development tools avai lable from STMi­croelectro n ics (ST62E2X-EPB o r ST62 2X -KIT).

1.4.3 EPROM Erasing

The EPROM of the windowed package of the
MCUs may be e rased b y exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is ex­posed to light with a wave lengths shorter than ap­proximately 4000Å. It should be noted that sun­lights and some types of fluorescent lam ps have
wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test­ing the application in such an environment.

The recommended erasure procedure of the
MCUs EPROM is the exposure to short w ave ul­traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 30W­sec/cm

2

. The erasure tim e wi th t his do sa ge i s ap­proximately 30 to 40 minutes using an ultraviolet
lamp with 12000µW/cm

2

power rating. The
ST62E20C should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.

Device Address Descrip tion

0000h-0B9F h
0BA0h-0F9F h
0FA0h-0FEF h
0FF0h-0FF7 h
0FF8h-0FFB h

0FFCh-0FFD h

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Descrip tion

0000h-087F h

0880h-0F9F h
0FA0h-0FEF h
0FF0h-0FF7 h
0FF8h-0FFB h

0FFCh-0FFD h

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-007Fh
0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

99

12/70

ST62T08C/T09C ST62T10C/T20C/E20 C

2 CENTRAL PR OCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the
I/O or Memory conf iguration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and P e­ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe­ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.

Accumulator (A)

. The accumulator is an 8-bit
general purpose register used in all arithmetic cal­culations, logical operations, and data manipula­tions. The accumulator can be ad dressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.

Indirect Registers (X, Y).

These two indirect reg­isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad­dressed in the data space as RAM locations at ad­dresses 80h (X) and 81h (Y). They can also be ac­cessed with the direct, short direct, or bit direct ad­dressing modes. Accordingly, the ST6 in struction
set can use the indirect registers as any other reg­ister of the data space.

Short Direct Registers (V, W).

These two regis­ters are used to save a byte in short direct ad­dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be acc ess ed using the di­rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis­ters as any other register of the data space.

Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper­and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.

Figure 6. ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

2

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

12

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

100

13/70

ST62T08C/T09C ST62T10C/T20C /E20C

CPU REGISTERS

(Cont’d)

However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.

The PC value is incremented after reading the ad­dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the resul t is then
shifted back into the PC. The program counter can
be changed in the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- Reset PC= Reset vector

- RET & RETI instructionsPC= Pop (stack)

- Normal instructionPC= PC + 1

Flags (C, Z)

. The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of o peration:
Normal mode, Interrupt mod e and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pa ir (CN, ZN) is used
during Normal operation, another pair is used dur­ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNM I, ZN­MI).

The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable I nterrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NM I flags)
instead of the Normal flags. When the RETI in­struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou­tine). The flags are not cleared during context
switching and thus retain their status.

The Carry flag is set when a carry or a borrow oc­curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the valu e of
the bit tested in a bit test instruction; it also partici­pates in the rotate left instruction.

The Zero flag is set if the result of the last arithme­tic or logical operation was equal to zero; other­wise it is cleared.

Switching between the three sets of flags is per­formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is

automatically selected aft er the reset of the MCU,
the ST6 core uses at first the NMI flags.

Stack.

The ST6 CPU in cludes a true LIFO hard­ware stack which eliminates the need for a stack
pointer. The stack con sists of six sepa rate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter­rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each l evel is popped
back into the previous level. Since the acc umula­tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou­tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut­ed, and consequent ly the last return address wi ll
be lost. It will al so remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.

Figure 7. ST6 CP U Pr ogramming Mode

l

SHORT
DIRECT

ADDRESSING

MODE

VREGISTER

WREGISTER

PROGRAMCOUNTER

SIX LEVELS

STACK REGISTER

CZNORMAL FLAGS

INTERRUPT FLAGS

NMI FL AGS

INDEX

REGISTER

VA 000 42 3

b7

b7

b7

b7

b7

b0

b0

b0

b0

b0

b0b11

ACCUMULATOR

YREG.POINTER

XREG.POINTER

CZ

CZ

101

14/70

ST62T08C/T09C ST62T10C/T20C/E20 C

3 CLOCKS, RESET, INTER RUPTS AND POWER SAV ING MODES

3.1 CLOCK SYSTEM

The MCU f e atures a Main Oscillator w hic h c an be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a s uita­ble ceramic resonator, or with an external resistor
(R

NET

). In addition, a Low Frequency Auxiliary Os­cillator (LFAO) can be switched in for security rea­sons, to reduce power consumption, or to offer the
benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati­cally limits the internal cloc k frequency (f

INT

) as a

function of V

DD

, in order to guarantee correct oper­ation. The se functions a re illustrated in Figure 9,

Figure 10, Figure 11 and Figure 12.
Figure 8 illustrates var i o us po ssible oscilla t or co n -

figurations using an external crystal or ceramic res­onator, an external clock input, an external resistor
(R

NET

), or the lowest cost solution using only the

LFAO. C

L1

an CL2 should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.

The internal MCU clock frequency (f

INT

) is divided
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.

With an 8MHz oscillator frequency, the fastest ma­chine cycle is therefore 1.625µs.

A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An i nstruction may requi re
two, four, or five machine cycles for execution.

3.1.1 Main Oscillator

The oscillator configuration may be specified by se­lecting the appropriate option. When the CRYSTAL/
RESONATOR option is selected, it must be used with
a quartz crystal, a ceramic resonator or an external
signal provided on the OSCin pin. When the RC NET­WORK option is selected, the system clock is gen­erated by an external resistor.

The main oscillator can be turned off (when the
OSG ENABLED option is selec ted) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatical­ly started.

Figure 8. Oscillator Configurations

INTEGRATED CL OCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

in

OSC

out

C

L1n

C

L2

ST6xxx

CRYSTAL/RESONATO R CLOCK

CRYSTAL/RESONATOR option

OSC

in

OSC

out

ST6xxx

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

NC

OSC

in

OSC

out

ST6xxx

NC

OSC

in

OSC

out

R

NET

ST6xxx

RC NETWORK

RC NETW O RK option

NC

102

15/70

ST62T08C/T09C ST62T10C/T20C /E20C

CLOCK SYSTEM

(Cont’d)

Turning on the main oscillator is achieved by re­setting the OSCOFF bit of the A/D Converter Con­trol Register or by resetting the MCU. Restarting
the main osc illator im plies a dela y comp rising the
oscillator start up delay period plus the duration of
the software instruction at f

LFAO

clock frequency.

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used t o reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENA­BLED option is selected. In this case, it automati­cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid­ed, main osc illator switched off...).

User code, normal interrupts, WAIT and STOP in­structions, are processed as normal, at the re­duced f

LFAO

frequency. The A/D converter accura­cy is decreased, since the internal frequency is be­low 1MHz.

At power on, the Low Frequency Aux ilia ry Osc ill a­tor starts faster than the Main Oscillator. It there­fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is auto­matically switched off as soon as the main oscilla­tor sta r ts.

ADCR

Address: 0D1h — Read/Write

Bit 7-3, 1-0=

ADCR7-ADCR3, ADCR1-ADCR0

:

ADC Control Register

.

These bits are not used.

Bit 2 =

OSCOFF

. When low, this bit enables m ain
oscillator to run. The main oscillator is switc hed off
when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affords drastical­ly increased operational integrity in S T62xx dev ic­es. The OSG circuit provides three basic func­tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Freque ncy Auxiliary Os­cillator (L FA O), used to ens u re m in im u m process­ing in case of main oscillator failure, to offer re­duced power consumption or to provide a fixed fre­quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a f unction of
supply voltage, in order to ensure correct opera­tion even if the power supply should drop.

The OSG is enabled or disabled by choosing the
relevant OSG option. It may b e viewed as a filter
whose cross-over frequency is device dependent.

Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre­quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure

9). In all cases, when the OSG is active, the maxi-

mum internal clock frequency, f

INT

, is limited to

f

OSG

, which is supply voltage depende nt. This re-

lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency

Auxiliary Oscillator may be accessed. This oscilla­tor starts operating after the first missing edge of
the main oscillator (see Figure 10).

Over-frequency, at a given power supp ly level, is
seen by the OSG as spikes; it therefore filte rs out
some cycles in order that the internal clock fre­quency of the device is kept within the range the
particular device can stand (depen ding on V

DD

),

and below f

OSG

: the maximum authorised frequen-

cy with OSG enabled.

Note.

The OSG should be used wherever possible
as it provides maximum safet y. Care must be tak­en, however, as it ca n increase power consump­tion and reduce the maximum operating frequency
to f

OSG

.

70

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

0

103

16/70

ST62T08C/T09C ST62T10C/T20C/E20 C

CLOCK SYSTEM

(Cont’d)

Figure 9. OSG Filtering Principle

Figure 10. OSG Emergency Oscillator Principle

(1)

VR001932

(3)

(2)

(4)

(1)
(2)
(3)
(4)

Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin

Noise from OSCin
Resulting Internal Frequency

Main

VR001933

Internal

Emergency

Oscillator

Frequency

Oscillator

104

17/70

ST62T08C/T09C ST62T10C/T20C /E20C

CLOCK SYSTEM

(Cont’d)

Figure 11. Clock Circuit Block Diagram

Figure 12. Maximum Operating Frequency (f

MAX

) versus Supply Voltage (VDD)

Notes

:

1. In this area, operation is guaranteed at the
quartz crystal frequency.

2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar­anteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

area is guaranteed at the quartz crystal frequency.
When the OSG is enab led, access to this a rea is
prevented. The internal frequency is kept a f

OSG.

4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enab led, access to this a rea is
prevented. The internal frequency is kept at f

OSG.

MAIN

OSCILLATOR

OSG

LFAO

M

U
X

Core

:

13

:

12

:

1

TIMER 1

Watchdog

POR

f

INT

Main Oscillator off

1

2.5

3.644.555.56

8

7

6

5

4

3

2

Maximum FREQUENCY (MHz)

SUPPLY VOLTAGE (V

DD

)

FUNCTIONALITY IS NOT

3

4

3

2

1

f

OSG

f

OSG

Min

GUARANTEED

IN THIS AREA

VR01807

105

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ST62T08C/T09C ST62T10C/T20C/E20 C

3.2 RESETS

The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)

3.2.1 RESET Input

The RESET

pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET

pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET

pin are acceptable, provide d VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET

pin is held low.

If RESET

activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con­figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se­quence is executed following expiry of the internal
delay period.

If RESET

pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET

pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit cons ists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: al l I/O ports are c onfigured as
inputs with pull-up resistors an d no instruction is
executed. When the power supply voltage rises to
a sufficient level, the os cillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fully s tabil ize b efore execut ­ing the first instruction. The initialization sequence

is executed immediately following the internal de­lay.

To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi­cient level for the chosen frequency (see recom­mended operation) before the reset signal is re­leased. In addition, supply rising must start from
0V.

As a consequence, the POR does not allow to su­pervise static, slowly rising, or falling, or noisy
(present in g o s c illation) VDD supplies.

An external RC network connected to the RESET
pin, or the LVD reset can b e used instead to get
the best performances.

Figure 13. Reset and Interrupt Processing

INT LATCH CLEARED

NMI M ASK SET

RESET

( IF PRESENT )

SELECT

NMI MODE FLAGS

IS RESET STILL

PRESENT?

YES

PUT FFEH

ON ADDRESS BUS

FROM RESET LOCATIONS

FFE/FFF

NO

FETCH INSTRUCTION

LOAD PC

VA000427

106

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RESETS

(Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Wat chdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog regi ster is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongs t ot h­er things, resets the watchdog counter.

The MCU restarts just as though the Reset had
been generated by the RESET

pin, including the

built-in stabilisation delay period .

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-

ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.

As long as the supply voltage is below the refer­ence value, there is a internal and static RESET
command. The MCU can start only when the sup­ply voltage rises over the reference value. There­fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figur e 14, that represents a power­up, power-down sequence.

Note

: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De­tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.

Figure 14. LVD Reset on Power-on and Power-down (Brown -out)

3.2.5 Application Notes

No external resistor is requi red betw een V

DD

and

the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to
V

DD

must be avoided in order to ensure safe be­haviour of the internal reset sources (AND.Wired
structure).

RESET

RESET

VR02 106 A

time

V

Up

V

dn

V

DD

107

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ST62T08C/T09C ST62T10C/T20C/E20 C

RESETS

(Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat­ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the I n­terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in­itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how­ever, a pending interrupt is present, it will be serv­iced.

Figure 15. Reset and Interrupt Processing

Figure 16. Reset Block Diagram

RESET

RESET

VECTOR

JP

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION
ROUTINE

VA00181

V

DD

RESET

R

PU

R

ESD

1)

POWER

WATCHDOG RESET

CK

COUNTER

RESET

ST6
INTERNAL
RESET

f

OSC

RESET

ON RESET

LVD RESE T

VR02107A

AND. Wired

1) Resis t i ve E SD protect io n. Value not guaranteed.

108

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ST62T08C/T09C ST62T10C/T20C /E20C

RESETS

(Cont’d)

Table 5. Register Reset Status

Register Address(es) Status Comment

Oscillator Control Register
Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control

0DCh
0C0h to 0C1h
0C4h to 0C5h
0CCh to 0CDh
0C8h
0D4h

00h

f

INT

= f

OSC

; OSG disabled
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
TIMER disabled

X, Y, V, W, Register
Accumulator
Data RAM
Data ROM Window Register
A/D Result Register

080H TO 083H
0FFh
084h to 0BFh
0C9h
0D0h

Undefined As written if programmed

TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register

0D3h
0D2h
0D8h
0D1h

FFh
7Fh
FEh
40h

Max count loaded

A/D in Standby (When available)

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3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.

The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual­ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re­loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or­der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.

Watchdog behaviour is govern ed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6).

In the SOFTWARE option, t he Watchdog is d isa­bled until bit C of the DWDR register has been set.

When the Watchdog is disab led, low power Stop
mode is available. On ce activated, the Watchdog
cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog i s per­manently enabled. Since the oscillator will run con­tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc­tion, and the Watchdog continues to countdown.

However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then gov­erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in­struction is encountered when the NMI pin is high,
the Watchdog counter is f rozen and the CPU en­ters STOP mode.

When the MCU exits STOP mode (i.e. when an in­terrupt is generated), the Watchdog resumes its
activity.

Table 6. Recommended Option Choices

Functions Required Recommended Options

Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”

Stop Mode “SOFTWARE WATCHDOG”

Watchdog “HARDWARE WATCHDOG”

110

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DIGITAL WATCHDOG

(Cont’d)

The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca­tion 0D8h) which is described in greater detail in

Section 3.3.1 Digital Watchdog Register (DWDR).

This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 t o T5, and the SR bit
are all set to “1”, thus selecting the longest Watch­dog timer period. This time period can be set to t he
user’s requirements by setting the appropriate val­ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen­erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re­set.

It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as­sociated bits in the down counter: bit 7 of the
DWDR register corresponds , in f act, to T 0 a nd bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis­ter. The relationship between the DWDR regist er
bits and the physical implementation of the Watch­dog timer downcounter is illustrated in Figure 17.

Only the 6 most significant bits may be used to de­fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock c ycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri­ods ranging from 384µs to 24.576ms).

Figure 17. Watchdog Counter Control

WATCHDOG CONTROL REGISTER

D0

D1

D3

D4

D5

D6

D7

WATCHDOG COUNTER

C

SR

T5

T4

T3

T2

T1

D2

T0

OSC ÷12

RESET

VR02068A

÷

2

8

111

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ST62T08C/T09C ST62T10C/T20C/E20 C

DIGITAL WATCHDOG

(Cont’d)

3.3.1 Digital Watchdog Register (DWDR)

Address: 0D8h — Read/Write
Reset status: 1111 1110b

Bit 0 = C:

Watchdog Control bit

If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se­lected, the Watchdo g function is activated by set ­ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).

When C is kept low the counter can be used as a
7-bit timer.

This bit is cleared to “0” on Reset.
Bit 1 = SR:

Software Reset bit

This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of

the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 =

T5-T0

:

Downcounter bits

It should be noted that the register bits are re­versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.

These bits are set to “1” on Reset.

3.3.2 Application Notes

The Watchdog plays an i mportant support ing role
in the high noise immunity of ST62xx devices, and
should be used whe rever possible. W atchdog re­lated options should be selected on the basis of a
trade-off between application s ecurity and STOP
mode availabilit y.

When STOP m ode is not requ ired, hardware acti­vation without EXTERNAL STOP MODE CON­TROL should be preferred, as it provides maxi­mum security, especially during power-on.

When STOP mode i s required, hardware activa­tion and EXTERNAL STOP MODE CONTROL
should be chosen. NM I s hould be high by default,
to allow STOP mode to be entered when the MCU
is idle.

The NMI pin can be connected to an I/O line (see

Figure 18) to allow its state to be controlled by soft-

ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.

When software activation is selected and the
Watchdog is not activated, th e downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).

The software activation opt ion should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un­expectedly activated, the following instructions
should be executed within the first 27 instructions:

jrr 0, WD, #+3
ldi WD, 0FDH

70

T0 T1 T2 T3 T4 T5 SR C

112

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ST62T08C/T09C ST62T10C/T20C /E20C

DIGITAL WATCHDOG

(Cont’d)

These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.

In all modes, a minimum of 28 instructions are ex­ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 inst ructions
executed following a Reset (hardware activation).

It should be noted that when the GEN bit is low (in­terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.

Figure 18. A typical circuit maki ng use of the
EXERNAL STOP MODE CONTROL feature

Figure 19. Digital Watchdog Block Diagram

NMI

SWITCH

I/O

VR02002

RSFF

8

DATA BUS

VA00010

-2

-12

OSCILLATOR

RESET

WRITE

RESET

DB0

R

S

Q

DB1.7 SETLOAD

7

8

-2

SET

CLOCK

113

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ST62T08C/T09C ST62T10C/T20C/E20 C

3.4 INTERRUPTS

The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source i s asso­ciated with a specific Interrupt Vector which con­tains a Jump instruction to the associated interrupt
service routine. These vec tors are located i n Pro­gram space (see Table 7).

When an interrupt source generates an interrupt
request, and interrupt processing i s enabled, the
PC register is loaded with the address of the inter­rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv­ice routine, thus servicing the interrupt.

Interrupt sources are linked to events either on ex­ternal pins, or on chip peripherals. Several event s
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.

The Non Maskable Interrupt request has the high­est priority and can interrupt any interrupt rou tine
at any time; the other four interrupts cannot inter­rupt each other. If more than one interrupt request
is pending, these are processed by the proces sor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.

Table 7. Interrupt Vector Map

3.4.1 Interrupt request

All interrupt sources but the Non M askable Inter­rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in­cluding the Non Maskable Interrupt source, can re­start the MCU from STOP/WAIT modes.

Interrupt request from the Non M askable Interrupt
source #0 is latched by a flip flop which is automat-

ically reset by the core at the beginning of the non­maskable interrupt service routine.

Interrupt request from source #1 can be config­ured either as edge or level sensitive by setting ac­cordingly the LES bit of t he I nterrupt Option Regi s­ter (IOR).

Interrupt request from source #2 are always edge
sensitive. The e dge polarity can be configured by
setting accord ingly th e ESB bit of the Int erru pt Op­tion Register (IOR).

Interrupt request from sources #3 & # 4 are level
sensitive.

In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be­fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.

Storage of interrupt requests is not available in lev­el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu­tion.

At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not execut ed and the appropri­ate interrupt service routine is executed instead.

Table 8. Interrupt Option Register Description

Interrupt Source Priority Vector Address

Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h)
Interrupt source #2 3 (FF4h-FF5h)
Interrupt source #3 4 (FF2h-FF3h)
Interrupt source #4 5 (FF0h-FF1h)

GEN

SET Enable all interrupts
CLEARED Disable all interrupts

ESB

SET

Rising edge mode on inter­rupt source #2

CLEARED

Falling edge mode on inter­rupt source #2

LES

SET

Level-sensitive mode on in­terrupt source #1

CLEARED

Falling edge mode on inter­rupt source #1

OTHERS NOT USED

114

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ST62T08C/T09C ST62T10C/T20C /E20C

INTERRUPTS

(Cont’d)

3.4.2 Interrupt Procedure

The interrupt procedure is very similar to a call pro­cedure, indeed the user can consider the interrupt
as an asynchron ous call proc edure. As th is is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re­sult, the user should save all Data space registers
which may be used within th e interrupt routines.
There are separate sets of processor flags for nor­mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.

The following list summarizes the interrupt proce­dure:

MCU

– The interrupt is detected.
– The C and Z flags are replaced by the interrupt

flags (or by the NMI flags).

– The PC contents are stored in the first level of

the stack.

– The normal interrupt lines are inhibited (NMI still

active).
– The first internal latch is cleared.
– The associated interrupt vector is loaded in the PC.

WARNING:

In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and es pecially during the ex ecu­tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.

User

– User selected registers are saved within the in-

terrupt service routine (normally on a software
stack).

– The source of the interrupt is found by polling the

interrupt flags (if more than one source is associ-

ated with the same vector).
– The int e rrupt is serviced.
– Return from interrupt (RETI)

MCU

– Automatically the MCU switches back to the nor-

mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.

The interrupt routine usually begins by the identify­ing the device which generated the interrupt re­quest (by polling). The user should save the regis­ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe­cuted, the MCU returns to the main routine.

Figure 20. Interrupt Processing Flow Chart

INSTRUCTION

FETCH

INSTRUCTION

EXECUTE

INSTRUCTION

WAS

THE INSTRUCTION

A RETI

?

?

CLEAR

INTERRUPT MASK

SELECT

PROGRAM FLAGS

"POP"

THE STACKED PC

?

CHECK IF THERE IS

AN INTERRUPT REQUEST

AND INTERRUPT MASK

SELECT

INTERNAL MODE FLAG

PUSH THE

PC INTO THE STACK

LOAD PC FROM

INTERRUPT VECTOR

(FFC/FFD)

SET

INTERRUPT MASK

NO

NO

YES

IS THE CORE

ALREADY IN

NORMAL MODE?

VA000014

YES

NO

YES

115

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ST62T08C/T09C ST62T10C/T20C/E20 C

INTERRUPTS

(Cont’d)

3.4.3 Interrupt Option Register (IOR)

The Interrupt Option Register (IOR) is used to en­able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.

Address: 0C8h — Write Only
Reset status: 00h

Bit 7, Bits 3-0 =

Unused

.

Bit 6 =

LES:

Level/Edge Selection bit

.

When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.

Bit 5 =

ESB

:

Edge Selection bi t

.

The bit ESB selects the polarity of the interrupt
source #2.

Bit 4 =

GEN

:

Global Enable Interrupt

. When this bit
is set to one, all interrupts are e nabled . W hen this
bit is cleared to zero a ll the interrupts (excluding
NMI) are disabled.

When the GE N bit i s low, t he NM I interrupt is ac­tive but cannot cause a wake up from STOP/WAIT
modes.

This register is cleared on reset.

3.4.4 Interrupt Sources

Interrupt sources available on the ST62E20C/
T20C are summarized in the Tabl e 9 with associ­ated mask bit to enable/disable the interrupt re­quest.

Table 9. Interrupt Requests and Mask Bits

*Except ST62T08C

70

- LES ESB GEN - - - -

Peripheral Register

Address
Register

Mask bit Masked Interrupt Source

Interrupt

vector

GENERAL IOR C8h GEN

All Interrupts, excluding
NM

I
TIMER TSCR D4h ETI TMZ: TIMER Overflow Vector 3
A/D CONVERTER(*) ADCR D1h EAI EOC: End of Conversion Vector 4
Port PAn ORPA-DRPA C4h-CCh ORPAn-DRPAn PAn pin Vector 1
Port PBn ORPB-DRPB C5h-CDh ORPBn-DRPBn PBn pin Vector 2

116

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ST62T08C/T09C ST62T10C/T20C /E20C

INTERRUPTS

(Cont’d)

Figure 21. Interrupt Block Diagram

NMI

V

DD

FF

CLK Q

CLR

INT #0 - NMI (FFC,D)

I0 Star t

RESTART FROM
STOP/WAIT

INT #1 (FF6,7)

FF

CLK Q

CLR

PBE

0

MUX

1

PORT A

PORT B

Bits

INT #2 (FF4,5)

INT #3 (FF2,3)

TMZ

ETI

TIMER

FF

CLK Q

CLR

IOR REG. C8 H, bi t 5

I1 Start

I2 Start

IOR REG . C8H, bit 6

PBE

PBE

V

DD

FROM REGISTER

SINGLE BIT ENABLE

PORT A,B

PBE

INT #4 (FF0,1)

EAI

EOC

ADC(*)

GEN

VA0426T

(*)Except on ST62 T 08C

117

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ST62T08C/T09C ST62T10C/T20C/E20 C

3.5 POWER SAVING MODES

The WAIT and STOP modes have been imple­mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two powe r saving modes are
described in the following paragraphs.

In addition, the Low Frequency Auxiliary Oscillator
(LFAO) can be used instead of th e m ain oscil lator
to reduce power consumption in RUN and WAIT
modes.

3.5.1 WAIT Mode

The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The mi crocontroller
can be considered as being in a “s of twa re fro zen”
state where the core stops processing the pro­gram instructions, the RAM contents and peripher­al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac­tive.

WAIT mode can be used when the user wan ts to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa­bility of monitoring extern a l ev e nt s . Th e active os ­cillator (main oscillator or LFAO) is not stopped in
order to provide a clock signal to t he peripherals.
Timer counting may be enabled as well as the
Timer interrupt, before entering the WAIT mode:
this allows the WA IT mode to be exited when a
Timer interrupt occurs. The same applies to other
peripherals which use the clock signal.

If the power consumption has to be further re­duced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequency is lower. If requ ired, the
LFAO must be switched on before entering the
WAIT mode.

If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce­dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the s tate
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following para­graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be­cause the oscillator clock is still av ailable and no
stabilisation period is necessary.

3.5.2 STOP Mode

If the Watchdog is disabled, STOP mode is availa­ble. When in STOP mode, the M CU is placed in
the lowest power consumption mode. In this oper­ating mode, the microcontroller can be considered
as being “frozen”, no instruction is execut ed, the
oscillator is stopped, the RAM contents and pe­ripheral registers are preserved as long as the
power supply voltage is h igher than the RAM re­tention voltage, and the ST62xx core wa its for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.

If the STOP state is exited due to a Reset (by acti­vating the external p in) the MCU will enter a nor­mal reset procedure. Behaviour in response to in­terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener­ated.

This case will be described in the following para­graphs. The proces sor core generates a de lay a f­ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be­fore executing the first instruction.

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POWER SAVING MODE

(Cont’d)

3.5.3 Exit from WAIT and STOP Modes

The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter­rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in­terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.

Interrupts do not affect the oscillator selection,
consequently, when the LFAO is used, the user
program must manage oscillator selection as soon
as normal RUN mode is resumed.

3.5.3.1 Normal Mode

If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from S top
or Wait mode will occur as soon as an interrupt oc­curs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro­viding no other interrupts are pending.

3.5.3.2 Non Maskable Interrupt Mode

If the STOP or WAIT instruc tion has been execut­ed during execution of the non-maskab le interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is ex­ecuted, and the MCU remains in non-maskable in­terrupt mode, even if another interrupt has been
generated.

3.5.3.3 Normal Interrupt Mode

If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an in terrupt oc­curs. Nevertheless, two cases must be consid­ered:

– If the interrupt is a normal one, the interrupt rou-

tine in which the WAIT or STOP mode was en-

tered will b e c o mpleted, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou­tine pending interrupts will be serviced in accord­ance with their priority.

– In the event of a non-maskable interrupt, the

non-maskable interrupt service routine is proc­essed first, then the routine in which t he WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal in­terrupt mode.

Notes:

To achieve the lowest power consumpti on during
RUN or WAIT modes, the user program must take
care of:

– configuring unused I/Os as inputs without pull-up

(these should be externally tied to well defined
logic levels);

– placing all peripherals in their power down

modes before entering STOP mode;

– selecting the Low Frequency Auxiliary Oscillator

(provided this runs at a lower frequency than the
main osc illat o r ).

When the hardware activated Watchdog i s sel ect­ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc­tion will be ex e c ut e d in its pla c e.

If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in­terrupt, it will stop it generating a wake-up signal.

The WAIT and STOP instructions are not execut­ed if an enabled interrupt request is pending.

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4 ON-CHIP PER IPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which m ay
be individually programmed as any of the following
input or output configurations:

– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
– Push- pull outp ut
– Open drain output
The lines are organised as bytewise Ports.
Each port is associated with 3 registers in Data

space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat­ed with the PA0 line of Port A).

The DATA registers (DRx), are us ed to read the
voltage level values of the lines which have been
configured as inputs, or to wri te the logic value of
the signal to be output on the l ines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but t hey can

be also written by user software, in conjunction
with the related option registers, to select the dif­ferent input mode options.

Single-bit operations o n I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct­ly affect the Port data register ca using an unde­sired change of the input configuration.

The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.

The Option regist ers (O Rx) are us ed t o se lect t he
different port options available both in input and in
output mode.

All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg­isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.

Figure 22. I/O Port Block Diagram

V

DD

RESET

SIN CONTRO LS

S

OUT

SHIFT

REGISTER

DATA

DATA

DIRECTION

REGISTER

REGISTER

OPTION

REGISTER

INPUT/OUTPUT

TO INTERRUPT

V

DD

TO ADC

VA00413

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I/O PO R T S

(Cont’d)

4.1.1 Operating Modes

Each pin may be individually programmed as input
or output with various configurations.

This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and O ption reg­isters (OR). Table 10 illustrates the various port
configurations which can be selected by user soft­ware.

4.1.1.1 Input Options

Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped­ance state.

4.1.1.2 Interrupt Options

All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter­rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de­scribed in the Interrupt Chapter for each port.

4.1.1.3 Analog Input Options

Some pins can be configured as analog inputs by
programming the OR and DR registers according­ly. These analog inputs are c onnected to the on­chip 8-bit Analog to Digital Converter.

ONLY ONE

pin should be programmed as an analog input at
any time, since by selecting m ore than one input
simultaneously their pins will be effectively short­ed.

Table 10. I/O Port Option Selection

Note:

X = Don’t care

DDR OR DR Mode Option

0 0 0 Input With pull-u p, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)

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I/O PO R T S

(Cont’d)

4.1.2 Safe I/O State Switching Sequence

Switching the I/O ports from one st ate to another
should be done in a se quence whi c h ensures that
no unwanted side effects can occur. The recom­mended safe transitions are illustrated in Figure

23. All other transitions are potentially risky and

should be avoided when changing the I/O operat­ing mode, as it is most likely that undesirable side­effects will be experienced, such as spurious inter­rupt generation or two pins shorted together by the
analog multiplexer.

Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire reg ister. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis­ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and

outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RA M copy, after whi ch the whole
copy register can be written to the port data regis­ter:

SET bit, datacopy
LD a, datacopy
LD DRA, a

Warning:

Care must also be taken to not use in­structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the de vice. Unavailable bits must be
masked by software (AND instruction).

The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con­sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.

The user must ta ke ca re n o t to switch output s with
heavy loads during the con version of one of the
analog inputs in order to avoid any disturbance to
the conversion.

Figure 23. Diagram showing Safe I/O State Transitions

Note *.

xxx = DDR, OR, DR Bits respectively

Interrupt
pull-up

Output
Open Drain

Output
Push-pull

Input
pull-up (Reset
state)

Input

Analog

Output

Open Drain

Output

Push-pull

Input

010*

000

100

110

011

001

101

111

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I/O PO R T S

(Cont’d)

4.1.3 I/O Port Option Registers
ORA/B (CCh PA, CDh PB)

Read/Write

Bit 7-0 =

Px7 - Px0:

Port A and B Option Register

bits.

4.1.4 I/O Port Data Direction Registers
DDRA/B (C4h PA, C5h PB)

Read/Write

Bit 7-0 = Px7 - Px0:

Port A and B Data Direction

Registers bits.

4.1.5 I/O Port Data Registers
DRA/B (C0h PA, C1h PB)

Read/Write

Bit 7-0 =

Px7 - Px0:

Port A and B Data Registers

bits.

Note:

X = Don’t care

70

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

70

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

70

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0

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ST62T08C/T09C ST62T10C/T20C/E20 C

I/O PO R T S

(Cont’d)

Table 11. I/O Port Option Selections

Note 1

. Provided the correct configuration has been selected.

MODE AVAILABLE ON

(1)

SCHEMATIC

Input

PA0-PA3
PB0-PB7

Input

with pull up

PA0-PA3
PB0-PB7

Input

with pull up

with interrupt

PA0-PA3
PB0-PB7

Analog Input

PB0-PB3
(ST62T10C,T20C,E20C)

PB4-PB7
(All except ST62T08C)

Open drain output

5mA

Open drain output

20mA

PB0-PB7

PA0-PA3

Push-pull output

5mA

Push-pull output

20mA

PB0-PB7

PA0-PA3

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

Data out

ADC

Data out

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4.2 TIMER

The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program­mable prescaler, giving a maximum count of 2

15

.
The peripheral may be configured in three different
operating modes.

Figure 24 shows the Timer Block Diagram. The

external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the state of
the 7-bit prescaler can be read in the PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.

The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit pre scaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena­ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.

The prescaler input can be the internal frequency
f

INT

divided by 12 or an external clock applied to
the TIMER pin. The prescale r decrements on the
rising edge. Depending on t he division factor pro­grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul­tiplexed to different sources. For division factor 1,
the clock input of the prescaler is also that of timer/
counter; for factor 2, bit 0 of the prescaler register
is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres­caler input clock. For factor 4, bit 1 of the PS C is
connected to the clock input o f TCR, and so f orth.
The prescaler initialize bit, PSI, in the TSCR regis­ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If it is cleared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value bet ween 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg­ister.

Figure 25 illustrates the Timer’s working principle.

Figure 24. Timer Block Diagram

DATABUS 8

8

8

8

8-BIT

COUNTER

6
5
4
3

2
1
0

PSC

STATUS/CONTROL

REGISTER

b7 b6 b5 b4 b3 b 2

b1

b0

TMZ ETI TOUT

DOUT

PSI

PS2

PS1 PS0

SELECT
1 OF 7

3

LATCH

SYNCHRONIZATION

LOGIC

TIMER

INTERRUPT

LINE

VA00009

:12

f

OSC

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TIMER

(Cont’d)

4.2.1 Timer Operating Modes

There are three operating modes, which are se­lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f

INT

÷ 12 or TIMER pin signal), and to

the output mode.

4.2.1.1 Gated Mode

(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the

Timer clock input (f

INT

÷ 12), but ONLY when the
signal on the TIMER pin is held high (allowing
pulse width measurem ent). T his mod e is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.

4.2.1.2 Event Counter Mode

(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of

the prescaler which is decremented o n the rising
edge.

4.2.1.3 Output Mode

(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,

hence the Timer prescaler is clocked by the pres­caler clock input (f

INT

÷ 12).

The user can select the des ired pres caler di vision
ratio through the PS2, PS1, P S0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested u nder program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the TSCR and t rans­fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.

Table 12. Tim er Operating M od es

4.2.2 Timer Interrupt

When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is g enerated a s described in the
Interrupt Chapter. When the coun ter decrements
to zero, the TMZ bit in the TSCR register is set to
one.

Figure 25. Tim e r Working Pri nci pl e

TOUT DOUT Timer Pin Timer Function

0 0 Input Event Counter
0 1 Input Gated Input
1 0 Output Output “0”
1 1 Output Output “1”

BIT0 BIT1 BIT2

BIT3 BIT6BIT5BIT4

CLOCK

7-BIT PRESCALER

8-1 MULTIPLEXER

8-BIT COUNTER

BIT0 BIT1

BIT2

BIT3 BIT4 BIT5

BIT6

BIT7

10

2

34

5

67

PS0
PS1
PS2

VA00186

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TIMER

(Cont’d)

4.2.3 Application Notes

The user can select the presence of an on-chip
pull-up on the TIMER pin as option.

TMZ is set when the counter reaches zero; howev­er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde­sired interrupts when leaving the interrup t service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is l oad­ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.

If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement). When TM Z is high, the latch is t rans­parent and DOUT is copied to the timer pin. When
TMZ goes low, DOUT is latched.

A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit i s not set until the 8-bit c ounter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.

4.2.4 Timer Registers
Timer Status Control Register (TSCR)

Address: 0D4h — Read/Write

Bit 7 =

TMZ

:

Timer Ze r o bit

A low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by user sof tware bef ore starting a new
count.

Bit 6 =

ETI

:

Enable Timer Interrupt

When set, enables the timer interrupt request
(vector #3). If ETI=0 the timer interrupt is di sabled.
If ETI=1 and TMZ=1 an interrupt request is gener­ated.

Bit 5 =

TOUT

:

Timers Output Control

When low, this bit selects the input mode for the
TIMER pin. When high the out put mode is select ­ed.

Bit 4 =

DOUT

:

Data Output

Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).

Bit 3 =

PSI

:

Prescaler Initialize Bit

Used to initialize the prescaler and inhibit its count­ing. When PSI=“0” the presc aler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal­er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run­ning.

Bit 2, 1, 0 =

PS2, PS1, PS0

:

Prescaler Mux. Se-

lect.

These bits select the division ratio of the pres-

caler register.

Table 13. Prescaler Division Factors

Timer Counter Regi ster TCR

Address: 0D3h — Read/Write

Bit 7-0 =

D7-D0

:

Counter Bits.

Prescaler Register PSC

Address: 0D2h — Read/Write

Bit 7 = D7: Always read as "0".
Bit 6-0 =

D6-D0

: Prescaler Bits.

70

TMZ ETI TOUT DOUT PSI PS2 PS1 PS0

PS2 PS1 PS0 Divided by

0 0 0 1
0 0 1 2
0 1 0 4
0118
10016
10132
11064
111128

70

D7 D6 D5 D4 D3 D2 D1 D0

70

D7 D6 D5 D4 D3 D2 D1 D0

127

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4.3 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8 -b it ana log to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend­ent), offering 8-bit resolution with a typical conver­sion time of 70us (at an oscillator clock frequency
of 8MHz).

The ADC converts the inpu t voltage by a process
of successive approximations, using a clock fre­quency derived from the os cillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de­creased.

Selection of the input pi n is done by configuring
the related I/O line as an analog input via the Op­tion and Data registers (refer to I/O ports descrip­tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selecte d as an analog input si­multaneously, to avoid device malfunction.

The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis­ter, ADCR, used to program the ADC functions.

A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto­matically clears (resets to “0”) the End Of Conver­sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and t hat the data
in the ADC data conversion register is val id. E ach
conversion has to be separately initiated by writing
to the STA bit.

The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com­pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log­ical “0”.

The A/D converter features a maskable interrupt
associated with the end of conversion. This inter­rupt is associated with interrupt vector #4 and oc­curs when the EOC bit is set (i.e. when a c onver­sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.

The power consumption of th e device can be re­duced by turning off the ADC peripheral. Thi s is
done by setting the PDS bit in the ADC control reg­ister to “0”. If PDS=“1”, the A/D is powered and en­abled for conversion. This bit mus t be set at least
one instruction before the beginning of the conver-

sion to allow stabilisation of the A/D converter.
This action is also needed before ente ring WAIT
mode, since the A/D com parator is not automati­cally disabled in WAIT mode.

During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).

Figure 26. ADC Block Diagram

4.3.1 Application Notes

The A/D converter doe s not f eature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con­version cycle. Voltage variation should not exceed
±1/2 LSB for the optim um con ve rsion acc uracy . A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con­version.

When selected as an analog channel, the input pin
is internally connected to a cap acitor C

ad

of typi­cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver­sion. In the worst case, conversion starts on e in­struction (6.5 µs) after the channel has been se­lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us­ing the following formula:

6.5µs = 9 x C

ad

x ASI

(capacitor charged to over 99.9%), i.e. 30 kΩ in­cluding a 50% guardband. ASI can be higher if C

ad

has been charged for a longer period by adding in­structions before the start of conversion (adding
more than 26 CPU cycles is pointless).

CONTRO L REGIS T ER

CONVERTER

VA00418

RESULT REGISTER

RESET

INTERRUPT
CLOCK

AV
AV

DD

Ain

8

CORE

CONTROL SI GNA LS

SS

8

CORE

128

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A/D CONVERTER

(Cont’d)

Since the ADC is on the same chip as the micro­processor, the user should not switch heavily load­ed output signals during conversion, if high preci­sion is required. Such switching will affect the sup­ply voltages used as analog references.

The accuracy of the conversion depends on the
quality of the power supplies (V

DD

and VSS). The
user must take special care to ensure a well regu­lated reference voltage is present on the V

DD

and

V

SS

pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the V

DD

pin.
The converter resolution is given by::

The Input voltage (Ain) which is to be converted
must be constant for 1µs be fore conversion and
remain constant during conversion.

Conversion resolution can be improved if the pow­er supply voltage (V

DD

) to the microcontroller is

lowered.
In order to optimise conversion resolution, the user

can configure the microcon troller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch­ing. Nevertheless, th e WAIT instruction s hould be
executed as soon as possible after the beg inning
of the conversion, because execution of the WAIT
instruction may cause a small variation of the V

DD

voltage. The negative effect of this variation is m in­imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.

The best configuration, from an accuracy stand­point, is WAIT mode with the Timer stopped. In­deed, only the AD C peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking

up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.

A/D Converter Control Register (ADCR)

Address: 0D1h — Read/Write

Bit 7 =

EAI

:

Enable A/D Interrupt.

If this b it is se t to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.

Bit 6 =

EOC

:

End of conversio n. Read Only

. This
read only bit indicates when a conversion has
been completed. Thi s bit is automatically reset t o
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.

Bit 5 =

STA

: Start of Conversion. Write Only

. Writ­ing a “1” to this bit will start a conversion on the se­lected channel and aut omatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.

Bit 4 =

PDS

: Power Down Selection.

This bit acti­vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down m ode (id le
mode).

Bit 3-0 =

D3-D0.

Not used

A/D Converter Data Register (ADR)

Address: 0D0h — Read only

Bit 7-0 =

D7-D0

: 8 Bit A/D Conversion Result.

V

DDVSS

–

256

--------------------------- -

70

EAI EOC STA PDS D3 D2 D1 D0

70

D7 D6 D5 D4 D3 D2 D1 D0

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5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum ; in short,
to provide byte efficient programming capability.
The ST6 core has t he ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depe nding on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RE S instruc tion is pr ocessed.

5.2 ADDRESSING MODES

The ST6 core offers nine addressing modes,
which are described in the follo wing paragraphs.
Three different address spaces are available: Pro­gram space, Data space, and Stack space. Pro­gram space contains t he inst ructions whi ch are to
be executed, plus the data for immediate mode in­structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con­stants). Stack spac e contai n s six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.

Immediate

. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme­diate addressing mode is used to access con­stants which do not change during program execu­tion (e.g., a constant used to initialize a loop coun­ter).

Direct

. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di­rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.

Short D ir ect

. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op­code. Short direct addressing is a subset of the di­rect addressing mode. (Note that 80h and 81h are
also indirect registers).

Extende d

. In the extended add ressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant

bits of the opcode with the byte following t he op­code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.

An extended addressing m ode instruction is two­byte long.

Program Counter Relative

. The relative address­ing mode is only used in conditional branch in­structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of

-15 to +16 locations around the address of the rel­ative instruction. If the condition is not true, the in­struction which follows the relative instruction is
executed. The relative addressing mode instruc­tion is one-byte long. The opcode is o btained in
adding the three most significant bits which char­acterize the kind of the test, one bit which de ter­mines whether the branch is a forward (wh en it is

0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub­tracted to the ad dress of t he rel ative instruc tion t o
obtain the address of the branch.

Bit Direct

. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad­dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.

Bit Test & Branch

. The bit test and branch ad­dressing mode is a combination of direct address­ing and relative addressing. The bit test and
branch instruction is three-by te long. The bit iden­tification and the tested condition are include d in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro­gram space. The third byte is t he jump displace­ment, which is in the range of -12 7 to +128. T his
displacement can be determined using a label,
which is converted by the assembler.

Indirect

. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in­direct registers, X or Y (80h,81h). The indirect reg­ister is selected by the bit 4 of the opcode. A regis­ter indirect instruction is one byte long.

Inherent

. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.

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5.3 INSTRUCTION SET

The ST6 core offers a set o f 40 basic instruc tions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di­vided into six different ty pes: load/store, arithme­tic/logic, conditional branch, control instructions,
jump/call, and bit manipu lat ion. T he f ollowing par­agraphs describe the different types.

All the instructions belonging to a given type are
presented in individual tables.

Load & Store

. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.

For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.

Table 14. Load & Store Instructions

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register

∆

. Affected

* . Not Affected

Instruction Addressing Mode Bytes Cycles

Flags

ZC

LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *

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INSTRUCTION SET

(Cont’d)

Arithmetic and Logic

. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc­tions one operand is always the acc umulator while
the other can be either a data space memory con-

tent or an im med iate val ue i n rel ation with the ad­dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad­dresses. In COM, RLC, SLA the operand is always
the accumulator.

Table 15. Arithmetic & Logic Instructions

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct Reg i st ersD. Affect ed
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data spac e register

Instruction Addressing Mode Bytes Cycles

Flags

ZC

ADD A, (X) Indirect 1 4 ∆∆
ADD A, (Y) Indirect 1 4 ∆∆
ADD A, rr Direct 2 4 ∆∆
ADDI A, #N Immediate 2 4 ∆∆
AND A, (X) Indirect 1 4 ∆∆
AND A, (Y) Indirect 1 4 ∆∆
AND A, rr Direct 2 4 ∆∆
ANDI A, #N Immediate 2 4 ∆∆
CLR A Short Direct 2 4 ∆∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆∆
CP A, (X) Indirect 1 4 ∆∆
CP A, (Y) Indirect 1 4 ∆∆
CP A, rr Direct 2 4 ∆∆
CPI A, #N Immediate 2 4 ∆∆
DEC X Short Direct 1 4 ∆ *
DEC Y Short Direct 1 4 ∆ *
DEC V Short Direct 1 4 ∆ *
DEC W Short Direct 1 4 ∆ *
DEC A Direct 2 4 ∆ *
DEC rr Direct 2 4 ∆ *
DEC (X) Indirect 1 4 ∆ *
DEC (Y) Indirect 1 4 ∆ *
INC X Short Direct 1 4 ∆ *
INC Y Short Direct 1 4 ∆ *
INC V Short Direct 1 4 ∆ *
INC W Short Direct 1 4 ∆ *
INC A Direct 2 4 ∆ *
INC rr Direct 2 4 ∆ *
INC (X) Indirect 1 4 ∆ *
INC (Y) Indirect 1 4 ∆ *
RLC A Inherent 1 4 ∆∆
SLA A Inherent 2 4 ∆∆
SUB A, (X) Indirect 1 4 ∆∆
SUB A, (Y) Indirect 1 4 ∆∆
SUB A, rr Direct 2 4 ∆∆
SUBI A, #N Immediate 2 4 ∆∆

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INSTRUCTION SET

(Cont’d)

Conditional Branch

. The branch instructions
achieve a branch in the program when the select­ed condition is met.

Bit Manipulation Instructions

. These instruc­tions can handle any bit in data space memory.
One group either sets or clears. The ot her group
(see Conditional Branch) performs the bit test
branch operations.

Control Instructions

. The control instructions
control the MCU operations during program exe­cution.

Jump and Call.

These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.

Table 16. Conditional Branch Instructions

Notes

:

b. 3 -bit address rr. Data space register
e. 5 bi t s i gned displacem ent in the range -15 to +16 <F 128M>

∆

. Affected. The tested bit is shifted into carry.

ee. 8 bit s i gned displacem ent in the range -126 to +129 * . Not Affect ed

Table 17. Bit Manipulation Instructions

Notes:

b. 3-bit address; * . Not<M> Affected
rr. Data space register;

Table 18. Control Instructions

Notes:

1. This instruction is deact i vated<N>an d a WAIT is auto m atically executed instead of a STOP if the watchdog function is selected.

∆

. Affected

*. Not Affected

Table 19. Jump & Call Instructions

Notes:

abc. 12-bit address;
* . Not Affected

Instruction Branch If Bytes Cycles

Flags

ZC

JRC e C = 1 1 2 * *
JRNC e C = 0 1 2 * *
JRZ e Z = 1 1 2 * *
JRNZ e Z = 0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆

Instruction Addressing Mode Bytes Cycles

Flags

ZC

SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *

Instruction Addressing Mode Bytes Cycles

Flags

ZC

NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *

Instruction

Addressing Mode Bytes Cycles

Flags

ZC

CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *

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Opcode Map Summary.

The following table contains an opcode map for the instructions used by the ST6

LOW

0

0000

1

0001

2

0010

3

0011

4

0100

5

0101

6

0110

7

0111

LOW

HI HI

0

0000

2 JRNZ 4 CALL 2 J RNC 5 JRR 2 JRZ 2 JRC 4 LD

0

0000

e abc e b0,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

1

0001

2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 LDI

1

0001

e abc e b0,rr,ee e x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

2

0010

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 CP

2

0010

e abc e b4,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

3

0011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI

3

0011

e abc e b4,rr,ee e a,x e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

4

0100

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 ADD

4

0100

e abc e b2,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

5

0101

2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 ADDI

5

0101

e abc e b2,rr,ee e y e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

6

0110

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 INC

6

0110

e abc e b6,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

7

0111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

7

0111

e abc e b6,rr,ee e a,y e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

8

1000

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 LD

8

1000

e abc e b1,rr,ee e # e (x),a

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

9

1001

2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC

9

1001

e abc e b1,rr,ee e v e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

A

1010

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 AND

A

1010

e abc e b5,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

B

1011

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI

B

1011

e abc e b5,rr,ee e a,v e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

C

1100

2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB

C

1100

e abc e b3,rr,ee e # e a,(x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

D

1101

2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 SUBI

D

1101

e abc e b3,rr,ee e w e a,nn

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm

E

1110

2 JRNZ 4 CALL 2 JRN C 5 JRR 2 JRZ 2 JRC 4 DEC

E

1110

e abc e b7,rr,ee e # e (x)

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind

F

1111

2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC

F

1111

e abc e b7,rr,ee e a,w e #

1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates I l l egal Instr u ctions
sd Short Di rect e 5 Bit Dis pl acement
imm Immedia te b 3 Bit Address
inh Inherent rr 1byte dataspace address
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
bt Bit Test ee 8 bit Displa c e m ent
pcr Program Counter Relative
ind Indirect

2

JRC

e

1prc

Mnemonic

Addressing Mode

Bytes

Cycle
Operand

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Opcode Map Summary

(Continued)

LOW

8

1000

9

1001

A

1010

B

1011

C

1100

D

1101

E

1110

F

1111

LOW

HI HI

0

0000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD

0

0000

e abc e b0,rr e rr,nn e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind

1

0001

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

1

0001

e abc e b0,rr e x e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

2

0010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP

2

0010

e abc e b4,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

3

0011

2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 CP

3

0011

e abc e b4,rr e x,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

4

0100

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD

4

0100

e abc e b2,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

5

0101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD

5

0101

e abc e b2,rr e y e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

6

0110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC

6

0110

e abc e b6,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

7

0111

2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 INC

7

0111

e abc e b6,rr e y,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

8

1000

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD

8

1000

e abc e b1,rr e # e (y),a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind

9

1001

2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD

9

1001

e abc e b1,rr e v e rr,a

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

A

1010

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND

A

1010

e abc e b5,rr e a e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

B

1011

2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 AND

B

1011

e abc e b5,rr e v,a e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

C

1100

2 JRNZ4 JP2 JRNC4 RES2 JRZ2 RET2 JRC4 SUB

C

1100

e abc e b3,rr e e a,(y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

D

1101

2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB

D

1101

e abc e b3,rr e w e a,rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

E

1110

2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC

E

1110

e abc e b7,rr e e (y)

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind

F

1111

2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 DEC

F

1111

e abc e b7,rr e w,a e rr

1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates I l l egal Instr u ctions
sd Short Di rect e 5 Bit Dis pl acement
imm Immedia te b 3 Bit Address
inh Inherent rr 1byte dataspace address
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
bt Bit Test ee 8 bit Displa c e m ent
pcr Program Counter Relative
ind Indirect

2

JRC

e

1prc

Mnemonic

Addressing Mode

Bytes

Cycle
Operand

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6 ELECTRIC AL CHARACTERI STICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs
against damage due to high static voltages , how­ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.

For proper operation it is recommended that V

I

and VO be higher than VSS and lower than VDD.
Reliability is enhanc ed if unused inputs are con­nected to an appropriate logic vol tage level (V

DD

or VSS).

Power Considerations

.The average chip-junc­tion temperature, Tj, in Celsius can be obtained
from:

Tj=TA + PD x RthJA

Where:TA = Ambient Temperature.

RthJA =Package thermal resistance (junc-

tion-to ambient).
PD = Pint + Pport.
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined

by the user).

Notes:

- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to max i mum rating conditions f or extended periods may
affect device reliability.

- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.

Symbol Parameter Value Unit

V

DD

Supply Voltage -0.3 to 7.0 V

V

I

Input Voltage VSS - 0.3 to VDD + 0.3

(1)

V

V

O

Output Voltage VSS - 0.3 to VDD + 0.3

(1)

V

IV

DD

Total Current into VDD (source) 80 mA

IV

SS

Total Current out of VSS (sink) 100 mA

Tj Junction Temperature 150 °C

T

STG

Storage Temperature -60 to 150 °C

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6.2 RECOMMENDED OPERATING CONDITIONS

Notes

:

1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the

A/D conversion. For a -1m A i nj ection, a max i mum 10 KΩ is recomm ended.

2.An oscillator frequency above 1MHz is recommended for reliable A/D results

Figure 27. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

T

A

Operating Temperature

6 Suffix Version
1 Suffix Version
3 Suffix Version

-40
0

-40

85
70

125

°C

V

DD

Operating Supply Voltage

f

OSC =

4MHz, 1 & 6 Suffix

f

OSC =

4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix

3.0

3.0

3.6

4.5

6.0

6.0

6.0

6.0

V

f

OSC

Oscillator Frequency

2)

V

DD

= 3.0V, 1 & 6 Suffix

V

DD

= 3.0V , 3 Suffix

V

DD

= 3.6V , 1 & 6 Suffix

V

DD

= 3.6V , 3 Suffix

0
0
0
0

4.0

4.0

8.0

4.0

MHz

I

INJ+

Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA

I

INJ-

Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA

8

7

6

5

4

3

2

1

2.5 3 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

Maximum FREQUENCY (MHz)

FUNCTIONALITY IS NOT

GUARANTEED IN

THIS AREA

3 Suffix ver sion

1 & 6 Suffix version

3.6

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6.3 DC ELECTRICAL CHARACTERISTICS

(T

A

= -40 to +125°C unless otherwise specified)

Notes:

(1) Hysteresis voltage between switching levels
(2) All peri pherals runni ng
(3) All peri pherals in s tand-by

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

V

IL

Input Low Level Voltage
All Input pins

V

DD

x 0.3 V

V

IH

Input High Level Voltage
All Input pins

V

DD

x 0.7 V

V

Hys

Hysteresis Voltage

(1)

All Input pins

V

DD

= 5V

V

DD

= 3V

0.2

0.2

V

V

up

LVD Threshold in power-on 4.1 4.3

V

dn

L VD threshold in powerdown 3.5 3.8

V

OL

Low Level Output Voltage
All Output pins

VDD= 5.0V; I

OL

= +10µA

V

DD

= 5.0V; I

OL

= + 3mA

0.1

0.8
V

Low Level Output Voltage
20 mA Sink I/O pins

V

DD

= 5.0V; I

OL

= +10µA

V

DD

= 5.0V; I

OL

= +7mA

V

DD

= 5.0V; IOL = +15mA

0.1

0.8

1.3

V

OH

High Level Output Voltage
All Output pins

VDD= 5.0V; I

OH

= -10µA

V

DD

= 5.0V; I

OH

= -3.0mA

4.9

3.5

V

R

PU

Pull-up Resistance

All Input pins 40 100 350

ΚΩ

RESET pin 150 350 900

I

IL

I

IH

Input Leakage Current
All Input pins but RESET

VIN = VSS (No Pull-Up configured)
V

IN

= V

DD

0.1 1.0
µA

Input Leakage Current
RESET pin

VIN = V

SS

VIN = V

DD

-8 -16 -30
10

I

DD

Supply Current in RESET
Mode

V

RESET=VSS

f

OSC

=8MHz

3.5 mA

Supply Current in
RUN Mode

(2)

VDD=5.0V f

INT

=8MHz 3.5 mA

Supply Current in WAIT
Mode

(3)

VDD=5.0V f

INT

=8MHz 1.5 mA

Supply Current in STOP
Mode, with LVD disabled

(3)

I

LOAD

=0mA

V

DD

=5.0V

20 µA

Supply Current in STOP
Mode, with LVD enabled

(3)

I

LOAD

=0mA

V

DD

=5.0V

500

Retention EPROM Data Retention T

A

= 55°C 10 years

138

51/70

ST62T08C/T09C ST62T10C/T20C /E20C

DC ELECTRICAL CHARACTERISTICS

(Cont’d)

(T

A

= -40 to +85°C unless otherwise specified))

Note:
(*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

(T

A

= -40 to +125°C unless otherwise specified)

Notes:

1. Period for which V

DD

has to be connected at 0V to all ow internal Reset funct i on at next power -up.

2 An oscillator frequency above 1MHz is recommended for reliable A/D results.

3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

V

up

LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V

V

dn

L VD threshold in powerdown 3.6 3.8 Vup -50 mV V

V

OL

Low Level Output Voltage
All Output pins

V

DD

= 5.0V; I

OL

= +10µA

V

DD

= 5.0V; I

OL

= + 5mA

V

DD

= 5.0V; I

OL

= + 10mAv

0.1

0.8

1.2
V

Low Level Output Voltage
20 mA Sink I/O pins

V

DD

= 5.0V; I

OL

= +10µA

V

DD

= 5.0V; I

OL

= +10mA

V

DD

= 5.0V; I

OL

= +20mA

V

DD

= 5.0V; IOL = +30mA

0.1

0.8

1.3

2.0

V

OH

High Level Output Voltage
All Output pins

VDD= 5.0V; I

OH

= -10µA

V

DD

= 5.0V; I

OH

= -5.0mA

4.9

3.5

V

I

DD

Supply Current in STOP
Mode, with LVD disabled

(*)

I

LOAD

=0mA

V

DD

=5.0V

10 µA

Symbol

Parameter Test Conditions

Value

Unit

Min. Typ. Max.

t

REC

Supply Recovery Time

(1)

100 ms

f

LFAO

Internal frequency with LFAO active 200 400 800 kHz

f

OSG

Internal Frequency with OSG
enabled

2)

V

DD

= 3V

V

DD

= 3.6V

V

DD

= 4.5V

2
2
4

f

OSC

MHz

f

RC

Internal frequency with RC oscillator
and OSG disabled

2) 3)

VDD=5.0V
R=47kΩ
R=100kΩ
R=470kΩ

4

2.7

800

5

3.2

850

5.8

3.5

900

MHz
MHz

kHz

C

IN

Input Capacitance All Inputs Pins 10 pF

C

OUT

Output Capacitance All Outputs Pins 10 pF

139

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ST62T08C/T09C ST62T10C/T20C/E20 C

6.5 A/D CONVERTER CHARACTERISTICS

(T

A

= -40 to +125°C unless otherwise specified)

Notes

:

1. Noise at VDD , VSS <10 mV

2. With oscillator frequencies l ess than 1MH z, th e A/D Convert er accuracy is decreased .

6.6 TIMER CHARACTERISTICS

(T

A

= -40 to +125°C unless otherwise specified)

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

Res Resolution 8 Bit

A

TOT

Total Accuracy

(1) (2)

f

OSC

> 1.2MHz

f

OSC

> 32kHz

±2
±4

LSB

t

C

Conversion Time

f

OSC

= 8MHz (TA < 85°C)

f

OSC

= 4 MHz

70

140

µs

ZIR Zero Input Reading

Conversion result when
V

IN

= V

SS

00 Hex

FSR Full Scale Reading

Conversion result when
V

IN

= V

DD

FF Hex

AD

I

Analog Input Current Durin g
Conversion

V

DD

= 4.5V 1.0 µA

AC

IN

Analog Input Capacitanc e 2 5 pF

Symbol Parameter Test Conditions

Value

Unit

Min. Typ. Max.

f

IN

Input Frequency on TIMER Pin MHz

t

W

Pulse Width at TIMER Pin

V

DD

= 3.0V

V

DD

>4.5V

1

125

µs
ns

140

53/70

ST62T08C/T09C ST62T10C/T20C /E20C

Figure 28.. RC frequency versus Vcc

Figure 29. LVD thresholds versus temperature

33.544.555.56

0.1

1

10

MHz

VDD (volts )

Frequency

R=47K
R=100K
R=470K

This curves represents typical variations and is given for guidance only

3.6

3.7

3.8

3.9

4

4.1

4.2

Temp

Vthresh.

-40°C 25°C 95°C 125°C

Vup
Vdn

This curves represents typical variations and is given for guidance only

141

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ST62T08C/T09C ST62T10C/T20C/E20 C

Figure 30. Idd WAIT versus Vcc at 8 Mhz for OTP devices

Figure 31. Idd STOP versus Vcc for OTP devices

Figure 32. Idd STOP versus Vcc for ROM devices

0

0.2

0.4

0.6

0.8

1

1.2

Vdd

Idd WA IT (mA)

3V 4V 5V 6V

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

-2

0

2

4

6

8

Vdd

Idd WAIT (µA)

3V 4V 5V 6V

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

-0.5

0

0.5

1

1.5

2

Vdd

Idd STOP (µA)

3V 4V 5V 6V

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

142

55/70

ST62T08C/T09C ST62T10C/T20C /E20C

Figure 33. Idd WAIT versus Vcc at 8Mhz for ROM devices

Figure 34. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices

Figure 35. Vol versus Iol on all I/O port at Vdd=5V

0

0.2

0.4

0.6

0.8

Vdd

Idd WA IT (mA)

3V 4V 5V 6V

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

1

2

3

4

5

Vdd

Idd RUN (mA)

3V 4V 5V 6V

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

010203040

0

2

4

6

8

Iol (mA)

Vol (V)

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

143

56/70

ST62T08C/T09C ST62T10C/T20C/E20 C

Figure 36. Vol ve rsus Iol on all I/O port at T= 25 ° C

Figure 37. Vol versus Iol for High sink (20mA) I/Oports at T=25°C

Figure 38. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V

0 10203040

0

2

4

6

8

Iol (mA)

Vol (V)

Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V

This curves represents typical variations and is given for guidance only

0 10203040

0

1

2

3

4

5

Iol (mA)

Vol (V)

Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V

This curves represents typical variations and is given for guidance only

0 10203040

0

1

2

3

4

5

Iol (mA)

Vol (V)

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

144

57/70

ST62T08C/T09C ST62T10C/T20C /E20C

Figure 39. Voh versus Ioh on all I/O port at 25°C

Figure 40. V oh ver sus I oh on all I/O port at Vd d=5V

0 10203040

-2

0

2

4

6

Ioh (mA)

Voh (V)

Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V

This curves represents typical variations and is given for guidance only

0 10203040

-2

0

2

4

6

Ioh (mA)

Voh (V)

T = -40°C
T = 25°C
T = 95°C
T = 125°C

This curves represents typical variations and is given for guidance only

145

58/70

ST62T08C/T09C ST62T10C/T20C/E20 C

7 GENERAL INFO RM ATION

7.1 PACKAGE MECHANICAL DATA
Figure 41. 20-Pin Plastic Dual In-Line Package, 300-mil Width

Figure 42. 20-Pin Ceramic Side-Brazed Dual In-Line Package

Dim.

mm inches

Min Typ Max Min Typ Max

A

5.33 0.210

A2

2.92 3.30 4.95 0.115 0.130 0.195

b

0.36 0.46 0.56 0.014 0.018 0.022

b2

1.14 1.52 1.78 0.045 0.060 0.070

c

0.20 0.25 0.36 0.008 0.010 0.014

D

24.89 26.92 0.980 1.060

e

2.54 0.100

E1

6.10 6.35 7.11 0.240 0.250 0.280

L

2.92 3.30 3.81 0.115 0.130 0.150

Number of Pins

N

20

PDIP20

Dim.

mm inches

Min Typ Max Min Typ Max

A

3.63 0.143

A1

0.38 0.015

B

3.56 0.46 0.56 0.140 0.018 0.022

B1

1.14 12.70 1.78 0.045 0.500 0.070

C

0.20 0.25 0.36 0.008 0.010 0.014

D

24.89 25.40 25.91 0.980 1.000 1.020

D1

22.86 0.900

E1

6.99 7.49 8.00 0.275 0.295 0.315

e

2.54 0.100

G

6.35 6.60 6.86 0.250 0.260 0.270

G1

9.47 9.73 9.98 0.373 0.383 0.393

G2

1.14 0.045

L

2.92 3.30 3.81 0.115 0.130 0.150

S

12.70 0.500

Ø

4.22 0.166

Number of Pins

N20

CDIP20W

146

59/70

ST62T08C/T09C ST62T10C/T20C /E20C

PACKAGE MECHANICAL DATA (Cont’d)
Figure 43. 20-Pin Plastic Small Outline Package, 300-mil Width

7.2 .ORDERING INFORMATION
Table 20. OTP/EPROM VERSION ORDERING INFORMATION

Sales Type I/O

Program

Memory (Bytes)

Analog

input

Temperature Range Package

ST62E20CF1

12

3884 (EPROM) 8 0 to +70°C CDIP20W

ST62T08CB6

1036 (OTP) None

-40 to + 85°C

PDIP20
ST62T08CM6 PSO20
ST62T09CB6

1036 (OTP) 4

PDIP20
ST62T09CM6 PSO20
ST62T10CB6

1836 (OTP)

8

PDIP20
ST62T10CM6 PSO20
ST62T20CB6

3884 (OTP)

PDIP20
ST62T20CM6 PSO20
ST62T20CB3

3884 (OTP) -40 to + 125°C

PDIP20
ST62T20CM3 PSO20

Dim.

mm inches

Min Typ Max Min Typ Max

A

2.35 2.65 0.0926 0.1043

A1

0.10 0.0040

B

0.33 0.51 0.0130 0.0200

C

0.32 0.0125

D

4.98 13.00 0.1961 0.5118

E

7.40 7.60 0.2914 0.2992

e

1.27 0.050

H

10.01 10.64 0.394 0.419

h

0.25 0.74 0.010 0.029

K

0° 8° 0° 8°

L

0.41 1.27 0.016 0.050

G

0.10 0.004

Number of Pins

N20

SO20

147

60/70

ST62T08C/T09C ST62T10C/T20C/E20 C

Notes:

148

September 1998 61/70

Rev. 2.6

ST62P08C/P09C
ST62P10C/P20C

8-BIT FASTROM MCUs WITH A/D CONVERTER,

OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS

■

3.0 to 6.0V Supply Operating Range

■

8 MHz Maximum Clock Frequency

■

-40 to +125°C Operating Temperature Range

■

Run, Wait and Stop Modes

■

5 Interrupt Vectors

■

Look-up Table capability in Program Memory

■

Data Storage in Program Memory:
User selectable size

■

Data RAM: 64bytes

■

12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62P08C)

■

4 I/O lines can sink up to 20mA to drive LEDs or

TRIACs directly

■

8-bit Timer/Counter with 7-bit programmable

prescaler

■

Digital Watchdog

■

Oscillator Safe Guard

■

Low Voltage Detector for Safe Reset

■

8-bit A/D Converter with up to 8 analog inputs

■

On-chip Clock oscillator can be driven by Quartz

Crystal Ceramic resonator or RC network

■

Power-on Reset

■

One external Non-Maskable Interrupt

■

ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a

parallel port)

DEVICE SUMMARY

PDIP20

PSO20

(See end of Datasheet for Ordering Information)

DEVICE

ROM

(Bytes)

I/O Pins

Analog

inputs

ST62P08C 1036 1 2 ­ST62P09C 1036 1 2 4
ST62P10C 1836 1 2 8
ST62P20C 3884 1 2 8

149

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ST62P08C/P09C ST62P10C/P20C

1 GENERAL DESCRIPTIO N

1.1 INTRODUCTION

The ST62P08C,P09C,P10C,P20C are the Factory

A

dvanced Service Technique ROM (FASTROM)
versions of ST62T08C,T09C,T10C,T20C OTP de­vices.

They offer the same functionality as OTP devices,
selecting as FASTROM options the options de­fined in the program mab le o ption byt e of the OTP
version.

1.2 ORDERING INFORMATION

The following section deals with the proc ed ure f or
transfer of customer codes to STMicroelectronics.

1.2.1 Transfer of Customer Code

Customer code is made up of t he ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.

The selected options are com municated t o STM i­croelectronics using the correctly filled OPTION
LIST appended.

1.2.2 Listing Generation and Verification

When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to th e RO M con­tents an d options which will be u sed to produ ce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, com­plete, sign and return it to STMicroelectronics. The
signed listing forms a part of the contractual agree-

ment for the production of the specific customer
MCU.

The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con­tractual points.

Table 1. ROM Memory Map for ST62P08C,P09C

Table 2. ROM Memory Map for ST62P10C

Table 3. ROM Memory Map for ST62P20C

Device Address Description

0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-087Fh

0880h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-007Fh

0080h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

150

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ST62P08C/P09C ST62P10C/P20C

ORDERING INFORMATION (Cont’d)
Table 4. ROM version Ordering Information

(*)

Adva nced info rmation

Sales Type ROM Analog inputs Temperature Range Package

ST62P08CB1/XXX
ST62P08CB6/XXX
ST62P08CB3/XXX (*)

1036 Bytes None

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST62P08CM1/XXX
ST62P08CM6/XXX
ST62P08CM3/XXX (*)

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST62P09CB1/XXX
ST62P09CB6/XXX
ST62P09CB3/XXX (*)

1036 Bytes 4

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP2

ST62P09CM1/XXX
ST62P09CM6/XXX
ST62P09CM3/XXX (*)

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST62P10CB1/XXX
ST62P10CB6/XXX
ST62P10CB3/XXX (*)

1836 Bytes 8

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST62P10CM1/XXX
ST62P10CM6/XXX
ST62P10CM3/XXX (*)

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST62P20CB1/XXX
ST62P20CB6/XXX
ST62P20CB3/XXX (*)

3884 Bytes 8

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST62P20CM1/XXX
ST62P20CM6/XXX
ST62P20CM3/XXX (*)

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

151

64/70

ST62P08C/P09C ST62P10C/P20C

ST62P08C/P09C/P10C/P20C FASTROM MICROCONTROLLER OPTION LIST

Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references
Device: [ ] ST62P08C [ ] ST62P09C [ ] ST62P10C [ ] ST62P20C
Package: [ ] Dual in Line Plastic [ ] Small Outline Plas tic with conditionning:

[ ] Standard (Stick)
[ ] Tape & Reel

Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C

Oscillator Sourc e Sele ction: [ ] Cr ystal Quartz/Ceramic resonat or

[ ] RC Network

Watchdog Selection: [ ] Software Activation

[ ] Hardware Activation

Readout Protection: [ ] Disabled

[ ] Enabled

External STOP Mode Control[ ] Enabled [ ] Disabled
LVD Reset [ ] Enabled [ ] Disabled
TIMER pin pull-up [ ] Enabled [ ] Disabled
NMI pin pull-up [ ] Enabled [ ] Disabled
OSG [ ] Enabled [ ] Disabled

Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

152

September 1998 65/70

Rev. 2.6

ST6208C/0 9C
ST6210C/2 0C

8-BIT ROM MCUs WITH A/D CONVERTER,

OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS

■

3.0 to 6.0V Supply Operating Range

■

8 MHz Maximum Clock Frequency

■

-40 to +125°C Operating Temperature Range

■

Run, Wait and Stop Modes

■

5 Interrupt Vectors

■

Look-up Table capability in Program Memory

■

Data Storage in Program Memory:
User selectable size

■

Data RAM: 64bytes

■

12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST6208C)

■

4 I/O lines can sink up to 20mA to drive LEDs or

TRIACs directly

■

8-bit Timer/Counter with 7-bit programmable

prescaler

■

Digital Watchdog

■

Oscillator Safe Guard

■

Low Voltage Detector for Safe Reset

■

8-bit A/D Converter with up to 8 analog inputs

■

On-chip Clock oscillator can be driven by Quartz

Crystal Ceramic resonator or RC network

■

Power-on Reset

■

One external Non-Maskable Interrupt

■

ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a

parallel port)

DEVICE SUMMARY

PDIP20

PSO20

(See end of Datasheet for Ordering Information)

DEVICE

ROM

(Bytes)

I/O Pins

Analog

inputs

ST6208C 1036 1 2 ­ST6209C 1036 1 2 4
ST6210C 1836 1 2 8
ST6220C 3884 1 2 8

153

66/70

ST6208C/09C ST6210C/20C

1 GENERAL DESCRIPTIO N

1.1 INTRODUCTION

The ST6210C/20C are mask programmed ROM
version of ST62T08C,T09C,T10C,T20C OTP de­vice s.

They offer the same functionality as OTP devices,
selecting as ROM options the options def ined in
the programmable option byte of the OTP version.

Figure 1. Prog ra m mi ng wave form

1.2 ROM READOUT PROTECTION

If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre­vent any access to the program memory content.

In case the user wants to blow this fuse, high volt­age must be applied on the TEST pin.

Figure 2. Programming Circuit

Note: ZPD15 is used for overvoltage protection

0.5s min

TEST

15

14V typ

10

5

TEST

100mA

4mA typ

VR02001

max

150 µs typ

t

VR02003

TEST

5V

100nF

47mF

PROTECT

100nF

V

DD

V

SS

ZPD15
15V

14V

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ST6208C/09C ST6210C/20C

ST6208C/09C/10C/20C MICROCONTROLLER OPTION LIST

Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references
Device: [ ] ST6208C [ ] ST6209 C [ ] ST6210C [ ] ST6220C
Package: [ ] Dual in Line Plastic [ ] Small Outline Plas tic with conditionning:

[ ] Standard (Stick)

[ ] Tape & Reel
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: DIP20: 10

SO20: 8

Oscillator Sourc e Sele ction: [ ] Cr ystal Quartz/Ceramic resonat or

[ ] RC Network

Watchdog Selection: [ ] Software Activation

[ ] Hardware Activation

ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)

[ ] Enabled (Fuse can be blown by the customer)

Note: No part is delivered with protected ROM.

The fuse must be blown for protection to be effective.

External STOP Mode Control[ ] Enabled [ ] Disabled
LVD Reset [ ] Enabled [ ] Disabled
TIMER pin pull-up [ ] Enabled [ ] Disabled
NMI pin pull-up [ ] Enabled [ ] Disabled
OSG [ ] Enabled [ ] Disabled

Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

155

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ST6208C/09C ST6210C/20C

1.3 ORDERING INFORMATION

The following section deals with the proc ed ure f or
transfer of customer codes to STMicroelectronics.

1.3.1 Transfer of Customer Code

Customer code is made up of t he ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener­ated by the development tool. All unused bytes
must be set to FFh.

The selected mask op tions are communica ted to
STMicroelectronics using the correctly filled OP­TION LIST appended.

1.3.2 Listing Generation and Verification

When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be u sed to produc e the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.

The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con­tractual points.

Table 1. ROM Memory Map for ST6208C,09C

Table 2. ROM Memory Map for ST6210C

Table 3. ROM Memory Map for ST6220C

Device Address Description

0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-087Fh

0880h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-007Fh

0080h-0F9Fh
0FA0h-0FEFh

0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

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ST6208C/09C ST6210C/20C

ORDERING INFORMATION (Cont’d)
Table 4. ROM version Ordering Information

Sales Type ROM Analog inputs Temperature Range Package

ST6208CB1/XXX
ST6208CB6/XXX
ST6208CB3/XXX

1036 Bytes None

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST6208CM1/XXX
ST6208CM6/XXX
ST6208CM3/XXX

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST6209CB1/XXX
ST6209CB6/XXX
ST6209CB3/XXX

1036 Bytes 4

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP2

ST6209CM1/XXX
ST6209CM6/XXX
ST6209CM3/XXX

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST6210CB1/XXX
ST6210CB6/XXX
ST6210CB3/XXX

1836 Bytes 8

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST6210CM1/XXX
ST6210CM6/XXX
ST6210CM3/XXX

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST6220CB1/XXX
ST6220CB6/XXX
ST6220CB3/XXX

3884 Bytes 8

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PDIP20

ST6220CM1/XXX
ST6220CM6/XXX
ST6220CM3/XXX

0 to +70°C

-40 to + 85°C

-40 to + 125°C

PSO20

157

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ST6208C/09C ST6210C/20C

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of us e of s uch in fo rma tio n nor fo r an y inf rin g eme nt o f p a tent s o r othe r ri ght s of th ir d part i es w hic h ma y res ul t f rom i ts use. No lic ense is granted
by implica tion or otherwise un der any pat ent or pat ent rights of STMicroelectronics. Spec i fications mentioned in this publi cation are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics produ ct s are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroel ectronics



1998 STMicroelectronics - All Rights Reserved.

Purchase of I

2

C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an

I

2

C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.

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