ST2305A is the P-Channel logic enhancement mode power field effect transistor which
is produced using high cell density, DMOS trench technology. This high density
process is especially tailored to minimize on-state resistance. These devices are
particularly suited for low voltage application such as cellular phone and notebook
computer power management, other battery powered circuits, and low in-line power
loss are required. The product is in a very small outline surface mount package.
PIN CONFIGURATION
SOT-23-3L
3
D
G
1
1.Gate 2.Source 3.Drain
PART MARKING
SOT-23-3L
S
FEATURE
-20V/-3.5A, R
@VGS = -4.5V
-20V/-3.0A, R
@VGS = -2.5V
-20V/-2.0A, RDS(ON)=80m-ohm
@VGS=-1.8V
Super high density cell design for
extremely low R
Exceptional on-resistance and maximum
DC current capability
SOT-23-3L package design
= 45m-ohm (Typ.)
DS(ON)
= 55m-ohm
DS(ON)
DS(ON)
05YA
1
Y: Year Code A: Process Code
STANSON TECHNOLOGY
120 Bentley Square, Mountain View, Ca 94040 USA
www.stansontech.com
ST2305A 2005. V1
Page 2
ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted )
ST2305A
P Channel Enhancement Mode MOSFET
Parameter Symbol Typical Unit
-3.5A
Drain-Source Voltage V
Gate-Source Voltage V
Continuous Drain CurrentTJ=150℃)
Pulsed Drain Current IDM -10 A
Continuous Source Current (Diode Conduction) IS -1.6 A
Power Dissipation
Operation Junction Temperature TJ 150
Storgae Temperature Range T
Thermal Resistance-Junction to Ambient
TA=25℃
TA=70℃
TA=25℃
TA=70℃
-20 V
DSS
±
GSS
ID
PD
-55/150
STG
θ
R
JA
12
-3.5
-2.8
1.25
0.8
120
W
℃
℃
℃
V
A
/W
STANSON TECHNOLOGY
120 Bentley Square, Mountain View, Ca 94040 USA
www.stansontech.com
ST2305A 2005. V1
Page 3
nA
ST2305A
P Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS ( Ta = 25℃ Unless otherwise noted )