Datasheet ST10R272LAT1, ST10R272L Datasheet (SGS Thomson Microelectronics)

Download

Page 1

April 2000 1/77

This is preliminary information on a new product now in development. Details are subject to change without notice.

Rev. 1.2

■ High Performance 16-bit CPU

● CPU Frequency: 0 to 50 MHz

● 40ns instruction cycle time at 50-MHz CPU

clock

● Multiply-Accumulate unit (MAC)

● 4-stage pipeline

● Register-based design with multiple

variable register banks

● Enhanced boolean bit manip ulation

facilities

● Additional instructions to support HLL and

operating systems

● Single-cycle context switching support

● 1024 bytes on-Chip special function

■ Memory Organisation

● 1KByte on-chip RAM

● Up to 16 MBytes linear address space for

code and data (1 MByte with SSP used)

■ External Memory Interface

● Programmable external bus characteristics

for different address ranges

● 8-bit or 16-bit external data bus

● Multiplexed or demultiplexed external

address/data buses

● Five programmable chip-select signals

● Hold and hold-acknowledge bus arbitration

support

■ One Channel PWM Unit

● Fail Safe Protection

● Programmable watchdog timer

● Oscillator Watchdog

■ Interrupt

● 8-channel interrupt-driven single-cycle data

transfer facilities via peripheral event controller (PEC)

● 16-priority-level interrupt system with 17

sources, sample-rate down to 40 ns

■ Timers

● Two multi-functional general purpose timer

units with 5 timers

● Clock Generation via on-chip PLL, or via

direct or prescaled clock input

■ Serial Channels

● Synchronous/asynchronous

● High-speed-synchronous serial port SSP

■ Up to 77 general purpose I/O lines

■ No bootstrap loader

■ Electrical Characteristics

● 5V Tolerant I/Os

● 5V Fail-Safe Inputs (Port 5)

● Power: 3.3 Volt +/-0.3V

● Idle and power down modes

■ Support

● C-compilers, macro-assembler packages,

emulators, evaluation boards, HLLdebuggers, simulators, logic analyser disassemblers, programming boards

■ Package

● 100-Pin Thin Quad Flat Pack (TQFP)

ST10 CORE

DPRAM

Interrupt Controller

P.4

P.1 P.0

Po.2

P.6

P.3

Dedicated

pins

ASC GPT1/2

&PEC

WDT

XSSP

P.5

OSC

PLL

P.7

PWM

MAC

ST10R272L

16-BIT LOW VOLTAGE RO MLESS MCU WITH MAC

PRODUCT PREVIEW

Page 2

2/77

Table of Contents

1 PIN DESCRIPTIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 MULTIPLY-ACCUMULATE UNIT (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 MAC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 MAC OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 INTERRUPT SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 HARDWARE TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 PARALLEL P ORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 PWM MODUL E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 GENERAL PU RPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

12 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

16.1 ABSOLUTE MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

16.2 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

16.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Page 3

3/77

Table of Contents

16.3.1 CPU clock generation mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

16.3.2 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

16.3.3 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.3.4 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16.3.5 CLKOUT and READY

/READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

16.3.6 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

16.3.7 External hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

16.3.8 Syn chronous serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17 PACKAGE MECHANICAL DAT A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

18 ORDERING IN FORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Page 4

4/77

ST10R272L - PIN DESCRIPTION

1 PIN DESCRIPTION

Figure 1 TQFP-100 pin configuration (top view)

12345678910111213141516171819202122232425

26 272829303132 33 34 35 36 37 38 39 40414243444546 47 48 49 50

75747372717069686766656463626160595857565554535251

100999897969594939291908988878685848382818079787776

P5 .1 3/T5IN

P5.14/T4EUD

P5.15/T2EUD

XTAL1

XTAL2

P3.0

P3 .1 /T6OU T

P3.2/CAPIN

P3 .3 /T3OU T

P3 .4 /T3EU D

P3 .5 /T 4IN

P3 .6 /T 3IN

P3 .7 /T 2IN

P3.8

P3.9

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13

P3.15/CLKOUT

P4 .0 /A16

P4 .1 /A17

P4 .2 /A18

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

SSVDD

P1H.1/A9

P1H.0/A8

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

P0H.0/AD8

P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN V

P1H.7/A15

P4.3/A19

P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK

WR/WRL

READY/READY

ALE

RPD

P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7

ST10R 272L

Page 5

5/77

ST10R272L - PIN DESCR IPTION

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

P5.10

–P5.15

98-100 1- 3

I I

5S5S6-bit input-only port with Schmitt-Trigger characteristics.

Port 5 pins also serve as timer inputs:

98 I 5S P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down

Ctrl.Input

99 I 5S P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down

Ctrl.Input 100 I 5S P5.12 T6IN GPT2 Timer T6 Count Input 1 I 5S P5.13 T5IN GPT2 Timer T5 Count Input 2 I 5S P5.1 4 T4 EUD GPT1 Timer T4 Ex t. Up / Down

Ctrl.Input 3 I 5S P5.1 5 T2 EUD GPT1 Timer T2 Ex t. Up / Down

Ctrl.Input

XTAL1

XTAL2

5 I 3T X TAL1: Input to the oscillator amplifier and internal clock

generator

6 O 3T XTAL2: Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Observe minimum and maximum high/low and rise/fall times specified in the AC Characteristics.

Table 1 Pin definiti ons

Page 6

6/77

ST10R272L - PIN DESCR IPTION

P3.0 – P3.13

P3.15

8-21

I/O

5T 5TA 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bit-

wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following pins have alternate

functions: 9 O 5T P3.1 T6OUT GPT2 Timer T6 toggle latch output 10 I 5T P3. 2 CAPIN GPT2 Register CAPREL capture

input 11 O 5T P3.3 T3OUT GPT1 Timer T3 toggle latch output 12 I 5T P3. 4 T3EUD GPT1 Timer T3 ext.up/down ctrl.input 13 I 5T P3. 5 T4IN GPT1 Timer T4 input for count/gate/

reload/capture 14 I 5T P 3.6 T3IN GPT1 Timer T3 count/ gate input 15 I 5T P3. 7 T2IN GPT1 Timer T2 input for count/gate/

reload/capture 18 O 5T P3.10 TxD0 ASC0 clock/data output (asyn./syn.) 19 I/O 5T P3. 11 RxD0 ASC0 data input (asyn.) or I/O (syn.) 20 O 5T P3.12 BHE

Ext. Memory High Byte Enable Signal

O5T WRH

Ext. Memory High Byte Write Strobe 22 O 5T P3.15 CLKOUT System clock output (=CPU clock)

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

Table 1 Pin definiti ons

Page 7

7/77

ST10R272L - PIN DESCR IPTION

P4.0– P4.7

23-26 29-32-

I/O 5T An 8-bit bidirectional I/O port. Port 8 is bit-wise programmable

for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 can be used to output the segment address lines for

external bus configuration. 23 O 5T P4.0 A16 Least Significant Segment Addr. Line

... ... ... ... ... ...

26 O 5T P4.3 A19 Segment Address Line 29 O 5T P4.4 A20 Segment Address Line

O 5T SSPCE1 Chip Enable Line 1

30 O 5T P4.5 A21 Segment Address Line

O 5T SSPCE0 SSPChip Enable Line 0

31 O 5T P4.6 A22 Segment Address Line

I/O 5T SSPDAT SSP Data Input/Outpu t Line

32 O 5T P4.7 A23 Most Significant Segment Addr. Line

O 5T SSPCLK S SP Clock Output Line

33 O 5T External Memory Read Strobe. RD is activated for every exter-

nal instruction or data read access.

WR/ WRL

34 O 5T External Memory Write Strobe. In WR-mode, this pin is acti-

vated for every external data write access. In WRL-mode, this

pin is activated for low byte data write accesses on a 16-bit

bus, and for every data write access on an 8-bit bus.

See WRCFG in the SYSCON register for mode selection.

READY/ READY

35 I 5T Ready Input. Active level is programmable. When the Ready

function is enabled, the selected inactive level at this pin dur-

ing an external memory access will f orce t he insertion of mem-

ory cycle time waitstates until the pin returns to the selected

active level. Polarity is pro gram mable.

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

Table 1 Pin definiti ons

Page 8

8/77

ST10R272L - PIN DESCR IPTION

ALE 36 O 5T Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multi-

plexed bus modes.

37 I 5T E xt ernal Access Enable pin. Low level at this pin during and

after reset forces the ST10R272L to begin instruction execu-

tion out of external memory. A high level forces execution out

of the internal ROM. The ST10R272L must have this pin tied

to ‘0’.

PORT0: P0L.0–

P0L.7, P0H.0 -

P0H.7

41 - 48

51 - 58

I/O 5T PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is

bit-wise programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into high-

impedance state.

For external bus configuration, PORT0 acts as address (A)

and address/data (AD) bus in multiplexed bus modes and as

the data (D) bus in demultiplexed bus modes.

PORT1: P1L.0–

P1L.7, P1H.0 -

P1H.7

59- 66

67, 68 71-76

I/O 5T PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is

bit-wise programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into high-

impedance state. PORT1 acts as a 16-bit address bus (A) in

demultiplexed bus modes and also after switching from a

demultiplexed bus mode to a multiplexed bus mode.

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

Table 1 Pin definiti ons

Demultiplexed bus modes

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15

Multiplexed bus modes

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

Page 9

9/77

ST10R272L - PIN DESCR IPTION

RSTIN 79 I 5T Reset Input with Schmitt-Tr ig ger characteristics. Resets the

device when a low level is applied for a specified duration while

the oscillator is running. An internal pullup resi stor enables

power-on reset using only a capacitor connected to

. With

a bonding option, the RSTIN

pin can also be pulled-down for 512 internal clock cycles for hardware, software or watchdog timer triggered resets

RSTOUT

80 O 5T Internal Reset Indication Output. This pin is set to a low level

when the part is executes hardware-, software- or watchdog timer reset. RSTOUT

remains low until the EINIT (end of ini-

tialization) instruction is executed.

NMI

81 I 5S Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. If it is not used, NMI

should be pulled high externally.

P6.0P6.7

82-89 I/O 5T An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable

for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers.

The following Port 6 pins have alternate functions:

82 O 5T P6.0 CS0

Chip Select 0 Output

... ... ... ... ... ...

86 O 5T P6.4 CS4

Chip Select 4 Output 87 I 5T P 6. 5 HOL D

External Master Hold Request Input

(Master mode: O, Slave mode: I) 88 I/O 5T P6.6 HLDA

Hold Acknowledge Output 89 O 5T P6.7 BRE Q

Bus Request Output

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

Table 1 Pin definiti ons

Page 10

10/77

ST10R272L - PIN DESCR IPTION

P2.8 – P2.11

90 - 93 I/O 5T Por t 2 is a 4-bit bidirectional I/O port. It is bit-wise programma-

ble for input or output via di rection bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers.

The following Port 2 pins have alternate functions: 90 I 5T P 2.8 EX0IN Fast External Interrupt 0 Input

... ... ... ... ... ...

93 I 5T P 2.11 EX 3IN Fast External Interrupt 3 Input

P7.0 – P7.3

94 - 97 I/O 5T Por t 7 is a 4-bit bidirectional I/O port. It is bit-wise programma-

ble for input or output via di rection bits. For a pin configured as

input, the output driver is put into high-impedance state. Port

7outputs can be configured as push/pull or open drain drivers.

The following Port 7 pins have alternate functions: 97 O 5T P7.3 POUT3 PWM (Channel 3) Output

RPD 40 I/O 5T Input timing pin for the return from powerdown circuit and

power-up asynchronous reset.

7, 28, 38, 49, 69, 78

- PO Digital supply voltage.

4, 27, 39, 50, 70, 77

- PO Digital ground.

1) The following I/O kinds are used. Refer to

ELECTRICAL CHARACTERISTICS

page 40 for a detailed description. PO: Power pin 3T: 3 V tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5) 5V: 5 V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered) 5S: 5 V tolerant and f ail-safe pin (-0.5-5.5 ma x. voltage w.r.t. Vss ev en if chip is n ot pow-

ered).

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

Table 1 Pin definiti ons

Page 11

11/77

ST10R272L - FUNCTIONAL DESCRIPTION

2 FUNCTI ONAL DESCRIPTION

ST10R272L architecture combines the advantages of both RISC and CISC processors wi th an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure.

Figure 2 Block diagram

ST10 CO RE

1KByte

DPRAM

Interrupt Controller

Port 4

Port 1

8-bit

2x8-bit

Port 0

2x8-bit

Port 2

4-bit

Port 6

8-bit

I/O

CS(4:0)

I/O

HOLD

HLDA

BREQ

A(15:0)

I/O, D(7:0)

D(15:8), D(7:0)

A(15:8), AD(7:0)

AD(15:8), AD(7:0)

I/O

Port 3

15-bit

I/O

EXIN(3:0)

XTAL1

dedicated

pins

ASC GPT1/2

PEC

I/O CLKOUT, BHE/WRH

, RxD0, TxD0, T2IN, T3IN, T4IN, T3EUD, T3OUT, CAPIN, T6OUT

I T2EUD, T4EUD, T5IN, T6IN, T5EUD, T6EUD

EA, ALE, RD, WR/WRL, READY, NMI, RSTIN, RSTOUT

WDT

XSSP

4-bit

I/O A(23:16), SSPCLK, SSPDAT, SSPCE(1:0)

Port 5

6-bit

OSC

PLL

XTAL2

Port 7

4-bit

PWM

I/O

POUT3

MAC

Page 12

12/77

ST10R272L - MEMORY MA PPING

3 MEMORY MAPPING

The ST10R272L is a ROMless device, the internal RAM space is 1 KByte. The RAM address

space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h

- 00’FCFFh) and the bit-addressable space (in 00’FD00h - 00’FDFFh).

Figure 3 Memory map

XSSP

Data Page 0

Data Page 1

Data Page 2

Data Page 3

00’0000h

00’4000h

00’8000h

00’F000h

00’FFFFh

00’0000h

00’1FFFh

8K-byte

00’EF00h

00’EFFFh

256 Byte

internal memory

00’F000h

00’F200h

00’FE00h

00’FFFFh

SFR Area (reserved)

1K-Byte

RAM/SFR

DPRAM / SFR Area 4 K-Byte

System Segment 0 64 K-Byte

External memory

00’FE20h

00’FE3Fh

00’FF20h

00’FF3Fh

ESFR Area (reserved)

00’F020h

00’F03Fh

00’FF20h

00’FF3Fh

RAM

00’FA00h

Block 1

Block 0

Page 13

13/77

ST10R272L - CENTRAL PROCESSING UNIT

4 CENTRAL PROCESSING UNIT

The main core of the CPU contains a 4-stage instruction pipeline, a MAC multiplyaccumulation unit, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be ex ecuted i n one machine cycle r equiring 40ns at 50MHz CPU clock.

The CPU includes an actual register context consisting of 16 wordwide GPRs physically located in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the activ e register bank to be ac cessed b y the CPU . T he number of r egister banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is al located in the on-chip RAM area, and it i s accessed by the C PU via the stac k pointer (SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack pointer value during each stack access to detect stack overflow or underflow.

Figure 4 CPU block diagram

Internal

RAM

1KByte

R15

General

Purpose

Registers

R15

MDH

MDL

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

Context Ptr

ADDRSEL 1 ADDRSEL 2

ADDRSEL 3 ADDRSEL 4

Code Seg. Ptr.

CPU

IDX0

IDX1 QX1

QX0 QR0

QR1

STKOV STKUN

Exec. Unit

Instr. Ptr Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1

BUSCON 2 BUSCON 3 BUSCON 4

Data Pg. Ptrs

Page 14

14/77

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

5 MULTIPLY-ACCUMULATE UNIT (MAC)

The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the performance of signal processing algorithms. It includes:

• a multiply-accumulate unit

• an address generation unit, able to feed the mac unit with 2 operands per cycle

• a repeat unit, to execute a series of multiply-accumulate instructions

New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic operations and the CoMOV transfer ins tru ction have been added to the standard instruction

set. Full details are provided in the ‘ST10 Family Programming Manual’.

Figure 5 MAC architecture

MAC CoProcessor

dual-port

internal RAM

external memory

memory

program

new addressing features

IDX0

IDX1

QX0

QX1

QR0 QR1

operands

control

program code

data buses

16 x16

multiplier

40-bit ALU

shifter

MCW

MAL

MRW MAH

MSW

repeat unit

40-bit accumulator

Peripheral interface

ST10R272L CPU

Page 15

15/77

ST10R272L - MULTIPLY-ACCU MULATE UNIT (MAC)

5.1 MAC Features

Enhanced addressing capabilities

•

Double indirect addressing mode with pointer post-modification.

• Parallel Data Move allows one operand move during Multiply-Accumulate instructions

without penalty.

• CoSTORE instruction (for fast access to the MAC SFRs) and CoMOV (for fast memory to

memory table transfer).

General

•

Two-cycle execution for all MAC operations.

• 16 x 16 signed/unsigned parallel multiplier.

• 40-bit signed arithmetic unit with automatic saturation mode.

• 40-bit accumulator.

• 8-bit left/right shifter.

• Scaler (one-bit left shifter)

• Data limiter

• Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and

compare instructions.

• Three 16-bit status and control registers: MSW: MAC Status Word, MCW: MAC Control

Word, MRW: MAC Repeat Word.

Progra m control

•

Repeat Unit allows some MAC co-pr ocessor instructions to be repeated up to 8192 times . Repeated instructions may be interrupted.

• MAC interrupt (Class B Trap) on MAC condition flags.

Page 16

16/77

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

5.2 MAC Operation

Instruction pipelini ng

All MAC instructions use the 4-stage pipeline. During each stage the following tasks are performed:

• FETCH: All new instructions are double-word instructions.

• DECODE: If required, operand addresses are calculated and the resulting operands are

fetched. IDX and GPR pointers are post-modified if necessary.

• EXECUTE: Performs the MAC operation. At the end of the cycle, the Accumulator and the

MAC condition flags are updated if required. Modified GPR pointers are written-back during this stage, if required.

• WRITEBACK: Operand write-back in the case of parallel data move.

Note At least one instruction which does not use the MAC must be inserted between two

instructions that read from a MAC register. This is because the Accumulator and the status of the MAC are modified during the Execute stage. The CoSTORE instruction has been added to allow access to the MAC registers immediately after a MAC operation.

Address generation

MAC instructions can use some standard ST10 addressing modes such as GPR direct or #data4 for immediate shift value.

New addressing modes have been added to supply the MAC with two new operands per instruction cycle. These allow indirect addressing with address pointer post-modification.

Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX

). The GPR

pointer allows access to the entire memory space, but IDX

are limited to the internal Dual-

Port RAM, except for the CoMOV instruction.

Page 17

17/77

ST10R272L - MULTIPLY-ACCU MULATE UNIT (MAC)

The following table shows the various combinations of pointer post-modification for each of

these 2 new addressing modes. In this document the symbols “[Rw

⊗]” and “[IDXi⊗]” refer to

these addressing modes.

For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This class of instruction is only a vailable with double indirect addres sing mode. P ar al lel D ata Mo v e allows the operand pointed by IDX

to be moved to a new location in parallel with the MAC operation. The write-back address of Parallel Data Move is calculated depending on the postmodification of IDX

. It is obtained by the rev erse oper ation than the one used to calculate the

new value of IDX

. The following table shows these rules.

Symbol Mnemonic Address Pointer Operation

“[IDXi⊗]” stands for [IDXi](IDX

) ← (IDXi) (no-op)

[IDXi+](IDX

) ← (IDXi) +2 (i=0,1)

[IDXi -] (IDXi) ← (IDXi) -2 (i=0,1)

[IDXi + QXj](IDX

) ← (IDXi) + (QXj) (i, j =0,1)

[IDXi - QXj](IDX

) ← (IDXi) - (QXj) (i, j =0,1)

“[Rw

⊗]” stands for [Rwn] (Rwn) ← (Rwn) (no-op)

[Rwn+] (Rwn) ← (Rwn) +2 (n=0-15) [Rwn-] (Rwn) ← (Rwn) -2 (k=0-15) [Rwn+QRj] (Rwn) ← (Rwn) + (QRj) (n=0-15;j =0,1)

[Rwn - QRj] (Rwn ) ← (Rwn) - (QRj) (n=0-15; j =0,1)

Table 2 Pointer post-modification combinations for IDXi and Rwn

Instructio n Writeback Address

CoMACM [IDX

+],... <IDXi-2>

CoMACM [IDX

-],... <IDXi+2>

CoMACM [IDX

+QXj],... <IDXi-QXj>

CoMACM [IDX

-QXj],... <IDXi+QXj>

Table 3 Parallel data move addressing

Page 18

18/77

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

The Parallel Data Move shifts a table of operands in parallel with a computation on those operands. Its specific use is for signal processing algorithms like filter computation. The following figure gives an example of Parallel Data Move with CoMACM instruction.

16 x 16 signed/unsigned parallel mul tiplier

The multiplier executes 16 x 16-bit parallel signed/unsigned fractional and integer multiplies. The multiplier has two 16-bit i nput ports, and a 32-bit product output port. The input ports can accept data from the MA-bus and from the MB-bus. The output is sign-extended and then feeds a scaler that shifts the multiplier output according to the shift mode bit MP specified in the co-processor Control Word (MCW). The product can be shifted one bit left to compensate

for the extra sign bit gained in multiplying two 16-bit signed (2’s complement) fractional numbers if bit MP is set.

40-bit signed arithmetic unit

The arithmetic unit over 32 bits wide to allow intermediate overflow in a series of multiply/ accumulate operations. The extension flag E, contained in the most significant byte of MSW, is set when the Accumulator has overflowed beyond the 32-bit boundary, that is, when there are significant (non-sign) bits in the top eight (signed arithmetic) bits of the Accumulator.

The 40-bit arithmetic unit has two 40-bit input ports A and B. The A-input port accepts data from 4 possible sources: 00,0000,0000h, 00,0000,8000h (round), the sign-extended product, or the sign-extended data c on veyed b y the 32-bit b us result ing from the concatenation of MAand MB-buses. Product and Concatenation can be shifted left by one according to MP for the multiplier or to the i ns truction f or the concatenation. The B-input port is fed either by the 40-bit shifted/not shifted and inverted/not inverted accumulator or by 00,0000,0000h. A-input and B-

Figure 6 Example of parallel data move

CoMACM [IDX0+], [R2+]

n+2 n n-2 n-4

16-bit

IDX0 X

n+2 n n-2 n-4

IDX0

Parallel Data Move

After ExecutionBefore Execution

Page 19

19/77

ST10R272L - MULTIPLY-ACCU MULATE UNIT (MAC)

input ports can receive 00,0000,0000h to allow direct transfers from the B-source and Asource, respectively, to the Accumulator (case of Multiplication, Shift.). The output of the arithmetic unit goes to the Accumulator.

It is also possible to saturate the Accumulator on a 32-bit value, automatically after every accumulation. Automatic saturation is enabled by setting the saturation bit MS in the MCW register. When the Accumulator is in the saturation mode and an 32-bit overflow occurs, the accumulator is loaded with either the most positive or the most negative value representable in a 32-bit value, depending on the direction of the overflow. The value of the Accumulator upon saturation is 00,7fff,ffffh (positive) or ff,8000,0000h (negative) in signed arithmetic. Automatic saturation sets the SL flag MSW. This flag is a sticky flag which means it stays set until it is explicitly reset by the user.

40-bit overflow of the Accumulator sets the SV flag in MSW. This flag is also a sticky flag.

40-bit accumulator register

The 40-bit Accumulator consists of three SFR registers MAH, MAL and MAE. MAH and MAL are 16-bit wide. MAE is 8-bit wide and is contained within the least significant byte of MSW. Most co-processor operations specify the 40-bit Accumulator register as source and/or destination operand.

Data limite r

Saturation arithmetic is also provided to selectively limit overflow, when reading the accumulator by means of a CoSTORE <destination>

MAS instruction. Limiting is performed on the MAC Accumulator. If the contents of the Accumulator can be represented in the destination operand size without overflow, the data limiter is disabled and the operand is not modified. If the contents of the accumulator cannot be represented without overflow in the

destination operand size, the limiter will substitute a ‘limited’ data as explained in the f ollowing table.

Note In this case, the accumulator and the status register are not affected. MAS readable

from a CoSTORE instruction.

x 0 x unchanged MAS 1 0 7fffh MAS 1 1 8000h

Table 4 Data Limit Values

Page 20

20/77

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

Accumulator shi fter

The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source operand of the shifter is the Accumulator and the possible shifting operations are:

• No shift (Unmodified)

• Up to 8-bit Arithmetic Left Shift

• Up to 8-bit Arithmetic Right Shift

E, SV and SL bits from MSW are affected by Left shifts, theref or e i f the s atur ation mechanism is enabled (MS), the behavior is similar to the one of the arithmetic unit. The carry flag C is also affected by left shifts.

Repeat unit

The MAC includes a repeat unit allowing the repetition of some co-processor instructions up to 2

(8192) times. The repeat count may be specified either by an immediate value (up to 31

times) or by the content of the Repeat Count ( bits 12 to 0) i n the MAC Repeat Word (MRW). If

the Repeat Count equals “N” the instruction will be executed “N+1” times. At each iteration of a cumulative instruction the Repeat Count is tested for zero. If it is zero the instruction is terminated else the Repeat Count is decremented and the instruction is repeated. During such a repeat sequence, the Repeat Flag in MRW is set until the last execution of the repeated instruction.

The syntax of repeated instructions is shown in the following examples:

In example 1, the instruction is repeated according to a 5-bit immediate value. The Repeat Count in MRW is automatically loaded with this value minus one (MRW=23).

In this example, the instruction is repeated according to the Repeat Count in MRW . Notice that due to the pipeline processing at least one instruction should be inserted between the write of MRW and the next repeated instruction.

Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence, the sequence is stopped and the i nterrupt routine i s e xecuted. The repeat sequence resumes at the end of the interrupt routine. During the interrupt, MR remains set, indicating that a repeated instruction has been interrupted and the Repeat Count holds the number (minus 1)

1 Repeat #24 times

CoMAC[IDX0+],[R0+] ; repeated 24 times

1 MOV MRW, #00FFh ; load MRW

NOP ; instruction latency Repeat MRW times CoMACM [IDX1-],[R2+] ; repeated 256 times

Page 21

21/77

ST10R272L - MULTIPLY-ACCU MULATE UNIT (MAC)

of repetition that remains to complete the sequence. If the R epeat Unit is us ed in the i nterrupt routine, MRW must be saved by the user and restored before the end of the interrupt routine.

Note The Repeat Count should be used with caution. In this case MR should be written as

0. In general MR should not be set by the user otherwise correct instruction processing can not be guaranteed.

MAC interrupt

The MAC can generate an interrupt according to the value of the status flags C (carry), SV (overf low), E (ex tension) or SL (limit) of the MSW . T he MAC interrupt is globally enabl ed when the MIE flag in MCW is set. When it is enabled the flags C, SV, E or SL can triggered a MAC interrupt when they are set provided that the corresponding mask flag CM, VM, EM or LM in MCW is also set. A MAC interrupt request set the MIR flag in MSW , this flag must be reset by the user during the interrupt routine otherwise the interrupt processing restarts when returning from the interrupt routine.

The MAC interrupt is implemented as a Class B hardware trap (trap number Ah - trap priority I). The associated Trap Flag in the TFR register is MACTRP, bit #6 of the TFR (Remember that this flag must also be reset by the user in the case of an MAC interrupt request).

As the MAC status flags are updated (or eventually written by software) during the Execute stage of the pipeline, the response time of a MAC interrupt request is 3 instruction cycles (see Figure 3). It is the number of instruction cycles required between the time the request is sent and the time the first instruction located at the interrupt vector location enters the pipeline. Note that the IP value stacked after a MAC interrupt does not point to the instruction that triggers the interrupt.

Figure 7 Pipeline diagram for MAC interrupt response time

N N-1 N-2 N-3

N+1 N N-1 N-2

N+2 N+1 N N-1

N+4 TRAP (1) N+2 N+1

I1 TRAP (2) TRAP (1) N+2

I2 I1 TRAP (2) TRAP (1)

N+3 N+2 N+1 N

FETCH DECODE

EXECUTE WRITEBACK

MAC Interrupt Request

Response Time

Page 22

22/77

ST10R272L - INTERRUPT AND TRAP FUNCTIONS

Number representation & rounding

The MAC supports the two’s-complement representation of binary numbers. In this format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one for negative numbers. Unsigned numbers are supported only by multiply/multiplyaccumulate instructions which specifies whether each operand is signed or unsigned.

In two’s complement fractional format, the N-bit operand is represented using the 1.[N-1] format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between -1 and +1-2

-[N-1]

. This format is suppor ted when MP of MCW is set.

The MAC implements ‘two’s complement rounding’. With this rounding type, one is added to the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).

6 INTERRUPT AND TRAP FUNCTIONS

The architecture of the ST10R272L supports s everal mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In a standard interrupt service, program executi on is suspended and a branch to the interrupt service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current CPU activity. A PEC service is a single, byte or word data transfer between any two memory locations, with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except in the continuous transfer mode. When this counter reaches zero , a standard interrupt is performed to the corresponding source-related vector location. PEC services are very well suited, for example, to the transmission or reception of blocks of data. The ST10R272L has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists f or each of the possib le interrupt sources. Via it s related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher priority service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruc tion in combination with an individual trap (interrupt) number.

Page 23

23/77

ST10R272L - INTERRUPT AND TRAP FUNCTIONS

6.1 Interrupt Sources

Source of Interru pt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

Trap Number

External Interrupt 0 CC8IR CC8IE CC8INT 60h 18h External Interrupt 1 CC9IR CC9IE CC9INT 64h 19h External Interrupt 2 CC10IR CC10IE CC10INT 68h 1Ah External Interrupt 3 CC11IR CC11IE CC11INT 6Ch 1Bh GPT1 Timer 2 T2IR T2IE T2INT 88h 22h GPT1 Timer 3 T3IR T3IE T3INT 8Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 90h 24h GPT2 Timer 5 T5IR T5IE T5INT 94h 25h GPT2 Timer 6 T6IR T6IE T6INT 98h 26h GPT2 CAPREL Register CRIR CRIE CRINT 9Ch 27h ASC0 T ransmit S0TIR S0TIE S0TINT A8h 2Ah ASC0 Transmit Buffer S0TBIR S0 T BIE S0 TB IN T 11Ch 47h ASC0 Receive S0RIR S0RIE S0RINT ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT B0h 2Ch PWM Channel 3 PWMIR PWMIE PWMINT FCh 3Fh SSP Interrupt XP1IR X P 1IE X P1I NT 104h 41h PLL Unlock XP3I R XP3IE X P3I NT 10Ch 43h

Table 5 List of possible interrupt sources, flags, vector and trap numbers

Page 24

24/77

ST10R272L - INTERRUPT AND TRAP FUNCTIONS

6.2 Hardware Trap s

Exceptions or error conditions that arise during run-time are called Hardware T raps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual progr am ex ecution. In turn, hardware trap services can not normally be interrupted by standard or PEC interrupts. The following tab le shows all of the possible ex ceptions or error conditions that can arise during run-time:

Exception Condition T rap Flag Trap Vector

Vector Location

Trap Number

Trap Priority

Reset Functions:

Hardware Reset RESET 00’0000

h 00h III

Software Reset RESET 00’0000

h 00h III

Watchdog Timer Overflow RESET 00’0000

h 00h III

Class A Hardware Traps:

Non-Maskable Interrupt NMI NMITRAP 00’0008

h 02h II

Stack Overflow STKOF STOTRAP 00’0010

h 04h II

Stack Underflow STKUF STUTRAP 00’0018

h 06h II

Class B Hardware Traps:

Undefined opcode UNDOPC BTRAP 00’0028h 0A

h I

Protected instruction fault PRTFLT BTRAP 00’0028h 0A

h I

Illegal word operand access ILLOPA BTRAP 00’0028h 0A

h I

Illegal instruction access ILLINA BTRAP 00’0028h 0A

h I

Illegal external bus access ILLBUS B TRAP 00’0028h 0A

h I

MAC trap MACTRP BTRAP 00’0028h 0A

h I

Reserved [2C

h – 3Ch][0Bh – 0Fh]

Software Traps

TRAP Instruction Any [00’0000

– 00’01FC

steps of 4

Any [00

h – 7Fh]

Current CPU Priority

Table 6 Exceptions or error conditions

Page 25

25/77

ST10R272L - PARALLEL PORTS

7 PARALLEL POR TS

The ST10R272L provides up to 77 I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory , while P ort 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ

, HLDA, HOLD) and chip select signals. Port 3 includes

alternate functions of timers, serial interfaces, the optional bus control signal BHE

and the system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

8 EXTERNA L BUS CONTR OLLER

All external memory accesses are performed by the on-chip External B us Controller which can be programmed either to single chip mode when no external memory is required, or to the following external memory access modes:

In the demultiplex ed b us modes, addresses are output on PORT1 and data is input/output on PORT0/P0L, respectively. In the multiplex ed bus modes both addresses and data use PORT0 for input/output.

Memory cycle time, memory tri-state time, length of ALE and read write delay are programmable so that a wide range of different memory types and external peripherals can be used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx register pairs) to access different resources with different bus characteristics. These address windows are arranged hier archically where BUSCON4 ov errides BUSCON3 etc. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 exte r nal CS

signals (4 windows plus default) can be generated to reduce external glue logic.

Access to very slow memories is supported by the READY function. A HOLD

/HLDA protocol is available for bus arbitration so that external resources can be shared with other bu s masters. In slav e mode, the s lave controller can be connec ted to another master controller without glue logic. For applications which require less than 16 MBytes

16-bit data, demultiplexed 16-/18-/20-/24-bit addresses 16-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, demultiplexed 16-/18-/20-/24-bit addresses

Page 26

26/77

ST10R272L - PWM MODULE

of external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte.

9PWM MODULE

A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centrealigned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.

Mode 0 edge aligned

Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU clock/1 20ns 195.3 KHz 48.83KHz 12.21KHz 3.052KHz 762.9Hz CPU clock/64 1.28ns 3.052KHz 762.9Hz 190.7Hz 47.68Hz 11.92Hz

Mode 1 center aligned

Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

CPU clock/1 20ns 97.66KHz 24.41KHz 6.104KHz 1.525KHz 381.5Hz CPU clock/64 1.28ns 1.525Hz 381.5 Hz 95.37Hz 23.84Hz 0Hz

Table 7 PWM unit frequencies and resolution at 50MHz CPU clock

Page 27

27/77

ST10R272L - GENERAL PURPOSE TIMERS

10 GENERAL PURPOSE TIMERS

The GPTs are flexible multifunctional timer/counters used f or time-related tasks such as e vent timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules, GPT1 and GPT2. Each timer in each module m ay operate independently in a number of different modes, or may be concatenated with another timer of the same module.

10.1 GPT1

Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually f or one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode

where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 8 GPT1 timer input frequencies, resolution and periods lists the timer input frequencies, resoluti on and periods f or eac h pre-s caler option at 50MHz CPU cl oc k. T his al so applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD).

In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or ma y be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers f or timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an ex ternal signal or by a selectabl e state transiti on of its toggle latch T3O TL. When both T2 and T4 are configured to alternately reload T3 on opposite state tr ansitions of T 3O T L with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

Page 28

28/77

ST10R272L - GENERAL PURPOSE TIMERS

CPU

=50MHz

Timer input selection

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler Factor

8 16 32 64 128 256 512 1024

Input Frequency

6.25 MHz 3.125 MHz

1.5625 MHz

781 KHz

391 KHz

195 KHz

97.5 KHz

48.83

KHz Resolution 160ns 32 0ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us 20.48 us Period 10.49ms 20 .97 ms 41 .94 ms 83 .88ms 168m s 336ms 672ms 1.342s

Table 8 GPT1 timer input frequencies, resolution and periods

Figure 8 GPT1 block diagram

2n n= 3 ...10

n= 3 ...10

T2EUD

T2IN

CPU Clock

T3IN

T4IN

T3EUD

T4EUD

T2 Mode

T3 Mode

T4 Mode

GPT1 Timer T2

GPT1 Timer T3

GPT1 Timer T4

T3OTL

Reload Capture

U/D

Reload

Capture

Interrupt

Request

Interrupt

Request

Interrupt Request

T3OUT

U/D

Page 29

29/77

ST10R272L - GENERAL PURPOSE TIMERS

10.2 GPT2

The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable prescaler or with e xternal signals. The count direction (up/down) for each timer is programmable by software or altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of T6OT L may be used to cloc k timer T5, or ma y be output on a port pin T6OUT. The overflow s/underflows of timer T6 reload the CAPREL register. The CAPREL register captures the contents of T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performedwithout software overhead.

CPU

=50MHz

Timer input selection

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler Factor

4 8 16 32 64 128 256 512

Input Frequency

12.5 MHz 6.25 MHz 3.125 MHz

1.563 MHz

781 KHz

391 KHz

195 KHz

97.6

KHz Resolution 80ns 160 ns 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us Period 5.24ms 10.49ms 20.97m s 41. 94m s 83.88ms 167.7ms 335.5m s 671ms

Table 9 GPT2 timer in put frequencies, resolution and periods

Page 30

30/77

ST10R272L - SERIAL CHANNELS

11 SERIAL CHANNELS

Serial communication with other microcontrollers, proces sors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).

ASC0 A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3

separate interrupt vectors are provided for transmission, reception, and erroneous reception. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. Fo r multiprocessor comm unication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode).

In synchronous mode, the ASC0 transm its or receives bytes (8 bits) synchronously to a s hift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can be generated automatically on transmission, or checked on reception. Framing error detection recognizes data frames with missing stop bits. An overrun error is generated if the last character received was not read out of the receive buffer register at the time the reception of a new character is complete.The table below lists

Figure 9 GPT2 block diagram

2n n=2...9

n=2...9

T5EU D

T5IN

CPU Clock

T6IN

T6EUD

T5 Mode

T6 Mode

GP T2 Timer T5

GPT2 Timer T6

U/D

Interrupt Request

U/D

GPT2 CAPREL

T60TL

Toggle FF

T6OUT

CAPIN

Reload

Inte rr up t Request

Capture

Clear

Inte rr up t Request

Page 31

31/77

ST10R272L - SERIAL CHANN ELS

various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate.

SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated b y the SSP. The SSP can start shifting with the LSB or with the MSB and is used to select shifting and latching clock edges, and clock polarity . Up to two chip select lines may be activ ated in order to direct data transf ers to one or both of two peripheral devices.

When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose IO. Note that the segment address selection done via the system st art-up configuration during reset has priority and overrides the SSP functions on these pins.

S0BRS = ‘0’, f

CPU

= 50MHz S0BRS = ‘1’, f

CPU

= 50MHz

Baud Rate (Baud)

Deviation Error Reload Value

Baud Rate (Baud)

Deviation Error Reload V al ue

1562500 0.0% / 0.0% 0000

/ 0000

1041666 0.0% / 0.0% 0000H / 0000

56000 +3.3% / -0.4% 001AH / 001BH56000 +3.3% / -2.1% 0011H / 0012

38400 +1.7% / -0.8% 0027H / 0028

38400 +0.5% / -3.1% 001AH / 001B

19200 +0.5% / -0.8% 0050H / 0051

19200 +0.5% /-1.4% 0035H / 0036

9600 +0.5% / -0.1% 00A1H/ 00A2

9600 +0.5% / -0.5% 006BH / 006C

4800 +0.2% / -0.1% 0144H / 0145

4800 0.0% / -0.5% 00D8H / 00D9

2400 0.0% / -0.1% 028AH / 028BH2400 0.0% / -0.2% 01B1H / 01B2

1200 0.0% / -0.1% 0515H / 0516

1200 0.0% / -0.1% 0363H / 0364

600 0.0% / 0.0% 0A2BH / 0A2CH600 0.0% / -0.1% 06C7H / 06C8

190 +0.4% /+0.4% 1FFFH / 1FFFH75 0.0% / 0.0% 363FH / 3640

127 +0.1% / +0.1% 1FFFH / 1FFF

Table 10 Common ly used bau d rates, required reload values and deviation errors

SSPCKS Value Synchronous baud rate

000 SSP clock = CPU clock divided by 2 25 MBit/s 001 SSP clock = CPU clock divided by 4 12.5 MBit/s 010 SSP clock = CPU clock divided by 8 6.25 MBit/s

Table 11 Synchronous b a ud rate and SSPCKS reloa d values

Page 32

32/77

ST10R272L - WATCHDOG TIMER

12 WATCH DO G TIMER

The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the controller . The Watchdog Timer is always enabled after device reset and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this

way, the chip’s start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to maintain the Watchdog Timer, it will overflow generating an internal hardware reset and pulling the RSTOUT

pin low to reset external hardware

components. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by

128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock rounded to 3 significant figures.

011 SSP clock = CPU clock divided by 16 3.13 MBit/s 100 SSP clock = CPU clock divided by 32 1.56 MBit/s 101 SSP clock = CPU clock divided by 64 781 KBit/s 110 SSP clock = CPU clock divided by 128 391 KBit/s 111 SSP clock = CPU clock divided by 256 195 KBit/s

Reload value in WDTREL

Prescaler for f

CPU

2 (WD TIN = ‘0’ ) 128 (WDTIN = ‘ 1 ’)

10.24 µs 655 µs

2.62 ms 168 ms

Table 12 Watchdog timer range

SSPCKS Value Synchronous baud rate

Table 11 Synchronous b a ud rate and SSPCKS reloa d values

Page 33

33/77

ST10R272L - SYSTEM R ESET

13 SYSTEM RESET

The following type of reset are implemented on the ST10R272L: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock

signal on XTAL1 as it is not internally resynchronized, it resets the microcontroller into its default reset state. Asynchronous reset is required on chip power-up and can be used during catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before exiting the reset condition, therefore, only the entry to hardware reset is asynchronous.

Synchronous hardware reset (warm reset): A war m synchronous hardware reset is triggered when the reset input signal RSTIN

is latched low and Vpp pin is high. The I/Os are

immediately (asynchronously) set in high impedance, RSTOUT

is driven low. After RSTIN negation is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. Then, the internal reset sequence is active for 1024 TCL (512 CPU clock cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 5 in SYSCON register), RSTIN

pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state . Note that after all reset sequence, bit BDRSTEN is cleared. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN becomes inactive.

Software reset: The reset sequence can be trigger ed at any time by the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. As for a synchronous hardware reset, the reset sequence lasts 1024 TCL (512 CPU clock cycles), and drives the RSTIN

pin low.

Watchdog timer reset: When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle does not use READY

, or if READY is sampled active (low) after the

programmed waitstates. When READY

is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. The watchdog reset cannot occur while the ST10R 272L is in bootstrap loader mode.

Bidirectional reset: This reset makes the watchdog timer reset and software reset externally visible. It is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. Therefore, the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL.

Page 34

34/77

ST10R272L - POWER REDUC TION MODES

14 POWER REDUCTION MODES

Two different power reduction modes with different levels of power reduction can be entered under software control.

In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request.

In Po wer Do wn mod e both the CPU and the peripheral s are stopped. P o wer Down mode can now be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins.

All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low f or negativ e polarity, or driven high for positive polarity) during the last bus access.

15 SPECIA L FUNCTION REGI STERS

The following table lists all ST10R272L SFRs in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.

An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed by its physical address (using the Data Page Pointers), or by its short 8-bit address (without using the Data Page Pointers).

Name

Physical Address

8-Bit Address

Description

Reset Value

ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h ADDRSEL3 FE1Ch 0E h Address Select Register 3 0000h ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0XX0h BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4A h 25 h GPT2 Capture/Reload Register 0000h CC8IC b FF88h C4h EX0IN Interrupt Control Register 0000h

Table 13 Special functional r e gisters

Page 35

35/77

ST10R272L - SPECIAL FUNCTION REGISTERS

CC9IC b FF8Ah C5h EX1IN Interrup t Control Register 0000h CC10IC b FF8Ch C6h EX2IN Interrup t Control Register 0000h CC11IC b FF8Eh C7h EX3IN Interrupt Control Register 0000h CP FE10h 08h CPU Context Pointer Register FC00h CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h CSP FE08h 04h CP U Code Segment Pointer Register (read only) 0000h DP0L b F100h E 80h P 0L Direction Control Register 00h DP0H b F102h E 81h P0h Direction Control Register 00h DP1L b F104h E 82h P1L Direction Control Register 00h DP1H b F106h E 83h P1h Direction Control Register 00h DP2 b FFC2h E1h Port 2 Direction Control Register -0--h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Control Register 00h DP6 b FFCEh E7h Port 6 Direction Control Register 00h DP7 b FFD2h E9h Port 7 Direction Control Register -0h DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10 bits) 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10 bits) 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10 bits) 0002h DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10 bits) 0003h EBUSCON b F10Eh E 87H Extended BUSCON register 0000h EXICON b F1C0h E E0h External Interrupt Control Register 0000h IDCHIP F07Ch E 3Eh Dev ice Identifier Register 1101h IDMANUF F07Eh E 3Fh Manufacturer/Process Identifier Register 0201h IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 0000h IDPROG F078h E 3Ch Programming Voltage Identifier Register 0000h IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h

Name

Physical Address

8-Bit Address

Description

Reset Value

Table 13 Special functional r e gisters

Page 36

36/77

ST10R272L - SPECIAL FUNCTION REGISTERS

IDX1 b FF0Ah 85h MAC Unit Address Pointer 1 0000h MAH FE5Eh 2Fh MAC Unit Accumulator - High Word 0000h MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h MCW FF DCh EEh MAC Unit Control Word 0000h MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h

MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MSW b FF DEh EFh MAC Unit Status Word 0200h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register -0--h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h ODP6 b F1CEh E E7h Port 6 Open Drain Control Register 00h ODP7 b F1D2h E E9h Port 7 Open Drain Control Register -0h ONES FF1E h 8Fh Constant Value 1’s Register (read only) FFF Fh P0L b FF00 h 80h Port 0 Low Register (Lower half of PORT0) 00h P0H b FF02h 81 h Port 0 High Register (Upper half of PORT0) 00h P1L b FF04 h 82h Port 1 Low Register (Lower half of PORT1) 00h P1H b FF06h 83 h Port 1 High Register (Upper half of PORT1) 00h P2 b FFC0h E0h Port 2 Register (4 bits) -0--h P3 b FFC 4h E2 h Port 3 Register 0000h P4 b FFC8h E4h Port 4 Register (8 bits) 00h P5 b FFA2h D1h Port 5 Register (read only) XXXXh P6 b FFCCh E6h Port 6 Register (8 bits) 00h P7 b FFD0h E8h P ort 7Register (4 bits) -0h PECC0 FEC0h 60h P EC Channel 0 Control Register 0000h PECC1 FEC2h 61h P EC Channel 1 Control Register 0000h

Name

Physical Address

8-Bit Address

Description

Reset Value

Table 13 Special functional r e gisters

Page 37

37/77

ST10R272L - SPECIAL FUNCTION REGISTERS

PECC2 FEC4h 62h P EC Channel 2 Control Register 0000h PECC3 FEC6h 63h P EC Channel 3 Control Register 0000h PECC4 FEC8h 64h P EC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h PSW b FF10h 88h CPU Program Status Word 0000h PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E BFh PWM M odule Interrupt Control Register 0000h QR0 F004h E 02h MAC Unit Offset Register R0 (8 bits) 00h QR1 F006h E 03h MAC Unit Offset Register R1 (8 bits) 00h QX0 F000 h E 00h MAC Unit Offset Register X0 (8 bits) 00h QX1 F002 h E 01h MAC Unit Offset Register X1 (8 bits) 00h RP0H b F108 h E 84h System Start-up Configuration Register (Rd. only) XXh S0BG FEB4h 5Ah Serial Channel 0 baud rate generator reload reg 0000h S0CON b FFB0h D8h Ser ial Channel 0 Control Register 0000h S0EIC b FF70 h B8h Ser ial Channel 0 Error Interrupt Control Register 0000h S0RBUF FEB2h 59h Serial Channel 0 receive buffer reg. (rd only) XXh S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Reg. 00 00h S0TBIC b F19Ch

CEh Serial Channel 0 transmit buffer interrupt control

reg

0000h

S0TBUF FEB0h 58h Serial Channel 0 transmit buffer register (wr only) 00h S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Regis-

ter

0000h

Name

Physical Address

8-Bit Address

Description

Reset Value

Table 13 Special functional r e gisters

Page 38

38/77

ST10R272L - SPECIAL FUNCTION REGISTERS

SP FE12h 09h CPU System Stack Pointer Register FC00h SSPCON0 EF00h X --- SSP Control Register 0 0000h SSPCON1 EF02h X --- SSP Control Register 1 0000h SSPRTB EF04h X --- SSP Receive/Transmi t Bu ffer XXXXh SSPTBH EF06h X --- SSP Transmit Buffer High XXXXh STKOV FE14 h 0Ah CPU Stack Overflow Pointer Register FA00h STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h SYSCON b FF12h 89h CP U System Configuration Register

0xx0h

T2 FE40h 20 h GPT1 Timer 2 Register 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register 0000h T3 FE42h 21 h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register 0000h T4 FE44h 22 h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5 FE46h 23 h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24 h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h TFR b FFA Ch D6h Trap Flag Register 0000h WDT FEAEh 57h Watchdog Timer Register (read only) 0000h WDTCON FFAEh D7h Watchdog Timer Control Register

000xh

Name

Physical Address

8-Bit Address

Description

Reset Value

Table 13 Special functional r e gisters

Page 39

39/77

ST10R272L - SPECIAL FUNCTION REGISTERS

Note 1. The sy stem configuration is selected during reset. Note 2. Bit WDTR indicates a watchdog timer triggered reset.

XP1IC b F18Eh E C7h SSP Interrupt Control Register 0000h XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register 0000h ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h

Name

Physical Address

8-Bit Address

Description

Reset Value

Table 13 Special functional r e gisters

Page 40

40/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16 ELECTRICAL CHARACTERIST ICS

16.1 Absolute Maximum Ratings

• Ambient temperature under bias (T

):......................................................... -40 to +85 °C

• Storage temperature (T

):.......................................................................– 65 to +150 °C

• Voltage on V

pins with respect to ground (VSS):..................................... – 0.5 to +4.0 V

• Voltage on any pin with respect to ground (V

): ................................ –0.5 to VDD +0.5 V

• Voltage on any 5V tolerant pin with respect to ground (V

): .......................–0.5 to 5.5 V

• Voltage on any 5V fail-safe pin with respect to ground (V

): .......................–0.5 to 5.5 V

• Input current on any pin during overload condition: ..................................–10 to +10 mA

• Absolute sum of all input currents during overload condition: .............................|100 mA|

• Power dissipation:................................................................................. ....................1.0 W

Note Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V

IN>VDD

or VIN<VSS) the voltage on pins with respect to ground

) must not exceed the values defined by the Absolute Maximum Ratings.

The parameters listed in thi s section represent both the ST10R272L controller characteristics and the system requirements. To aid parameters interpretation in design evaluation, the a symbol column is marked:

CC for Controller Characteristics: The ST10R272L logic provides signals with the

respective timing characteristics.

SR for System Requirement: The external system must provide signals with the

respective timing characteristics to the ST10R272L.

Page 41

41/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Remarks on 5 volt tolerant (5T ) and 5 v olt fail-safe (5S) pins

The 5V tolerant input and output pi ns can sustain an absol ute maximum exte rnal voltage of

5.5V. However, signals on unterminated bus lines might have overshoot above 5.5V, presenting

latchup and hot carrier ris ks. Whi le these r isks are under evaluation, observe the followi ng security recommendations:

• Maximum peak voltage on 5V tolerant pin with respect to ground (V

)= +6 V

• If the ringing of the external signal exceeds 6V, then clip the signal to the 5V supply.

Power supply failure condition

The power supply failure condition is a state where the chip is NOT supplied but is connected to active signal lines. There are several cases:

• 3.3V external lines on 3.3V (3T) pin on the non powered chip:............... NOT Acceptable

• 3.3V external lines on 5V tolerant (5T) pin on the non powered chip:............. Acceptable

The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.

• 3.3V external lines on 5V fail-safe (5S) pin on the non powered chip: ............Acceptable

The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.

• 5.5V external lines on 5V tolerant (5T) pin on the non powered chip:............. Acceptable

For VERY SHORT times only: the buffers do not leak (external signals not altered) but there is a fast degr adati on of the gate oxides in the buffers . The total maxim um time under this stress condition is 2 days. This limits this configuration to short power-up/down sequences. For 10 year life time, the maximum duty factor is 1/1800 allowing e.g. a maximum stress duration of 48 seconds per day.

• 5.5V external lines on 5V fail-safe (5S) pin on the non powered chip: ............Acceptable

• 6V transient signals on 5V tolerant (5T) pin on the non powered chip:...NOT Acceptable

• 6V transient signals on 5V fail-safe (5S) pin on the non powered chip:.......... Acceptable

Page 42

42/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.2 DC Characteristics

= 3.3V ± 0.3V VSS = 0 V Reset active TA = -40 to +85 °C

Parameter Symbol

Limit Values

Unit Test Condition

min. max.

Input low voltage

SR – 0.3 0.8 V –

Input high voltage (all except RSTIN

and XTAL1)

SR 2.0

+ 0.3

V–

Input high voltage RSTIN,

RPD

IH1

0.6

+ 0.3

V–

Input high voltage XTAL1

IH2

0.7

+ 0.3

V–

Output low voltage (ALE, RD

, WR, BHE, CLKOUT,

RSTIN

,RSTOUT, CSX)

CC – 0.4 V

= 4 mA

Output low voltage (all other outputs)

OL1

CC – 0.4 V

OL1

= 2 mA

Output high voltage ALE, RD

, WR, BHE, CLKOUT,

RSTIN

,RSTOUT, CSX)

CC 2.4 – V

= –4 mA

Output high voltage

(all other outputs)

OH1

CC 2.4 – V

= – 2mA

Input leakage current (3T pins)

CC – ±10 µA

0 V<

IN<VDD

Input leakage current (5T, 5S pins)

OZ1

CC – ±10

±100

µA µA

0 V<

IN<VDD

VDD<VIN<5.0V

RSTIN pull-up resistor

RST

CC 20 300 kΩ

= 0 V

Read/Write pullup current

RWH

–-40µA

OUT

= 2.4 V

Read/Write pullup current

RWL

-500 – µA

OUT

= 0.4 V

ALE pulldown current

ALEL

40 – µA

OUT

= 0.4 V

ALE pulldown current

ALEH

–500µAV

OUT

= 2.4 V

Port 6 (C S

) pullup current

P6H

–-40µAV

OUT

= 2.4 V

Port 6 (C S

) pullup current

P6L

-500 – µA

OUT

= 0.4 V

Table 14 DC characteristics

Page 43

43/77

ST10R272L - ELECTRICAL CHARACTERISTICS

PORT0 configuration current

P0H

–-4µAVIN = V

IHmin

P0L

-50 – µAVIN = V

ILmax

RPD pulldown current

RPD

100 500 µAV

OUT

= V

XTAL1 input current

CC – ±20 µA

0 V <

< V

Pin capacitance

(digital inputs/outputs)

CC – 10 pF

f = 1 MHz T

= 25 °C

Power supply current

–15 +

2.5 * f

CPU

in [MHz]

Idle mode supply current

–10 +

0.9 * f

CPU

RSTIN

= V

IH1

CPU

in [MHz]

Power-down mode supply current

PD 8

–200 µA

= 3.6 V

1) This specification is not valid for outputs which are switched to open drain mode. In this case the resp ec ti ve out pu t w ill fl oa t and the re su lti n g vo ltage comes from the extern al c ir c uitry .

2) This specification is only valid during reset, or interruptible power-down mode, after reception of an exte r nal in t e rr up t signal that will wak e u p the CPU.

3) This specification is only valid during reset, hold or adapt-mode. Port 6 pins are only affected if they are used for CS

output and the open drain function is not enabled.

4) The maximum current may be drawn while the signal line remains inactive.

5) The minimum current must be drawn in order to drive the signal line active.

6) Not 100% tested, guaranteed by design characterization.

7) Supply current is a function of operating frequency as illustrated in Figure 10 on page 44. This parameter is tested at V

max and 50 MHz CPU clock with all outputs disconnected

and all inputs at V

or VIH with an infinite execution of NOP instruction fetched from external memory (16-bit dem ux bus mode, no waitstates, no memory tri-state waitstates, normal ALE).

8) Typical value at 25°C = 20 µA.

9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V

– 0.1 V to VDD, V

REF

= 0 V, all outputs (including pins con-

figured as outputs) disconnected.

Parame ter Symbol

Limit Values

Unit Test Condition

min. max.

Table 14 DC characteristics

Page 44

44/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 10 Supply/idle current vs operating frequency

Supply/idle current [mA]

CPU

[MHz]

10 20

30 40

200

150

100

CCmax

IDmax

Page 45

45/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3 AC Characteristics

Test conditions

•

Input pulse levels:........................................................................................... 0 to +3.0 V

• Input rise and fall times (10%-90%):........................................................................ 2.5 ns

• Input timing reference levels:................................................................................. +1.5 V

• Output timing reference levels:.............................................................................. +1.5 V

• Output load:.................................................................................................see Figure 12

Figure 11 Input waveform s

Figure 12 Output load circuit waveform

≤ 2.5ns

10%

90%

≤ 2.5 ns

10%

90%

0 V

3 V

1.5V

timing ref. points

1.5V 1.5V

timing reference points

ref

IOL = 1mA

= 1mA

From output under test

CL = 50pF

3.3 V

Page 46

46/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 13 Float waveforms

timing reference

VOH - 0.15 V

points

VOL + 0.15 V

LOAD

- 0.15 V

LOAD

+0.15 V

ref

IOL = 5 mA

From output under test

CL = 5 pF

3.3 V

For timing purposes a port pin is no longer floating when a 150 mV change from load voltage occurs, but begins to float when a 150 mV change from the loaded VOH/VOL level occurs.

CL is 5 pF for floating measurements only.

IOH = 5 mA

Page 47

47/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.1 CPU Clock Generation Mechanisms

ST10R2 72L intern al ope ration is c ontrol led by the C PU cloc k f

CPU

. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on the time between two c onsec-

utive edges of the CPU clock, called “TCL” (see figure below). The CPU clock signal can be generated by different mechanism s. The duration of TCLs and

their variation (and also the external timing) depends on the f

CPU

generation mechanism. This

must be considered when calculating ST10R272L timing. The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13

(P0H.7-5).

Figure 14 CPU clock g eneration mechanisms

P0.15-13 (P0H.7-5)

CPU frequency f

CPU

= f

XTAL

* F

External clock input range 1050MHz

Notes

111

XTAL

* 4

2.5 to 12.5 MHz Default configuration

110

XTAL

* 3

3.33 to 16.66 MHz

101

XTAL

* 2

5 to 25 MHz

Table 15 CPU clock generation mechanisms

TCLTCL

CPU

XTAL

CPU

XTAL

Phase Locked Loop Operation (PLL factor=4)

Direct Clock Drive

TCL TCL

CPU

XTAL

Prescaler Operation

Page 48

48/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Prescaler operation

Set when pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of f

CPU

is half the frequency of f

XTAL

and the high and low time of f

CPU

(i.e. the

duration of an individual TCL) is defined by the period of the input clock f

XTAL

The timings listed in the AC characteristics that refer to TCLs therefore can be calculated using the period of f

XTAL

for any TCL.

Note that if the bit OWDDIS in SYSCON register is cleared, the PLL r uns on i ts free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.

Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset, the on-chip phase locked loop is disabled and the CPU clock is driven from the internal oscillator with the input clock signal. The frequency of f

CPU

directly follows the frequency of f

XTAL

so the high and low time of f

CPU

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock f

XT AL

The TCL timing below must be calculated using the minimum possible TCL which can be calculated by the formula:

For two consecutive TCLs the deviation caused by the duty cycle of f

XTAL

is compensated so

the duration of 2TCL is always 1/f

XTAL

. Therefore, the minimum value TCL

min

has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: .

100

XTAL

* 5

2 to 10 MHz

011

XTAL

* 1

1 to 50 MHz

Direct drive

010

XTAL

* 1.5

6.66 to 33.33 MHz

001

XTAL

/ 2

2 to 100 MHz CP U clock via 2:1 prescaler

000

XTAL

* 2.5 4 to 20 MHz

1) The maximum depends on the duty cycle of the external clock signal. The maximum input frequency is 25 MHz when using an ex ternal crystal oscillator, but higher frequencies can be applied with an external clock source.

P0.15-13 (P0H.7-5)

CPU frequency f

CPU

= f

XTAL

* F

External clock input range 1050MHz

Notes

Table 15 CPU clock generation mechanisms

TCL

min

1 f

XTAL

⁄ DC

min

× DC(= duty cycle)=

2TCL 1 f

XTAL

⁄=

Page 49

49/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Note The addr ess float timings in M u ltiplexed bus mode (t11 and t45) use

instead of .

Oscillator Watchdog (OWD)

When the clock option s elected i s direc t driv e or dir ect driv e w ith prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows:

After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, set bit 4 of SYSCON register OWDDIS.

When the OWD is enabled, the PLL runs on its free-running frequency and increments the Oscillator Watchdog counter. On each transition of the XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not s witch back to the e xternal clock ev en if a valid e xternal clock e xits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input.

When the OWD is disabled, the CPU clock is always f ed from the oscillator input and the PLL is switched off to decrease power supply current.

Phase locked loop

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. f

CPU

= f

XTAL

* F). With

every F’th transition of f

XT AL

the PLL circuit synchronizes the CPU clock to the input clock. In

this way, f

CPU

is constantly adjusted so it is locked to f

XTAL

. The slight variation causes a jitter

of f

CPU

which affects individual TCL duration.Therefore, AC characteri stics that refer to TCLs

must be calculated using the minimum possible TCL. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL constantly

adjusts its output frequency, it corresponds to the applied input frequency (cr ys tal or oscillator). The relative de viation for periods of more than one TCL is lower than for one single TCL. For a period of

* TCL the minimum value is computed using the corresponding

deviation D

TCL

max

1 f

XTAL

⁄ DC

max

×= TCL

min

TCL

min

TCL

NOM

1 DN100⁄–()×=

4N15⁄–()%[]±=

Page 50

50/77

ST10R272L - ELECTRICAL CHARACTERISTICS

where N = number of consecutive TCLs and 1 ≤ N ≤ 40. So f or a period of 3 TCLs (i.e. N = 3):

and

PLL jitter is an important factor for b us cycles using wai tstates and for the operation of timers, serial interfaces, etc. For slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.

Figure 15 Approximated maximum PLL jitter

4315⁄–=

3.8%=

3TCL

min

3TCL

NOM

1 3.8 100⁄–()×=

3TCL

NOM

0.962 36.07nsec @ f c pu=50MHz()×=

3216

M a x .jitter [% ]

This formula is valid for 1<N<40 and 10<f

cpu

<50

Page 51

51/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.2 Memory Cycle Variables

The timing tables below use three variables derived from the BUSCONx registers and represent programmed memory cycle characteristics. Table 16 describes how these variabl es are computed.

Description Symbol Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time Waitstates

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

Table 16 Memory cycle variables

Page 52

52/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.3 Multiplexed Bus

= 3.3 V ± 0.3 V VSS = 0 V

= -40 to +85 °C

= 50 pF

ALE cycle time = 6 TCL + 2

+ tC + tF (60 ns at 50-MHz CPU clock without waitstates)

Parameter Symbol

Max. CPU Clock = 50 MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

ALE high time

7 +

–

TCL - 3 +

–ns

Address (P1, P4), BHE setup to ALE

3 +

–

TCL - 7 +

–ns

Address (P0) setup to ALE

5 +

–

TCL - 5 +

–ns

Address hold after ALE

5 +

–

TCL - 5 +

–ns

ALE falling edge to RD

(with RW-delay)

5 +

–

TCL - 5 +

–ns

ALE falling edge to RD

(no RW-delay)

-5 +

–

-5 +

–ns

Address float after RD

(with RW-delay)

CC –

–

Address float after RD

(no RW-delay)

CC –

–

TCL + 5

, WR low time

(with RW-delay)

13 +

–

2TCL - 7+

–ns

, WR low time

(no RW-delay)

23 +

–

3TCL - 7 +

–ns

to valid data in

(wit h RW-del ay)

SR –

5 +

– 2TCL - 15

to valid data in

(no RW-delay)

SR –

15 +

– 3TCL - 15

ALE low to va lid data in

SR – 15

+ t

– 3TCL - 15

+ t

Address to valid data in

SR – 20

+ t

– 4TCL - 20

+ t

Table 17 Mul tiplexed bus

Page 53

53/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Data hold after RD rising edge

SR 0 –0 – ns

Data float after RD

rising

edge

12))

SR –

15 +

–

2TCL - 5 +

Data valid to WR

13 +

–

2TCL - 7 +

–ns

Data hold after WR

13 +

–

2TCL - 7+

–ns

ALE rising edge after RD

10 +

–

2TCL - 10 +

–ns

Address hold after RD

, WR

10 +

–

2TCL - 10 +

–ns

Latched CS

setup to ALE

-7 +

3 + t

-7 + t

3 + t

Unlatched CS

setup to

ALE

38u

3 +

–

TCL - 7 +

–ns

Latched CS

low to V alid

Data In

SR – 13

tC + 2t

– 3TCL - 17

tC + 2t

Unlatched CS

low to Valid

Data In

39u

SR – 23

tC + 2t

– 4TCL - 17

tC + 2t

Latched CS

hold after RD,

20 +

–

3TCL - 10 +

–ns

Unlatched CS

hold after

, WR

40u

10 +

–

2TCL - 10 +

–ns

ALE fall. edge to RdCS

WrCS

(with RW delay)

7 +

–

TCL - 3 +

–ns

ALE fall. edge to RdCS

WrCS

(no RW delay)

-3 +

–

-3 +

–ns

Address float after RdCS (with RW delay)

CC –

–

Address float after RdCS (no RW delay)

CC –

–

TCL + 3

Parameter S ymbol

Max. CPU Clock = 50 MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

Table 17 Mul tiplexed bus

Page 54

54/77

ST10R272L - ELECTRICAL CHARACTERISTICS

RdCS to Valid Data In (with RW delay)

SR –

3 +

– 2TCL - 17

RdCS

to Valid Data In

(no RW delay)

SR –

13 +

– 3TCL - 17

RdCS

, WrCS Low Time

(with RW delay)

13 +

–

2TCL - 7+

–ns

RdCS

, WrCS Low Time

(no RW delay)

23 +

–

3TCL - 7+

–ns

Data valid to WrCS

10 +

–

2TCL - 10 +

–ns

Data hold after RdCS

SR0–0 – ns

Data float after RdCS

1 2

SR –

13 +

–

2TCL - 7 +

Address hold after RdCS

, WrCS

10 +

–

2TCL - 10 +

–ns

Data hold after WrCS

10 +

–

2TCL - 10 +

–ns

1) Output loading is specified using Figure 13 (CL = 5 pF).

2) This delay assumes that the fo llowing bus cycle is a multiplexe d bus cycl e. If n ext bus cycl e is demultiplexed, refer to demuxultiplexed equivalent AC timing.

Parameter Symbol

Max. CPU Clock = 50 MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

Table 17 Mul tiplexed bus

Page 55

55/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 16 External memory cycle:

multiplexed bus, with/witho ut read/write delay, normal AL E

Data In

Data Out

Address

ALE

CSx

BUS

Read Cycle

BUS

Write Cycle

WR,

WRL

, WRH

19m

CLKOUT

Address

A23-A16

(A15-A8)

BHE

Address

39u

38u

40u

Page 56

56/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 17 External memory cycle:

multiplexed bus, with/without read/write delay, extended ALE

Data Out

Address

Data In

Address

ALE

Write Cycle

WRL,

WRH

6d/b

Read Cycle

BUS

19m

CSx

CLKOUT

A23-A16

(A15-A8)

BHE

40u

39u

38u

Page 57

57/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 18 External memory cycle:

multiplexed bus, with/witho ut read/write delay, normal AL E, read/write chip select

Data In

Data Out

Address

ALE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WrCSx

52m

CLKOUT

Address

A23-A16

(A15-A8)

BHE

6b/d

Address

Page 58

58/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 19 External memory cycle:

multiplexed bus, with/without read/write delay, extended ale, read/write chip select

Data Out

Address

Data In

Address

ALE

RdCSx

Write Cycle

WRL,

WRH

6d/b

Read Cycle

BUS

19m

A23-A16

(A15-A8)

BHE

CLKOUT

Page 59

59/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.4 Demultiplexed Bus

= 3.3 V ± 0.3 V VSS = 0 V

= -40 to +85 °C

= 50 pF

ALE cycle time = 4 TCL + 2

+ tC + tF (40 ns at 50 MHz CPU clock without waitstates)

Parameter Symbol

Max CPU Clock 50MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

ALE high time

7 +

–

TCL - 3 +

–ns

Address (P1, P4), BHE setup to ALE

3 +

–

TCL - 7 +

–ns

Address setup to RD

, WR

(with RW-delay)

13 +

–

2TCL - 7 +

–ns

Address setup to RD

, WR

(no RW-delay)

3 +

–

TCL - 7 +

–ns

, WR low time

(with RW-delay)

13 +

–

2TCL - 7 +

–ns

, WR low time

(no RW-delay)

23 +

–

3TCL - 7 +

–ns

to valid data in

(wit h RW-del ay)

SR –

5 +

– 2TCL - 15

to valid data in

(no RW-delay)

SR –

15 +

– 3TCL - 15

ALE low to va lid data in

SR –

15 +

+ t

– 3TCL - 15

+ t

Address to valid data in

SR –

20 +

– 4TCL - 20

+ t

Data hold after RD rising edge

SR 0 – 0 – ns

Data float after RD

rising

edge (with RW-delay)

1) 2)

SR – 15

+ 2t

–2TCL - 5

+ 2t

Data float after RD

rising

edge (no RW-delay)

1 2

SR –

5 +

–TCL - 5

+ 2t

Data valid to WR

13 +

–

2TCL - 7 +

–ns

Table 18 Demultiplexed bus

Page 60

60/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Data hold after WR

5 +

–

TCL - 5 +

–ns

ALE rising edge after RD

-5 +

–

-5 +

–ns

Address hold after RD

, WR

CC 0 (no t

-9+t

F (tF>0)

–

0 (no

)

-9 +

F (tF>0)

–ns

Address hold after WRH

28h

CC -1 (no t

-8

F (tF>0)

–

-1 (no

)

-8 +

F (tF>0)

–ns

Latched CS

setup to ALE

-7 +

3 + t

-7 + t

3 + t

Unlatched CS

setup to ALE

38u

3 +

–

TCL - 7 +

–ns

Latched CS

low to V alid

Data In

SR – 13

tC + 2t

– 3TCL - 17

tC + 2t

Unlatched CS

low to Valid

Data In

39u

SR – 23

tC + 2t

– 4TCL - 17

tC + 2t

Latched CS

hold after RD,

3 +

–

TCL - 7 +

–ns

Unlatched CS

hold after RD,

41u

CC 0 (no t

-7

F (tF>0)

–

0 (no

)

-7 +

F (tF>0)

–ns

Address setup to RdCs

WrCs

(with RW-delay)

13 +

–

2TCL - 7 +

–ns

Address setup to RdCs

WrCs

(no RW-delay)

3 +

–

TCL - 7 +

–ns

RdCS

to Valid Data In

(with RW-delay)

SR –

3 +

–

2TCL - 17 +

RdCS

to Valid Data In

(no RW-delay)

SR –

13 +

–

3TCL - 17 +

RdCS

, WrCS Low Time

(with RW-delay)

11 +

–

2TCL - 9 +

–ns

RdCS

, WrCS Low Time

(no RW-delay)

21 +

–

3TCL - 9 +

–ns

Data valid to WrCS

13 +

–

2TCL - 7 +

–ns

Parameter Symbol

Max CPU Clock 50MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

Table 18 Demultiplexed bus

Page 61

61/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Data hold after RdCS

SR 0 –0 – ns

Data float after RdCS (with RW-delay)

1 2

SR –

13 +

F +

2tA

–2TCL - 7

F + 2tA

Data float after RdCS (no RW-delay)

1 2

SR –

3 +

F+ 2tA

–TCL - 7

F + 2tA

Address hold after RdCS

, WrCS

-5 +

–

-5 +

–ns

Data hold after WrCS

3 +

–

TCL - 7 +

–ns

1) Output loading is specified using Figure 13 with CL = 5 pF.

2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the data bus will only be driven ext ernally when the RD

or RdCs signal becomes active. RW-

delay and

refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus cycle, refer to equival e nt mult i ple xe d AC timing (which are still applicable d ue to au tomati c insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode.

Parameter Symbol

Max CPU Clock 50MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

Table 18 Demultiplexed bus

Page 62

62/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 20 External memory cycle:

demultiplexed bus, with/without read/write delay, no rmal ALE

Data In

Data Out

ALE

CSx

P0 BUS

(D15-D8)

D7-D0

Read Cycle

P0 BUS

(D15-D8)

D7-D0

Write Cycle

WR(L),

WRH

CLKOUT

Address

A23-A16

(A15-A8)

BHE

21d

20d

39u

38u

41u

28, t28h

Page 63

63/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 21 External memory cycle:

demultiplexed bus, with/without read/write delay, extended ALE

Address

ALE

Write Cycle

WR(L),

WRH

20d

CSx

CLKOUT

A23-A16

(A15-A8)

BHE

Data In

P0 BUS

(D15-D8)

D7-D0

Read Cycle

21d

38u

39u

41u

28h

Data Out

P0 BUS

(D15-D8)

D7-D0

Page 64

64/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 22 External memory cycle:

demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select

Data In

Data Out

ALE

P0 BUS

(D15-D8)

D7-D0

Read Cycle

RdCsx

P0 BUS

(D15-D8)

D7-D0

Write Cycle

WrCSx

CLKOUT

Address

A23-A16

(A15-A8)

BHE

68d

53d

Page 65

65/77

ST10R272L - ELECTRICAL CHARACTERISTICS

Figure 23 External memory cycle:

demultiplexed bus, no read/write d e lay, extended ALE, read/write chip select

Address

ALE

RdCSx

Write Cycle

WrCSx

53d

CLKOUT

A23-A16

(A15-A8)

BHE

Data In

P0 BUS

(D15-D8)

D7-D0

Read Cycle

68d

Data Out

P0 BUS

(D15-D8)

D7-D0

Page 66

66/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.5 CLKOUT and READY/READY

= 3.3 V ± 0.3 V VSS = 0 V

= -40 to +85 °C

= 50 pF

Parame ter Symbol

Max. CPU Clock = 50 MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

CLKOUT cycle time

CC 20 20 2TCL 2TCL ns

CLKOUT high time

CC 5 – TCL – 5 – ns

CLKOUT low time

CC 5 – TCL – 5 – ns

CLKOUT rise time

1) Measured between 0.3 and 2.7 volts

CC –

–

CLKOUT fa l l time

CC –

–

CLKOUT rising edge to ALE falling edge

-3 +

5 + t

-3 + t

5 + t

Synchronous READY setup time to CLKOUT

SR 9 – 9 – ns

Synchronous READY hold time after CLKOUT

SR 0 – 0 – ns

Asynchronous READY low time

SR 27 – 2TCL + 7 – ns

Asynchronous READY setup time

2) These timings assure recognition at a specific clock edge for test purposes only.

SR 9 – 9 – ns

Asynchronous READY hold time

SR 0 – 0 – ns

Async. REA DY hold time after RD

, WR high (Demulti-

plexed Bus)

3)2

3) Demultiplexed bus is the worst case. For multiplexed bus, 2TCL should be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the following bus cycle, tF refers to the current bus cycle.

SR 0 0

+ tc+ t

0TCL - 10

+ tc+ t

Table19CLKOUT and READY/READY

Page 67

67/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2 The leading edge of the respective command depends on RW-delay. 3READY

(or READY) sampled HIGH (resp. LOW) at this sampling point generates a

READY controlled waitstate, READY

(resp. READY) sampled LOW (resp. HIGH) at this

sampling point terminates the currently running bus cycle.

4READY

(resp. READY) may be deactivated in response to the trailing (rising) edge of the

corresponding command (RD

or WR).

5 If the Asynchronous READY

(or READY) signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)).

Figure 24 CLKOUT and READY

/READY

Sync

READY

Async

READY

see 6)

CLKOUT

ALE

Sync

READY

Async

READY

waitstate

READY

MUX/Tris ta te 6)

Running cycle 1)

Command

RD, WR

Page 68

68/77

ST10R272L - ELECTRICAL CHARACTERISTICS

6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional

MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero.

7 The next external bus cycle may start here.

Page 69

69/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.6 External Bus Arbitration

= 3.3 V ± 0.3 V VSS = 0 V

= -40 to +85 °C

= 50 pF

Parame ter Symbol

Max. CPU Clock = 50 MHz

Variable CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

HOLD

input setup time

to CLKOUT

15 – 15 – ns

CLKOUT to HLDA

high

or BREQ

low delay

– 10 – 10 ns

CLKOUT to HLDA

low

or BREQ

high delay

– 10 – 10 ns

CSx

release

– 15 – 15 ns

CSx

drive

-3 15 -3 15 ns

Other signals release

– 15 – 15 ns

Other signals drive

-3 15 -3 15 ns

Table 20 External bus arbitration

Page 70

70/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 The ST10R272L will complete the running bus cycle before granting bus access. 2 This is the first opportunity for BREQ

to become active.

3 The CS

outputs will be resistive high (pullup) after t64.

Figure 25 External bus arbitration, releasing the bus

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

Page 71

71/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 This is the last chance for BREQ to trigger the regain-sequence indicated.

Even if BREQ

is activated earlier, the regain-sequence is initiated by HOLD going high.

Please note that HOLD

may also be de-activated without the ST10R272L requesting the

bus.

2 The next ST10R272L driven bus cycle may start here.

Figure 26 External bus arbitration, (regaining the bus)

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

Page 72

72/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.7 External Hardware Reset

= 3.3 V ± 0.3 V VSS = 0 V

TA = -40 to +85 °C

= 50 pF

Parameter Symbol

Max. CPU Clock = 50 MHz

V ari abl e CPU Clock 1/2TCL = 1 to 50 MHz

Unit

min. max. min. max.

Sync. RSTIN

low time

1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available

(about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Configuration is correct on P ORT 0 (abo ut 50 µs for internal pull up de vice s to loa d 50 pF from V

min to VIHmin).

50 – 4 TCL + 10 – ns

RSTIN

low to internal

reset sequence start

4164 16 TCL

internal reset sequence, (RSTIN

internally pulled

low)

1024 1024 1024 1024 TCL

RSTIN

rising edge to inter-

nal reset condition end

4646TCL

PORT0 syste m start-up configuration setup to

RSTIN

rising edge

2))

2) The value of bits 0 (EMU), 1 (ADA PT), 13 to 15 (Clock Configuration) are loaded during

hardware reset as lo ng as i nterna l reset s ignal is act ive, and have an immediate ef fect on the system.

100 – 100 – ns

PORT0 syste m start-up configuration hold after RSTIN

rising edge

1616TCL

Bus signals drive from internal reset end

0 20 0 20 ns

RSTIN

low to signals

release

– 50 – 50 ns

ALE rising edge from internal reset condition end

8888TCL

Async. RSTIN

low time

1500 – 1500 – ns

Table 21 External hardware reset

Page 73

73/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 The ST10R272L is reset in its default state asynchronously with RSTIN. The internal

RAM content may be altered if an internal write access is in progress.

2 On power-up, RSTIN

must be asserted t79 after a stabilized CPU clock signal is available.

3 Internal pullup devices are active on the PORT0 lines, so - input level is high if the respec-

tive pin is left open - or is low if the respective pin is connected to an external pulldown device.

4 The ST10R272L starts execution here at address 00’0000h.

5RSTOUT

stays active until execution of the EINIT (end of initialization) instruction.

6 Activation of the IO pins is controlled by software

Figure 27 External asynchronous hardware reset (power-up reset): Vpp low

RSTIN

PORT1

(Demux Bus)

PORT0

Internal

Reset

Signal

792)

ALE

RD, WR

RSTOUT

Other IOs

Page 74

74/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 The pending internal hold states are cancelled and the current internal access cycle (if

any) is completed.

2RSTIN pulled low by internal device during internal reset sequence. 3 The reset condition may ends here if RSTIN

pin is sampled high after t72.

4 Internal pullup devices are active on the PORT0 lines. Their input level is high if the

respective pin is left open, or is low if the respective pin is connected to an external pulldown device by resistive high (pullup) after t64.

5 The ST10R272L starts execution here at address 00’0000h.

6RSTOUT

stays active until execution of the EINIT (End of Initialization) instruction.

7 Activation of the IO pins is controlled by software.

Figure 28 External synch ro nous hardware reset (warm reset): Vpp high

RSTIN

PORT1

(Demux B us)

711)

PORT0

Internal

Reset

Signal

722)

ALE

RD, WR

RSTOUT

Other IOs

Page 75

75/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.8 Synchronous Serial Port Timing

= 3.3 V ± 0.3 V VSS = 0 V

TA = -40 to +85 °C

= 50 pF

Parameter Symbol

Max. Baudrate

= 25 MBd

Variable Baudrate

= 0.2 to 25 MBd

Unit

min. max. min. max.

SSP clock cycle time

200

CC 40 40 4 TCL 512 TCL ns

SSP clock high time

201

CC 13 – t

200

/2 - 7 – ns

SSP clock low time

202

CC 13 – t

200

/2 - 7 – ns

SSP clock rise time

203

CC – 3 – 3 ns

SSP clock fall time

204

CC – 3 – 3 ns

CE active before shift edge

205

CC 13 – t

200

/2 - 7 – ns

CE inactive after latch edge

206

CC 33 47 t

200

- 7 t

200

+ 7 ns

Write data valid after shift edge

207

CC – 7 – 7 ns

Write data hold after shift edge

208

CC 0 – 0 – ns

Write data hold after latch edge

209

CC 15 25 t

200

/2 - 5 t

200

/2 + 5 ns

Read data active after latch edge

210

SR 27 – t

200

/2 + 7 – ns

Read data setup time before latch edge

211

SR 15 – 15 – ns

Read data hold time after latch edge

212

SR 0 – 0 – ns

Table 22 Synchronous serial por t timing

Page 76

76/77

ST10R272L - ELECTRICAL CHARACTERISTICS

1 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the

falling edge as shift edge (drawn bold).

2 The bit timing is repeated for all bits to be transmitted or received. 3 The active level of the chip enable lines is programmable. This figure uses an active low

CE (drawn bold). At the end of a transmission or reception the CE signal is disab led in si ngle transfer mode. In continuous transfer mode it remains active.

Figure 29 SSP write timing

Figure 30 SSP read timing

204

203

SSPCLK

SSPCEx

SSPDAT

205

207

208

209

206

1st Bit Last Bit2nd Bit

200

201

202

211

SSPCLK

SSPCEx

SSPDAT

209

206

last Wr. Bit

Lst.In Bit

212

1st.In Bit

210

Page 77

77/77

ST10R272L - PACKAGE MECHANICAL DATA

17 PA CKAGE MECHANI CAL DAT A

18 ORDERING INFORMATION

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise under any paten t or patent r i ghts of STMicroelectroni cs. Speci fications me nt i oned in this publication are subj ect to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as crit i cal component s i n l i f e support devices or systems wi thout the exp ress written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an

C system i s granted provided that the system conform s to the I2C Standard Specification as defined by Philips.

STMicroelectron ic s Group of Com panies

Australi a - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Mal ta - Morocco - Singapore - Spain

Sweden - Switzerla nd - United King dom - U.S.A.

http://www.s t. com

Figure 31 Package outline TQFP100 (14 x 14 mm)

Sales type Temperature range P ackage

ST10R272LT1 0°C to 70°C

TQFP100 (14x 14)

ST10R272LT6 -40°C to +85°C

Table 1:

Di m

mm inches

Mi Ty Ma Mi Ty Ma

A1.60.0 A 1.3 1.4 1.4 0.0 0.0 0.0 D 15. 16. 16. 0.6 0.6 0.6 D 13. 14. 14. 0.5 0.5 0.5 D 12. 0.4 E 15. 16. 16. 0.6 0.6 0.6 E 13. 14. 14. 0.5 0.5 0.5 E 12. 0.4 e0.5 0.0

Number of Pins

N25

Datasheet ST10R272LAT1, ST10R272L Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual