Datasheet ST10F167-Q6 Datasheet (SGS Thomson Microelectronics)

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May 1997 1/69

Thisispreliminaryinformation onanewproduct indevelopment orundergoing evaluation. Details are subjectto changewithout notice.

ST10F167

16-BIT MCU WITH 128K BYTE FLASH MEMORY

PRELIMINARY DATASHEET

■ High Performance 16-bit CPU with 4-Stage

Pipeline

■ 100 ns Instruction Cycle Time at 20MHz CPU

Clock

■ 500 ns Multiplication (16 × 16 bit), 1 µs Division

(32 / 16 bit)

■ Enhanced Boolean Bit Manipulation Facilities

■ Additional Instructions to Support HLL and

Operating Systems

■ Register-Based Design with Multiple Variable

■ Single-Cycle Context Switching Support

■ Clock Generation via on-chip PLL or via direct

clock input

■ Up to 16 MBytes Linear Address Space for

Code and Data

■ 2K Bytes On-Chip Internal RAM (IRAM)

■ 2K Bytes On-Chip Extension RAM (XRAM)

■ 128K Bytes On-Chip FLASH memory

■ FLASH Memory organized into 4 banks

independently erasable

■ Programmable External Bus Characteristics for

Different Address Ranges

■ 8-Bit or 16-Bit External Data Bus

■ Multiplexed or Demultiplexed External Address/

Data Buses

■ Five Programmable Chip-Select Signals

■ Hold- and Hold-Acknowledge Bus Arbitration

Support

■ 1024 Bytes On-Chip Special Function Register

Area

■ Idle and Power Down Modes

■ 8-Channel Interrupt-Driven Single-Cycle Data

Transfer Facilities via Peripheral Event Controller (PEC)

■ 16-Priority-Level Interrupt System with 56

Sources, Sample-Rate down to 50 ns

■ 16-Channel 10-bit A/D Converter with 9.7µs

Conversion Time

■ Two 16-Channel Capture/Compare Units

■ 4-Channel PWM Unit

■ Two Multi-Functional General Purpose Timer

Units with 5 Timers

■ Two Serial Channels (Synchronous/

Asynchronous and High-Speed-Synchronous)

■ On-Chip CAN 2.0B Interface with 15 Message

Objects (Full-CAN/Basic-CAN)

■ Programmable Watchdog Timer

■ Up to 111 General Purpose I/O Lines, partly

with Selectable Input Thresholds and Hysteresis

■ Supported by development tools: C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

■ On-Chip Bootstrap Loader

■ 144-Pin PQFP Package

Port 0

Port 1Port 4

Port 6

Port 5 Port 3

Port 2

GPT1

GPT2

ASC usart

BRG

Internal FLASH Memory

CPU-Core

Internal

RAM

Watchdog

Interrupt Controller

PEC

CAN

Port 7

Port 8

External Bus

10-Bit ADC

BRG

SSC

PWM

CAPCOM2

CAPCOM1

OSC.

XRAM

Controller

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Table of Contents

1 INTRODUCTION ......................................................4

2 PINDATA ........................................................... 5

3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . ........................12

4 MEMORYORGANIZATION ............................................13

5 EXTERNALBUSCONTROLLER ........................................13

6 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Flash Memory Programming And Erasure . . . . . . . . . . . . . . . . . . . . . . . .....14

6.2 Flash Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . ...............15

6.3 Flash Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............16

7 CENTRALPROCESSINGUNIT(CPU) ...................................19

8 INTERRUPTSYSTEM ................................................20

9 CAPTURE/COMPARE(CAPCOM)UNITS .................................24

10 GENERALPURPOSETIMER(GPT)UNIT ................................26

11 PWMMODULE ......................................................28

12 WATCHDOGTIMER..................................................29

13 A/DCONVERTER ....................................................29

14 SERIALCHANNELS ..................................................30

15 CAN-MODULE ......................................................30

16 PARALLELPORTS...................................................31

17 INSTRUCTION SET SUMMARY .........................................32

18 BOOTSTRAPLOADER................................................33

19 SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

20 ELECTRICALCHARACTERISTICS ......................................41

20.1 Absolute Maximum Ratings .......................................41

20.2 Parameter Interpretation . . . . . . . . . .................................41

20.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .....................42

20.4 A/D Converter Characteristics . . . . . .................................45

20.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............47

20.5.1 Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 47

20.5.2 Definition of Internal Timing . . ..............................48

20.5.3 DirectDrive ............................................. 48

20.5.4 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . ..................49

20.5.5 ExternalClockDriveXTAL1 ................................50

20.5.6 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

20.5.7 Multiplexed Bus . . . .......................................51

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3/62

20.5.8 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

20.5.9 CLKOUTandREADY.....................................63

20.5.10 External Bus Arbitration . . .................................65

21 PACKAGEMECHANICALDATA ........................................68

22 ORDERINGINFORMATION............................................68

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ST10F167

1 INTRODUCTION

The ST10F167 is a flash derivative of the SGS-THOMSON ST10 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance with high peripheral functionali-

ty and enhanced IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL.

Figure 1.1 Logic Symbol

XTAL1

RSTIN

XTAL2

RSTOUT

NMI EA

READY ALE

RD WR/WRL

Port 5 16-bit

Port 6

8-bit

Port 4

8-bit

Port 3

15-bit

Port 2

16-bit

Port 1

16-bit

Port 0

16-bit

ST10F167

Port 7

8-bit

Port 8 8-bit

AREF

AGND

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ST10F167

2 PIN DATA

ST10F167

P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO

P8.6/CC22IO P8.7/CC23IO

P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3

P8.5/CC21IO

P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0

P5.0AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9

POH.0/AD8 POL.7/AD7 POL.6/AD6 POL.5/AD5 POL.4/AD4 POL.3/AD3 POL.2AD2 POL.A/AD1 POL.0/AD0

EA ALE READY

WR/WRL RD V

P4.7/A23 P4.6/A22/CAN_T

P4.5/A21/CAN_R

D P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16

P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN

AREF

AGND

P5.10/AN10/T6EUD

P5.11/AN11/T5EUD

P5.12/AN12/T6IN

P5.13/AN13/T5IN

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

P2.0/CC0IO

P2.1/CC1IO

P2.2/CC2IO

P2.3/CC3IO

P2.4/CC4IO

P2.5/CC5IO

P2.6/CC6IO

P2.7/CC7IO

P2.8/CC8IO/EX0IN

P2.9/CC9IO/EX1IN

P2.10/CC10IOEX2IN

P2.11/CC11IOEX3IN

P2.12/CC12IO/EX4IN

P2.13/CC13IO/EX5IN

P2.14/CC14IO/EX6IN

P2.15/CC15IO/EX7IN/T7IN

P3.0/T0IN

P3.1/T6OUT

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

VSSNMI

RSTOUT

RSTIN

VSSXTAL1

XTAL2

VDDP1H.7/A15/CC27IO

P1H.6/A14/CC26IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

VSSVDDP1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

POH.7/AD15

POH.6/AD14

POH.5/AD13

POH.4/AD12

POH.3/AD11

POH.2/AD10

POH.1/AD9

VSSV

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

108 107 106 105 104 103 102 101 100

99 98 97

96 95

94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

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ST10F167

Table 2.1 Pin Definitions and Functions

Symbol

Number

Input (I)

Output

(O)

Function

P6.0 –P6.7 1 - 8

...

5 6 7 8

I/O

O ... O

I O O

Port 6 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable for input or output via direction bits. Fora pinconfigured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output

... ... ...

P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA HoldAcknowledge Output P6.7 BREQ BusRequest Output

P8.0 –P8.7 9 - 16

...

I/O

...

I/O

Port 8 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable for input or output via direction bits. Fora pinconfigured as input, the output driver is put into high-impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out

P7.0 –P7.7 19 - 26

... 22 23

... 26

I/O

O ... O

I/O

...

I/O

Port 7 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable for input or output via direction bits. Fora pinconfigured as input, the output driver is put into high-impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

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ST10F167

P5.0-P5.15 27 – 36

39 – 44

39 40 41 42 43 44

I I

I I I I I I

Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

P2.0-P2.15 47 – 54

57 - 64

... 54 57

... 64

I/O

... I/O I/O

... I/O

I I

Port 2 is a16-bit bidirectional I/Oport. It isbit-wise programmable for input or output via direction bits. Fora pinconfigured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out

... ... ...

P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out,

EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,

EX7IN Fast External Interrupt 7 Input

T7IN CAPCOM2 Timer T7 Count Input

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output

(O)

Function

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ST10F167

P3.0P3.13, P3.15

65 – 70, 73 – 80,

65 66 67 68 69 70

73 74

75 76 77 78 79

80 81

I/O I/O I/O

I I

I/O I/O

I/O

O O

I/O

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port.It is bitwise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured aspush/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture P3.8 MRST SSCMaster-Rec./Slave-Transmit I/O P3.9 MTSR SSCMaster-Transmit/Slave-Rec. O/I P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal,

WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock)

P4.0 –P4.7 85 - 92

85 90

I/O

O O

I O O O

Port 4 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable for input or output via direction bits. Fora pinconfigured as input, the output driver is put into high-impedance state. In case ofan externalbus configuration, Port 4 can be used tooutput the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.5 A21 Segment Address Line,

CAN_RxD CAN Receive Data Input

P4.6 A22 Segment Address Line,

CAN_TxD CANTransmit Data Output

P4.7 A23 Most Significant Segment Addr. Line

RD 95 O External Memory Read Strobe. RD is activated for every external

instruction or data read access.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output

(O)

Function

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ST10F167

WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated

for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

READY 97 I Ready Input. When the Ready function is enabled, a high level at

this pin during an external memory access will force the insertion of memory cycletime waitstates until the pin returns to a low level.

ALE 98 O Address Latch Enable Output. Can be used for latching the ad-

dress into externalmemory or an addresslatch inthe multiplexed bus modes.

EA 99 I External Access Enable pin. A low level at thispin duringand after

Reset forces the ST10F167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory.

PORT0: P0L.0P0L.7, P0H.0P0H.7

100-107

108,

111-117

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and

P0H. It is bit-wise programmable for input or output via direction bits. Fora pin configured as input, the output driveris putinto highimpedance state. In caseof an external bus configuration,PORT0 servesas the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width:8-bit 16-bit P0L.0 – P0L.7:D0 – D7D0 - D7 P0H.0 – P0H.7:I/O D8 - D15

Multiplexed bus modes:

Data Path Width:8-bit 16-bit P0L.0 – P0L.7:AD0 – AD7AD0 - AD7 P0H.0 – P0H.7:A8 - A15AD8 - AD15

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output

(O)

Function

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ST10F167

PORT1: P1L.0 – P1L.7, P1H.0 P1H.7

118 –

125

128 –

135

132 133 134 135

I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. Fora pin configured as input, the output driveris putinto highimpedance state. PORT1is used as the 16-bit address bus (A)in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1

XTAL2

138

137

XTAL1: Input to theoscillator amplifier andinput to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, driveXTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

RSTIN 140 I Reset Input withSchmitt-Triggercharacteristics. A lowlevel at this

pin for a specifiedduration while the oscillatoris running resets the ST10F167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS.

RSTOUT 141 O Internal ResetIndicationOutput. This pin isset to alowlevel when

the part isexecuting, eithera hardware, asoftware ora watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.

NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin

causes the CPU to vector tothe NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F167 to go into power down mode. If NMI is high, when PWRDN is executed, the part willcontinue to run in normal mode. If not used, pin NMI shouldbe pulled high externally.

AREF

37 - Reference voltage for the A/D converter.

AGND

38 - Reference ground for the A/D converter.

84 - Flash programming voltage. This pin accepts the programming

voltage for the on-chip flash EPROM of the ST10F167.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output

(O)

Function

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ST10F167

46, 82,

136

- Digital Supply Voltage for internal circuitry: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode

17, 56, 72, 93,

109,126,

144

- Digital Supply Voltage for port drivers: + 5 V during normal operation and idle mode

45, 83,

139

- Digital Ground for internal circuitry.

18, 55, 71, 94,

110,127,

143

- Digital Ground for port drivers.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output

(O)

Function

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ST10F167

3 FUNCTIONAL DESCRIPTION

The architecture of the ST10F167 combines the advantages of both RISC and CISC processors and an advanced peripheral subsystem. The following block diagram gives an overview of the dif-

ferent on-chip components and of the advanced, high bandwidth internal bus structure of the ST10F167.

Figure 3.1 Block Diagram

Internal FLASH Memory

CPU-Core

Internal

RAM

InterruptController

CAN

Module

XRAM

Ext. Bus

Con-

troller

10-Bit

ADC

Port 6 Port 5

Port 3 Port 7

Port 8

Port 2

Port 0

Port 1

Port 4

ASC

(USART)

SSC

PWM

CAPCOM2CAPCOM

GPT1

GPT2

BRG

Watchdog

OSC.

PEC

T2 T3

T5 T6

T7 T8

T0 T1

...

VR02060C

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ST10F167

4 MEMORY ORGANIZATION

Thememory spaceof the ST10F167 is configured in a Von-Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16MBytes. The entirememory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable.

The ST10F167 provides 128KBytes of on-chip flash memory.

2 KBytes of on-chip Internal RAM are provided as astorage for user definedvariables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide(R0 to R15) and/or bytewide(RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for other/future members of the ST10 family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and cannot be used for the system stack or register banks, and is not bit-addressable. The XRAM allows 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided on chip, upto 16 MBytes of external RAM and/or ROM can be connected tothe microcontroller.

5 EXTERNAL BUS CONTROLLER

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

• 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

• 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of theexternal bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable. This gives the choice of a widerange of different types of memories and external peripherals. In addition, different address ranges may be accessed with different bus characteristics. Up to5 externalCS signals (4windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.

For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. Inthis case Port 4 outputs four, twoor no address lines. If an address space of 16 MBytes is used, it outputs all 8 address lines.

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ST10F167

6 FLASH MEMORY

The ST10F167 provides 128KBytes of on-chip, electrically erasable and re-programmable Flash EPROM. The flash memory is organized in 32 bit wide blocks. This allows double word instructions to be fetched in one machine cycle. The flash memory can be used for both code and data storage. The flash memory is organised into four banks of sizes 8K, 24K, 48K and 48Kbytes (table

6.1). Each of these banks can be erased independently. This prevents unnecessary re-programming of the whole flash memory when only a partial re-programming is required.

The first 32K bytes of the FLASH memory are located in segment 0 (0h to 007FFFh) during reset, and include the reset and interrupt vectors. The rest of the FLASH memoryis mapped in segments 1 and 2 (018000h to 02FFFFh). For flexibility, the first 32K bytes of the FLASH memorymay be remapped to segment 1 (010000h to 017FFFh) during initialization. This allows the interrupt vectors to be programmed from the external memory, while retaining the common routines and constants that are programmed into the FLASHmemory.

6.1 Flash Memory Programming And Erasure

The FLASH memory is programmed using the PRESTO F Program Write algorithm. Erasure of the FLASH memory is performed in the program mode using the PRESTO F Erase algorithm.

Timing of the Write/Erase cycles is automatically generated by a programmable timer and comple-

tion is indicated by a flag. A second flag indicates that the VPPvoltage was correct for the whole programming cycle. This guarantees that a good write/erase operation has been carried out.

The FLASH parameters are detailed below.

Table 6.1 FLASH Memory Bank Organisation

Bank Addresses (Segment 0) Size (bytes)

0 1 2 3

000000h to 07FFFh and 018000h to 01BFFFh 01C000h to 027FFFh 028000h to 02DFFFh 02E000h to 02FFFFh

48K 48K 24K

Table 6.2 Flash Parameters

Parameter Units Min Typical Max

Word Programming Time µsec 12.8 12.8 1250 Bank Erasing Time sec 0.5 30 Endurance cycles 1000 Flash Vpp volts 11.4 12.6

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6.2 Flash Control Register (FCR)

Inthe standard operation mode,the FLASH memory can be accessed in the same way as the normal mask-programmable on-chip ROM. All, appropriate, direct and indirect addressing modes can be used for reading the FLASH memory.

All programming or erase operations are controlled via a 16-bit register, the FCR. The FCR is not an SFR or GPR. To prevent inadvertent writing to the FLASH memory, the FCR is locked and inactive during the standard operation mode. The FLASH memory writing mode must be entered, before a valid access to the FCR is provided. This is done via a special key code instruction sequence.

The FCR is virtually mapped into the active address space of the Flash memory. It can only be accessed with direct 16-bit (mem) addressing modes. Since the FCR is neither byte, nor bit-addressable, only word operand instructions can be used for FCR accesses. By default, the FCR can be accessed with any even address from 000000h to 07FFFEh and 018000h to 02FFFEh. If the first 32K byte Block of the FLASH memory is mapped to segment 1, the corresponding even FCR addresses are 010000h to 017FFEh. Note that DPP referencing andDPP contents mustbe considered for FCR accesses. If an FCR access is attempted via an odd address, an illegal operand access hardware trap will occur.

FCR

Flash Control Register Reset Condition: 0000h (Read)

b15 = FWMSET:

Flash Writing Mode Set

. This bit is set to ”1” automatically once the Flash writing mode is entered. To exit from the Flash writing mode, FWMSET must be set to ”0”. Since only word values can be written to FCR, care must be taken that FWMSET is not cleared inadvertently. Therefore, for any command written to FCR (except for the return to the Flash standard mode),

FWMSET must be set to ”1”. Reset condition of FWMSET is ”0”.

b14-b10 = Reserved: these bits are reserved for future development, they must be written to ”0”.

b9-b8 = BE0,1:

Bank erase select.

These bits select the Flash memory bank to be erased. The physical addresses of bank 0 depends on the which Flash memory map has been chosen. In Flash operating modes, other than the erasing mode, these bits arenot significant. At reset BE1,0 are set to ”00”.

b7 = WDWW:

Word/double word write.

Thisbit determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit (WDWW = ”1”). In Flash operation modes, other than the programming mode, this bit is notsignificant. At reset, WDWW is set to “0”.

b6-b5 = CKCTL0,1:

Flash Timer Clock Control.

These twobits control the width (TPRG) of the programming or erase pulses applied to the Flash memory cells during theoperation. TPRGvaries in an inverse ratio to the clock frequency. To avoid putting theFlash memory under critical stress conditions, the width of one single programming or erase pulse and the programming or erase time, must not exceed defined values. Thus the maximum number of programming or erase attempts, depends on the system clock frequency.

RESET state: 00. b4 = VPPRIV:

VPPRevelationbit.

Thisread-only bit reflects the state of the VPPvoltage in the Flash writing mode. If VPPRIV is set to ”0”, this indicates that VPPis below the threshold necessary for reliable programming. The normal reaction to this indication is to check the VPPpowersupply and to then repeat the intended operation. If the VPPvoltage is above a sufficient margin, VPPRIV will be set to ”1”. The reset state of the VPPRIV bit depends on the state of the external VPPvoltage at the VPPpin.

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b3 = FCVPP:

Flash VPPcontrol bit.

This read-only bit indicates that the VPPvoltage fell below the valid threshold value during a Flash programming or erase operation. If FCVPP is set to ”1” after such an operation has finished, it can mean that the operation was not successful. The VPPpower supply should be checked and the operation repeated. If FCVPP is set to ”0”, no critical discontinuity in V

occurred. At reset FCVPP is set to ”0”. b2 = FBUSY:

Flash busy bit.

This read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY is set to ”1” by hardware, as soon as the programming or erase command is given. At reset FBUSY is set to ”0”. Note that this bit position is also occupied by the writeonly bit RPROT.

b2 = RPROT:

Protection enable bit

. This bit set at 1,anded with the OTP protection bit, disables any access to the Flash, by instructions fetched from the external memory space, or from the internal RAM. This write-only bit, is only significant if the general Flash memory protection is enabled. If the protectionis enabled, the setting of RPROT determines whether the Flash protection is active (RPROT=”1”) or inactive (RPROT=”0”). RPROT is theonly FCRbit which can be modified evenin the Flash standard operation mode, but only by anin-

struction executed from the Flash memory itself. At reset,RPROT is set to ”1”. Note that this bit position is alsooccupied by theread-only bit FBUSY.

b1 = FEE:

Flash erase/program selection.

This bit selects the Flash write operation to be performed: erase (FEE=”1”) or programming (FEE=”0”). Together with bits FWE and FWMSET,bit FEE determined the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to ”0”, thesetting of FEE is insignificant. At reset, FEE is set to ”0”.

b0 = FWE:

Flash write/read enable

. This bit determines whether FLASH write operations are enabled (FWE=1) or disabled (FWE=0). By definition, a FLASH write operation can be either programming or erasure. Together with bits FEE and FWMSET, bit FWE determines the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation modeto beselected but does not launch the execution of the selected operation. If bit FWE was set to ”1”, any read accesson a Flash memory location means a particular program-verify or erase-verify read operation. Flashwrite operations are disabled at reset.

6.3 Flash Memory Security

Security and reliability have been enhanced by built-in features: a key code sequence is used to enter the Write/Erase mode preventing false write cycles, a programmable option (set by the programming board) prevents access to the FLASH memory from the internal RAM or from External

Memory. If the security option is set, the FLASH memory can only be accessed from a program within the FLASH memory area. This protection can only bedisabled by instructions executed from the FLASH memory.

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Figure 6.1 PRESTO F Write Algorithm

PCOUNT=PNmax?

PCOUNT=PCOUNT+1

VR02057A

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Figure 6.2 PRESTO F Erase Algorithm

PCOUNT=ENmax?

PCOUNT=PCOUNT+1

VR02057B

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7 CENTRAL PROCESSING UNIT (CPU)

Figure 7.1 CPU Block Diagram

Themain core of theCPU consists of a4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the ST10F167’s instructions can be executed in one machine cycle. This requires 100ns at 20MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycleindependent ofthe number of bits to be shifted. All multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. The ‘Jump Cache’ pipeline optimization,reduces theexecution timeof repeatedly performed jumps in a loop, from 2 cycles to 1 cycle.

The CPU includes an actual register context. This consists of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

FLASH

Internal

RAM

2KByte

R15

General

Purpose

Registers

R15

MDH MLD

Barrel-Shift

Mul./Div.-HW Bit-Mask Gen.

ALU

16-Bit

Context Ptr

STKOV

STKUN

Exec. Unit

Instr. Ptr Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON0 BUSCON1

BUSCON2 BUSCON3 BUSCON4

ADDRSEL 1 ADDRSEL 2

ADDRSEL 3 ADDRSEL 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

ROM

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An efficient instruction set allows maximum use of the CPU. The instruction set is classified into the following groups:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes exist.

8 INTERRUPT SYSTEM

With an interrupt response time from 250ns to 600ns (in the case of internal program execution), the ST10F167 reacts quickly to the occurrence of non-deterministic events

The architecture of the ST10F167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

Ina standard interrupt service, program execution is suspended and a branch to the interrupt vector tableis performed. For aPEC service, just one cycleis ‘stolen’ from the current CPU activity.A PEC service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except for the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are suitedto, for example, the transmission or reception of blocks of data. The

ST10F167 has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source canbe programmed to oneof sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 8.1 shows all of the possible ST10F167 interrupt sources and the corresponding hardwarerelated interrupt flags, vectors, vector locations and trap (interrupt) numbers

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Table 8.1 Interrupt Sources, Flags, Vector and Trap Numbers

Source of Interrupt or

PEC Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh

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Note: Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-

Peripherals are connected, may be used to generate software controlled interrupt requests by setting therespective XPnIR bit.

The ST10F167 provides an excellent mechanism toidentify and to process exceptions or error conditions that arise during run-time, ‘Hardware Traps’. Hardware traps cause an immediate nonmaskable system reaction which is similar to a standard interrupt service(branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except

when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn,hardware trap services can normally not be interrupted by standard or PEC interrupts

Table 8.2 shows all of the possible exceptions or error conditions that can arise during run-time.

GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h A/D OverrunError ADEIR ADEIE ADEINT 00’00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh CAN Interface XP0IR XP0IE XP0INT 00’0100h 40h X-Peripheral Node XP1IR XP1IE XP1INT 00’0104h 41h X-Peripheral Node XP2IR XP2IE XP2INT 00’0108h 42h PLL Unlock XP3IR XP3IE XP3INT 00’010Ch 43h

Table 8.1 Interrupt Sources, Flags, Vector and Trap Numbers (cont’d)

Source of Interrupt or

PEC Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

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Table 8.2 Exceptions or Error Conditions During Runtime

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

•HardwareReset

•SoftwareReset

•WatchdogTimer Overflow

RESET RESET RESET

00’0000h 00’0000h 00’0000h

00h 00h 00h

III III III

Class A Hardware Traps:

•Non-MaskableInterrupt

•StackOverflow

•StackUnderflow

NMI STKOF STKUF

NMITRAP STOTRP STUTRP

00’0008h 00’0010h 00’0018h

02h 04h 06h

II II II

Class B Hardware Traps:

•UndefinedOpcode

•ProtectedInstruction Fault

•IllegalWord Operand Access

•IllegalInstruction Access

•IllegalExternal Bus Access

UNDOPC PRTFLT ILLOPA ILLINA ILLBUS

BTRAP BTRAP BTRAP BTRAP BTRAP

00’0028h 00’0028h 00’0028h 00’0028h 00’0028h

0Ah 0Ah 0Ah 0Ah 0Ah

I I I I

I Reserved [2Ch –3Ch] [0Bh –0Fh] Software Traps

•TRAPInstruction

Any [00’0000h – 00’01FCh] in steps of 4h

Any [00h –7Fh]

Current CPU Priority

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9 CAPTURE/COMPARE (CAPCOM) UNITS

The CAPCOM units support generation and control of timing sequences on up to 32 channels. It has a maximum resolution of 400 ns at 20MHz system clock. The CAPCOM units are typically usedto handlehigh speed I/O tasks such aspulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers, provide two independent time bases for the capture/compare register array.

The input clock for the timers is programmable to several pre-scaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timersT0 and T7 allow event scheduling for the capture/compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare regis-

ters, each ofwhich may be individually allocatedto either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each registerhas one port pinassociated with it which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured) into the capture/compare register inresponse to an external eventat the port pin whichis associated with this register. In addition, a specific interrupt request forthis capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When amatch occurs between thetimer value and the value in a capture/compare register, specific actions will be taken, based on the selected compare mode.

Table 9.1 Compare Mode Function

Compare Modes Function

Mode 0 Interrupt-onlycompare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-onlycompare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.

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Figure 9.1 CAPCOM Unit Block Diagram

*) 12 outputs on CAPCOM2

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10 GENERAL PURPOSE TIMER (GPT) UNIT

The GPT unit is a flexible multifunctional timer/ counter structure. It may be used for many different time-related tasks such as: event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication.

TheGPT unit incorporatesfive 16-bit timers which areorganized intwo separate modules, GPT1and GPT2. Each timer, ineachmodule may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of threebasic modes of operation: Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derivedfrom the CPU clock, divided by a programmable prescaler. Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the ‘gate’ level on an externalinput pin. Each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400ns (@ 20MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD) to facilitate, for example, position tracking.

Timers T3 and T4 have output toggle latches (TxOTL)which change their state on each timer overflow/underflow. The state of these latches may be output on port pins (TxOUT) for time-out monitoring by external hardware components, or may be usedinternally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 andT4 may be configured as reload or capture

registers for timerT3. When usedas capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered, either by an external signal, or by a selectable state transition of its toggle latch T3OTL. When bothT2 and T4 are configuredto alternately reload T3 onopposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without softwareintervention.

With its maximum resolution of 160 ns (@ 20MHz), the GPT2 moduleprovides precise event control and time measurement.It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clockwhich is derived from theCPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionallybe cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without softwareoverhead.

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Figure 10.1 Block Diagram of GPT1

2nn=3...10

T2EUD

T2IN

CPU Clock

T3IN

T4IN

T3EUD

T4EUD

Mode

Control

Mode

Control

Mode

Control

GPT1 TimerT2

GPT1 Timer T3

GPT1 Timer T4

T3OTL

Reload Capture

U/D

Reload

Capture

Interrupt Request

Interrupt

Request

T3OUT

U/D

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Figure 10.2 Block Diagram of GPT2

11 PWM MODULE

ThePulse Width Modulation Module can generate up to four PWM output signals using edge-aligned or centre-alignedPWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM

signals is from 4.8 Hz to 1 MHz (referredto a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The levelof the output signals is selectable and the PWM module can generate interrupt requests.

2nn=2...9

T5EUD

T5IN

CPU Clock

T4IN

T4EUD

Mode

Control

Mode

Control

GPT2 Timer T5

GPT1 Timer T6

U/D

Interrupt Request

U/D

GPT2 CAPREL

T60TL

Toggle FF

T6OUT

CAPIN

Reload

Interrupt Request

to CAPCOM Timers

Capture

Clear

Interrupt Request

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12 WATCHDOG TIMER

The Watchdog Timer is a fail-safe mechanism. It limits the maximum malfunction time of the controller

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this way the chip’s start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or softwarerelated failures, the softwarefails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT

pin low in order to allow externalhardware components to be reset.

The Watchdog Timeris a 16-bit timer, clockedwith the systemclock dividedeither by 2 or by 128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer isreloaded. Therefore, timeintervals between 25µs and 420ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).

13 A/D CONVERTER

A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip for analog signal measurement. It uses a successive approximation method. The sample time (for loading the capacitors) and conversion time is programmable and can be modified for the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT). When the result of a previous conversion has not been read from the result register at the time the next conversion iscomplete, either an interrupt requestis generated, or the next conversion is suspended, until the previous result has been read.

For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins.

The A/D converter of the ST10F167 supports four different conversionmodes. Inthe standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without soft-

ware intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channelsis repeatedlysampled andconverted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence.This is called Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without the overhead of interrupt routines for each data transfer.

After each reset and also during normal operation, the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to the changing operating conditions (e.g. temperature) and compensates processvariations.

These calibration cycles are part ofthe conversion cycle. They do not affect the normal operation of the A/D converter.

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14 SERIAL CHANNELS

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces. An Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

ASC0 supports full-duplex asynchronous communicationup to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20MHz system clock. The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20MHz system clock.

Two dedicated baud rate generators are used to set up standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception, 3 separate interrupt vectors are provided for each serial channel.

In asynchronousmode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distin-

guish address from data bytes has been included (8-bit data + wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock. The shift clock can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes.

A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers.A parity bit can automatically be generated on transmission or be checked on reception. ‘framing error detection’ recognizes data frames with missing stop bits. An overrun error is generated if the last character received was not read out of the receive buffer register, on the reception of a new character.

15 CAN-MODULE

The integrated CAN-Module performs the autonomous transmission and reception of CAN frames inaccordance with the CAN specificationV2.0 part B (active). The on-chip CAN-Module can receive andtransmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

The module provides full CAN functionality for up to15 message objects. Messageobject 15may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance fil-

tering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins to interface to a bus transceiver.

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ST10F167

16 PARALLEL PORTS

The ST10F167 provides up to 77 I/O lines which areorganized into eight input/output ports and one input port.All port linesare bit-addressable, and all input/output lines are individually (bit-wise) programmable asinputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output driversof three I/ Oports can be configured (pin by pin)for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like). The special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports.

All port lineshave programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing externalmemory, while Port 4 outputsthe additional segment address bits A23/ 19/17...A16 in systems wheresegmentation is enabled to access more than 64KBytes of memory.Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels tothe A/D converter or timer control signals.

All port lines that are not used for these alternate functions may be used as general purpose IO lines.

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ST10F167

17 INSTRUCTION SET SUMMARY

The table below lists the instruction set of the ST10F167. More detailed information such as address modes,instruction operation, parametersfor

conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the “ST10 Programming Manual”..

Table 17.1 Instruction Set

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/ 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cyclesto normalize direct

word GPR and store result in direct word GPR

SHL / SHR Shift left/rightdirect word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute toa code segment 4 J(N)B Jump relative if direct bit is (not) set 4

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18 BOOTSTRAP LOADER

To activate the Boot-strap loader, a hardware reset with RSTIN pin low and an external pull-up resistor connected to the ALE pin, is applied. This forces the chip into a special test mode. The program execution starts from 1K bytes ROM, mappedfrom 0 to 3FF hexwhich is not accessible in normal execution mode.

Thistest ROM contains a one-time programmable flash EPROM,loaded with a self-test program plus the Boot-strap loader program. When the Boot-

strap loader modeis activated, an instruction fetch is performed from the test ROM regardless of the configuration selected with the EBC0, EBC1 and BUSACT pins. The reset vector in the test ROM branches to the self-test program, while the NonMaskable Interrupt vector (NMI) branches to the Boot-strap loader routine.

The self-test routine execution time is approximately 10ms. It terminates with a software reset instruction (SRST), where the chip is restarted ac-

JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if conditionis met 4 CALLS Call absolute subroutine in anycode segment 4 PCALL Push direct word register onto system stack and call

absolute subroutine

TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update

RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct

word register from system stack

RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (assumes NMI-pin low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2

Table 17.1 Instruction Set (cont’d)

Mnemonic Description Bytes

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ST10F167

cording to theEBC0, EBC1 and BUSACT pin configurations. The state of the ALE pin is not taken into account for software reset. To trigger the Boot-strap loader program, it is necessary to activate the Non Maskable Interrupt by forcing a low level on the NMI pin before the end of the self-test routine

The identification byte sent by the ST10F167 is D5h. Note thatthe bootstraploader of all ST10devices which include identification registers will return D5h as the identification byte. The startup code loaded with bootstrap loader will dump identification registers for complete chip identification from the host.

19 SPECIAL FUNCTION REGISTER OVERVIEW

The following table lists all ST10F167 SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name.Depending on the selected addressing mode, anSFR canbe accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 19.1 Special Function Register List

Name

Physical Address

8-Bit

Address

Description

Reset Value

ADCIC b FF98h CCh A/D Converter End of Conversion Interrupt Cont Reg 0000h ADCON b FFA0h D0h A/D Converter Control Register 0000h ADDAT FEA0h 50h A/D Converter Result Register 0000h ADDAT2 F0A0h E 50h A/D Converter 2 Result Register 0000h ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Reg 0000h BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0XX0h BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h CC0 FE80h 40h CAPCOM Register 0 0000h CC0IC b FF78h BCh CAPCOM Register 0 Interrupt Control Register 0000h CC1 FE82h 41h CAPCOM Register 1 0000h CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register 0000h CC2 FE84h 42h CAPCOM Register 2 0000h CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register 0000h

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ST10F167

CC3 FE86h 43h CAPCOM Register 3 0000h CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register 0000h CC4 FE88h 44h CAPCOM Register 4 0000h CC4IC b FF80h C0h CAPCOM Register4 Interrupt Control Register 0000h CC5 FE8Ah 45h CAPCOM Register 5 0000h CC5IC b FF82h C1h CAPCOM Register5 Interrupt Control Register 0000h CC6 FE8Ch 46h CAPCOM Register6 0000h CC6IC b FF84h C2h CAPCOM Register6 Interrupt Control Register 0000h CC7 FE8Eh 47h CAPCOM Register 7 0000h CC7IC b FF86h C3h CAPCOM Register7 Interrupt Control Register 0000h CC8 FE90h 48h CAPCOM Register 8 0000h CC8IC b FF88h C4h CAPCOM Register8 Interrupt Control Register 0000h CC9 FE92h 49h CAPCOM Register 9 0000h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register 0000h CC10 FE94h 4Ah CAPCOM Register 10 0000h CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register 0000h CC11 FE96h 4Bh CAPCOM Register 11 0000h CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register 0000h CC12 FE98h 4Ch CAPCOM Register 12 0000h CC12IC b FF90h C8h CAPCOM Register 12 Interrupt Control Register 0000h CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC13IC b FF92h C9h CAPCOM Register 13 Interrupt Control Register 0000h CC14 FE9Ch 4Eh CAPCOM Register 14 0000h CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register 0000h CC15 FE9Eh 4Fh CAPCOM Register 15 0000h CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register 0000h CC16 FE60h 30h CAPCOM Register 16 0000h CC16IC b F160h E B0h CAPCOM Register 16 Interrupt Control Register 0000h CC17 FE62h 31h CAPCOM Register 17 0000h CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register 0000h CC18 FE64h 32h CAPCOM Register 18 0000h CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register 0000h CC19 FE66h 33h CAPCOM Register 19 0000h CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register 0000h CC20 FE68h 34h CAPCOM Register 20 0000h CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register 0000h

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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CC21 FE6Ah 35h CAPCOM Register 21 0000h CC21IC b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register 0000h CC22 FE6Ch 36h CAPCOM Register 22 0000h CC22IC b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register 0000h CC23 FE6Eh 37h CAPCOM Register 23 0000h CC23IC b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register 0000h CC24 FE70h 38h CAPCOM Register 24 0000h CC24IC b F170h E B8h CAPCOM Register 24 Interrupt Control Register 0000h CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register 0000h CC26 FE74h 3Ah CAPCOM Register 26 0000h CC26IC b F174h E BAh CAPCOM Register 26 Interrupt Control Register 0000h CC27 FE76h 3Bh CAPCOM Register 27 0000h CC27IC b F176h E BBh CAPCOM Register 27 Interrupt Control Register 0000h CC28 FE78h 3Ch CAPCOM Register 28 0000h CC28IC b F178h E BCh CAPCOM Register 28 Interrupt Control Register 0000h CC29 FE7Ah 3Dh CAPCOM Register 29 0000h CC29IC b F184h E C2h CAPCOM Register 29 Interrupt Control Register 0000h CC30 FE7Ch 3Eh CAPCOM Register 30 0000h CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register 0000h CC31 FE7Eh 3Fh CAPCOM Register 31 0000h CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register 0000h CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h CP FE10h 08h CPU Context Pointer Register FC00h CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h DP0L b F100h E 80h P0L Direction Control Register 00h DP0H b F102h E 81h P0H Direction Control Register 00h DP1L b F104h E 82h P1L Direction Control Register 00h

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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DP1H b F106h E 83h P1H Direction Control Register 00h DP2 b FFC2h E1h Port 2 Direction Control Register 0000h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Control Register 00h DP6 b FFCEh E7h Port 6 Direction Control Register 00h DP7 b FFD2h E9h Port 7 Direction Control Register 00h DP8 b FFD6h EBh Port 8 Direction Control Register 00h DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10 bits) 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10 bits) 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10 bits) 0002h DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10 bits) 0003h EXICON b F1C0h E E0h External Interrupt Control Register 0000h MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h ODP6 b F1CEhE E7h Port 6 Open Drain Control Register 00h ODP7 b F1D2h E E9h Port 7 Open Drain Control Register 00h ODP8 b F1D6h E EBh Port 8 Open Drain Control Register 00h ONES FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh P0L b FF00h 80h Port 0 Low Register (Lower half of PORT0) 00h P0H b FF02h 81h Port 0 High Register (Upper half of PORT0) 00h P1L b FF04h 82h Port 1 Low Register (Lower half of PORT1) 00h P1H b FF06h 83h Port 1 High Register (Upper half of PORT1) 00h P2 b FFC0h E0h Port 2 Register 0000h P3 b FFC4h E2h Port 3 Register 0000h P4 b FFC8h E4h Port 4 Register (8 bits) 00h P5 b FFA2h D1h Port 5 Register (read only) XXXXh P6 b FFCCh E6h Port 6 Register (8 bits) 00h P7 b FFD0h E8h Port 7 Register (8 bits) 00h P8 b FFD4h EAh Port 8 Register (8 bits) 00h PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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ST10F167

PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PICON F1C4h E E2h Port Input Threshold Control Register 0000h PP0 F038h E 1Ch PWM ModulePeriod Register 0 0000h PP1 F03Ah E 1Dh PWM ModulePeriod Register 1 0000h PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h PSW b FF10h 88h CPU Program Status Word 0000h PT0 F030h E 18h PWM Module Up/Down Counter0 0000h PT1 F032h E 19h PWM Module Up/Down Counter1 0000h PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h PW0 FE30h 18h PWM ModulePulse Width Register 0 0000h PW1 FE32h 19h PWM ModulePulse Width Register 1 0000h PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCON0b FF30h 98h PWM Module Control Register 0 0000h PWMCON1b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E BFh PWM ModuleInterrupt Control Register 0000h RP0H b F108h E 84h System Startup Configuration Register (Rd. only) XXh S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Reg 0000h S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register 0000h S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) XXh S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register 0000h S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control

0000h

S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 00h S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register 0000h SP FE12h 09h CPU System Stack Pointer Register FC00h SSCBR F0B4h E 5Ah SSC Baudrate Register 0000h SSCCON b FFB2h D9h SSC Control Register 0000h SSCEIC b FF76h BBh SSC Error Interrupt Control Register 0000h SSCRB F0B2h E 59h SSC Receive Buffer (read only) XXXXh

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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SSCRIC b FF74h BAh SSC Receive Interrupt Control Register 0000h SSCTB F0B0h E 58h SSC Transmit Buffer (write only) 0000h SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register 0000h STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h SYSCON b FF12h 89h CPU System Configuration Register 0xx0h

T0 FE50h 28h CAPCOM Timer 0 Register 0000h T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register 0000h T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register 0000h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register 0000h T3 FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register 0000h T4 FE44h 22h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5 FE46h 23h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h T7 F050h E 28h CAPCOM Timer 7 Register 0000h T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register 0000h T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h T8 F052h E 29h CAPCOM Timer 8 Register 0000h T8IC b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register 0000h T8REL F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h TFR b FFACh D6h Trap Flag Register 0000h

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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ST10F167

Notes 1:The system configuration is selected during reset.

2:Bit WDTR indicates a watchdog timer triggered reset. 3:The Interrupt ControlRegisters XPnIC, control interrupt requests from integrated X-Bus periph-

erals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.

WDT FEAEh 57h Watchdog Timer Register (read only) 0000h WDTCON FFAEh D7h Watchdog Timer Control Register 000Xh

XP0IC b F186h E C3h CAN Module Interrupt Control Register 0000h XP1IC b F18Eh E C7h X-Peripheral 1 Interrupt Control Register 0000h XP2IC b F196h E CBh X-Peripheral 2 Interrupt Control Register 0000h XP3IC b F19Eh E CFh PLL Interrupt Control Register 0000h ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h

Table 19.1 Special Function Register List (cont’d)

Name

Physical Address

8-Bit

Address

Description

Reset Value

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ST10F167

20 ELECTRICAL CHARACTERISTICS

20.1 Absolute Maximum Ratings

Ambient temperature under bias (TA): ST10F167.................................................................. –40to +85 °C

Storagetemperature (TST)................................................................................................... –65 to +150 °C

Voltage on VDDpins with respect to ground (VSS).................................................................. –0.5 to +6.5 V

Voltage on any pin with respect to ground (VSS)............................................................. –0.3to VDD+0.3 V

Input current on any pin during overload condition.............................................................. –10 to +10 mA

Absolute sum of all input currents during overload condition........................................................ |100 mA|

Power dissipation............................................................................................................................... 1.5 W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (

IN>VDD

or VIN<VSS)

the voltage on pins with respect to ground (

) must not exceed the values defined by the Absolute Maximum

Ratings.

20.2 Parameter Interpretation

The parameters listed in the Electrical Characteristicstables, 20.1 to 20.9, represent the characteristics of the ST10F167 and its demands on the system.

Where the ST10F167 logic provides signals with their respective timing characteristics, the symbol

“CC” for Controller Characteristics, is included in the “Symbol” column.

Where the external system must provide signals with their respective timing characteristics to the ST10F167, the symbol “SR” for System Requirement, is included in the “Symbol” column.

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ST10F167

20.3 DC Characteristics

VDD=5V±5%, VSS=0,f

CPU

= 20MHz, Reset active, TA= -40 to +85 °C

Table 20.1 DC Parametric

Parameter

Symbol Limit Values

Unit Test Condition

min.

max.

Input low voltage (TTL) VILSR – 0.5 0.2 V

– 0.1

V–

Input low voltage (Special Threshold)

ILS

SR – 0.5 2.0 V –

Input high voltage,all except RSTIN and XTAL1 (TTL)

VIHSR 0.2 V

+ 0.9

VDD+ 0.5 V –

Input highvoltage RSTIN V

IH1

SR 0.6 V

VDD+ 0.5 V –

Input highvoltage XTAL1 V

IH2

SR 0.7 V

VDD+ 0.5 V –

Input highvoltage (Special Threshold)

IHS

SR 0.8 V

- 0.2

VDD+ 0.5 V –

Input Hysteresis (Special Threshold)

HYS 400 - mV –

Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)

VOLCC – 0.45 V IOL= 2.4 mA

Output low voltage (all otheroutputs)

OL1

CC – 0.45 V I

OL1

= 1.6 mA

Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)

VOHCC

0.9

2.4

–VI

=–

500 µA

=–

2.4 mA

Output high voltage

(all otheroutputs)

OH1

0.9

2.4

–V

= – 250 µA

IOH= – 1.6 mA

Input leakagecurrent (Port 5) I

OZ1

CC – ±

µA 0.45V < VIN<V

Input leakagecurrent (all other) I

OZ2

CC – ±

µA 0.45V < VIN<V

Overload current IOVSR – ±

mA 5) 8)

RSTIN pullup resistor R

RST

CC 50 250 kΩ –

Read/Write inactive current

RWH

– -40 µAV

OUT

= 2.4 V

Read/Write active current

RWL

-500 – µAV

OUT=VOLmax

ALE inactive current

ALEL

–30µAV

OUT=VOLmax

ALE active current

ALEH

500 – µAV

OUT

= 2.4 V

Port 6 inactive current

P6H

– -40 µAV

OUT

= 2.4 V

Port 6 active current

P6L

-500 – µAV

OUT=VOL1max

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ST10F167

Notes 1:This specification is not valid for outputs which are switched to open drain mode. In this case

the respective output will float and the voltage results from the external circuitry. 2:The maximum current may be drawn while the respective signalline remains inactive. 3:The minimum current must be drawn in order to drive the respective signal line active. 4:This specificationis only valid during Reset, or duringHold- orAdapt-mode. Port6 pins areonly

affected, if they are used for CS output and the open drain function is not enabled. 5:Not 100% tested, guaranteed by design characterization. 6:The supplycurrent isa function ofthe operating frequency. This dependencyis illustrated in the

figure below.

These parameters are tested at V

DDmax

and 20 MHz CPU clock with all outputs disconnected

and all inputs at VILor VIH. 7:This parameter is tested including leakage currents. All inputs (including pins configured as in-

puts) at 0 V to 0.1 V or at VDD– 0.1 V to VDD, V

REF

= 0 V, all outputs (including pins configured

as outputs) disconnected. 8:Overloadconditions occurif the standard operating conditions areexceeded, i.e. thevoltage on

any pin exceeds the specified range (i.e. VOV> VDD+0.5V or VOV< VSS-0.5V). The absolute

sum of input overload currents on all port pins may not exceed 50 mA. 9:Power Down Current is to be defined.

PORT0 configuration current

P0H

–

-10

µAV

IHmin

P0L

-100

–

µAV

IN=VILmax

XTAL1 input current IILCC – ±

µA0V<VIN<V

Pin capacitance

(digital inputs/outputs)

CIOCC –

pF f = 1MHz

TA=25°C

Power supply current I

– 120 +

5*f

CPU

mA RSTIN = V

CPU

in [MHz]

Idle mode supply current I

–40+

2*f

CPU

mA RSTIN = V

IH1

CPU

in [MHz]

Power-down mode supply current I

– 100 µAVDD= 5.25 V

Read Current I

PPR

- 200 µAV

Write Current I

PPW

- 50 mA at 20MHz 32-Bit programming

VPP= 12V

during Write/Read V

11.4 12.6 V

Table 20.1 DC Parametric (cont’d)

Parameter

Symbol Limit Values

Unit Test Condition

min.

max.

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ST10F167

Figure 20.1 Supply/Idle Current as a Function of Operating Frequency

I [mA]

CPU

[MHz]

5 101520

150

100

CCtyp

IDmax

CCmax

IDtyp

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ST10F167

20.4 A/D Converter Characteristics

VDD=5V±5%, VSS=0V,TA= -40 to +85 °C

4.0 V ≤ V

AREF

≤ VDD+0.1 V, VSS-0.1 V ≤ V

AGND

≤ VSS+0.2 V

Sample time and conversion time of the ST10F167’s ADC are programmable. Table 20.3

shows the timing calculations.

Notes 1:V

AIN

may exceed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conver-

sion result in these cases will be X000Hor X3FFH, respectively.

2:During the sample time the input capacitance CIcan be charged/discharged by the external

source. Theinternal resistance of the analog source mustallow the capacitanceto reachits final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values forthe sampleclock tSCdependon programming andcan betaken fromthe tableabove.

3:This parameter includes the sample time tS, the time for determining the digital result and the

time to load the result register with the conversion result. Values for the conversion clock tCCdepend on programming and can be taken from the table above.

4:This parameter depends on the ADC control logic. It is not a real maximum value, but rather a

Table 20.2 A/D Converter Characteristics

Parameter Symbol

Limit Values

Unit Test Condition

min. max.

Analog input voltage range V

AIN

SR V

AGND

AREF

V1)

Sample time t

CC – 2 t

2) 4)

Conversion time t

CC – 14 tCC+t

+ 4TCL

3) 4)

Total unadjusted error TUE CC – + 3 LSB 5) Internal resistance of reference voltage source

AREF

SR – tCC/165

-0.25

kΩ t

in [ns] 6) 7)

Internal resistance of analog source

ASRC

SR – tS/ 330

-0.25

kΩ t

in [ns] 2) 7)

ADC input capacitance C

AIN

CC – 33 pF 7)

Table 20.3 Sample and Conversion Time Calculations

ADCON.15|14

(ADCTC)

Conversion clock t

ADCON.13|12

(ADSTC)

Sample clock t

00 TCL * 24 00 t

01 Reserved, do not use 01 tCC*2 10 TCL * 96 10 tCC*4 11 TCL * 48 11 tCC*8

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ST10F167

fixum.

5:TUE is testedat V

AREF

=5.0V,V

AGND

=0V, VDD=4.9V. It isguaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOVspecification) occurs on maximum 2 not selected analog input pins and the absolutesum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be ±4 LSB.

6:During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The

internal resistance of the reference voltage source must allow the capacitance to reach its respective voltagelevel within tCC. Themaximum internal resistanceresults fromthe programmed conversion timing.

7:Not 100% tested, guaranteed by design characterization.

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ST10F167

20.5 AC Characteristics

20.5.1 Test Waveforms

Figure 20.2 Input Output Waveforms

Figure 20.3 Float Waveforms

2.4V

0.45V

Test Points

0.2V

+0.9

0.2V

+0.9

0.2V

-0.1

0.2V

-0.1

AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

For timing purposes a port pin is no longer floating when a 100 mV change from load voltageoccurs,butbeginstofloatwhena100mVchangefromtheloadedVOH/VOLleveloccurs (IOH/IOL= 20 mA).

Timing

Reference

Points

Load

+0.1V

Load

-0.1V

+0.1V

Load

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ST10F167

20.5.2 Definition of Internal Timing

The internal operation of the ST10F167 is controlled by the internal CPU clock f

CPU

. Both edges of theCPU clock can trigger internal (e.g.pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 20.4).

The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the mechanism used to generate f

CPU

. This influence must be taken into consideration when calculating the timings for the ST10F167.

Figure 20.4 Generation Mechanisms for the CPU Clock

20.5.3 Direct Drive

When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the CPU clock is directlydriven from theoscillator with the input clock signal.

Thefrequency of f

CPU

directlyfollows the frequen-

cyof f

XTAL

sothe high and lowtime of f

CPU

(i.e.the duration of an individual TCL) is defined by the duty cycle of the input clock f

XTAL

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula:

For two consecutive TCLsthe deviation caused by the duty cycle of f

XTAL

is compensated so the du-

ration of 2TCL is always 1/f

XTAL

. The minimum

value TCL

min

therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:

2TCL = 1/f

XTAL.

Note:The address float timings in Multiplexed bus mode

and t45) use the maximum duration of TCL

(TCL

max

= 1/f

XTAL

*DC

max

) instead of TCL

min

TCLTCL

CPU

XTAL

CPU

XTAL

Phase Locked Loop Operation

Direct Clock Drive

TCL

min

1 f⁄

XTAL

*DC

min

DC duty cycle=

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ST10F167

20.5.4 Phase Locked Loop

When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. f

CPU=fXTAL

* 4). With every

fourth transition of f

XTAL

the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of f

CPU

is constantly adjusted so it is

locked to f

XTAL

. The slight variation causes a jitter

off

CPU

which alsoeffects theduration of individual

TCLs. Thetimings listedin the ACCharacteristics that re-

ferto TCLs thereforemust be calculated using the minimumTCL that is possibleunder the respective circumstances.

Theactual minimum value for TCL dependson the jitterof the PLL. As the PLL is constantly adjusting itsoutput frequency so thatit remains locked tothe applied input frequency (crystal or oscillator) the relative deviationfor periods of more than one TCL is lower than for one single TCL (see formula and figure below).

For a period ofN*TCL the minimum value is computed using the corresponding deviation DN:

where

= number of consecutive TCLs and

1 ≤N≤ 40. So for a period of 3 TCLs (i.e.N= 3):

This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) thedeviation caused by the PLL jitter is negligible.

Figure 20.5 Approximated Maximum PLL Jitter

TCL

min

TCL

NOM

* 1lD

l)100§–(=

4 N15)%[]⁄–(±=

D34315⁄–=

3.8%=

TCL

min

TCL

NOM

1 3.8 100⁄–()×=

TCL

NOM

0.962×=

24.1

nsec@f

CPU

20MHz=()

3216

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for 1 ≤N≤ 40 and 10MHz ≤ f

CPU

≤ 20MHz.

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ST10F167

20.5.5 External Clock Drive XTAL1

VDD=5V±5%, VSS=0V,TA= -40 to +85 °C

Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.

Figure 20.6 External Clock Drive XTAL1

20.5.6 Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the pro-

grammed memory cycle. The following table describes, how these variables are to be computed.

Table 20.4 External Clock Drive Characteristics

Parameter Symbol

Direct Drive 1:1 PLL 1:4

Unit

min. max. min. max.

Oscillator period t

OSC

SR 50

1000 200 333 ns High time t1SR 25 – 6 – ns Low time t2SR 25 – 6 – ns Rise time t3SR – 10 – 10 ns Fall time t4SR – 10 – 10 ns

OSC

IH2

Table 20.5 Memory Cycle Variable Definition

Description Symbol Values

ALE Extension t

TCL * <ALECTL>

Memory Cycle Time Waitstates t

2TCL * (15 - <MCTC>)

Memory Tristate Time t

2TCL * (1 - <MTTC>)

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ST10F167

20.5.7 Multiplexed Bus

VDD=5V±5%,VSS=0V,TA= -40 to +85 °C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF,CL(for Port 6, CS) = 100 pF

ALE cycle time = 6 TCL + 2tA+ tC+ tF(150 ns at 20-MHz CPU clock without waitstates)

Table 20.6 Multiplexed Bus Characteristics

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

ALE high time t5CC 15 + t

–TCL-10+t

–ns

Address setup to ALE t6CC 0 + t

–TCL-25+t

–ns

Address hold after ALE t7CC 15 + t

–TCL-10+t

–ns ALE falling edge to RD, WR (with RW-delay)

CC 15 + t

–TCL-10+t

–ns

ALE falling edge to RD, WR (no RW-delay)

CC -10 + t

– -10 + t

–ns

Address float after RD,WR (with RW-delay)

CC – 5 – 5 ns

Address float after RD,WR (no RW-delay)

CC – 30 – TCL + 5 ns

RD, WR low time (with RW-delay)

CC 25 + t

– 2TCL - 25

+ t

–ns

RD, WR low time

(no RW-delay)

CC 65 + t

– 3TCL - 10

+ t

–ns

RD to valid data in

(with RW-delay)

SR – 5+ t

– 2TCL - 45

+ t

RD to valid data in

(no RW-delay)

SR – 55 + t

– 3TCL - 20

+ t

ALE low to valid data in t16SR – 40 + tA+t

– 3TCL - 35

+ tA+ t

Address to valid data in t17SR – 60

+2tA+t

– 4TCL - 40

+2tA+t

Data hold after RD rising edge

SR 0 – 0 – ns

Data float after RD t19SR – 35 + t

– 2TCL - 15 + tFns

Data valid to WR t22SR 15 + t

– 2TCL - 35

+ t

–ns

Data hold after WR t23CC 35 + t

– 2TCL - 15

+ t

–ns

ALE rising edge after RD, WR

CC 35 + t

– 2TCL - 15

+ t

–ns

Address hold after RD, WR t27CC 35 + t

– 2TCL - 15 + t

–ns

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ST10F167

ALE falling edge to CS t38CC -5 - t

10 - t

-5 - t

10 - t

CS low to Valid Data In t39SR – 45

+ tC+2t

– 3TCL - 30

+ tC+2t

CS hold after RD, WR t40CC 60 + t

– 3TCL - 15 + t

–ns ALE fall. edge to RdCS,

WrCS (with RW delay)

CC 20 + t

– TCL - 5 + t

–ns

ALE fall. edge to RdCS, WrCS (no RW delay)

CC -5 + t

–-5+t

–ns

Address float after RdCS, WrCS (with RW delay)

CC – 0 – 0 ns

Address float after RdCS, WrCS (no RW delay)

CC – 25 – TCL ns

RdCS to Valid Data In (with RW delay)

SR – 15 + t

– 2TCL - 35

+ t

RdCS to Valid Data In (no RW delay)

SR – 50 + t

– 3TCL - 25

+ t

RdCS, WrCS Low Time (with RW delay)

CC 40 + t

– 2TCL - 10

+ t

–ns

RdCS, WrCS Low Time (no RW delay)

CC 65 + t

– 3TCL - 10

+ t

–ns

Data valid to WrCS t50CC 35 + t

– 2TCL - 15

+ t

–ns

Data hold after RdCS t51SR 0 – 0 – ns Data float after RdCS t52SR – 30 + t

– 2TCL - 20 + tFns

Address hold after RdCS, WrCS

CC 30 + t

– 2TCL - 20 + t

–ns

Data hold after WrCS t56CC 30 + t

– 2TCL - 20 + t

–ns

Table 20.6 Multiplexed Bus Characteristics (cont’d)

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

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ST10F167

Figure 20.7 External Memory Cycle:Multiplexed Bus, With Read/Write Delay, Normal

ALE

Data In

Data OutAddress

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

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ST10F167

Figure 20.8 External Memory Cycle:Multiplexed Bus, With Read/Write Delay,

Extended ALE

Data OutAddress

Data InAddress

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

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ST10F167

Figure 20.9 External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Normal

ALE

Data OutAddress

Address Data In

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

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ST10F167

Figure 20.10 External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Extended

ALE

Data OutAddress

Data InAddress

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read Cycle

RdCSx

BUS

Write Cycle

WR,

WRL, WRH

WrCSx

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ST10F167

20.5.8 Demultiplexed Bus

VDD=5V±5%,VSS=0V,TA= -40 to +85 °C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF,CL(for Port 6, CS) = 100 pF

ALE cycle time = 4 TCL + 2tA+ tC+ tF(100 ns at 20-MHz CPU clock without waitstates)

Table 20.7 Demultiplexed Bus Characteristics

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

ALE high time t5CC 15 + t

– TCL - 10 + t

–ns

Address setup to ALE t6CC 0 + t

– TCL - 25 + t

–ns

ALE falling edge to RD, WR (with RW-delay)

t8CC 15 + t

– TCL - 10

+ t

–ns

ALE falling edge to RD, WR (no RW-delay)

t9CC -10 + t

– -10 + t

–ns

RD, WR low time

(with RW-delay)

t12CC 25 + t

– 2TCL - 25

+ t

–ns

RD, WR low time

(no RW-delay)

CC 65 + t

– 3TCL - 10

+ t

–ns

RD to valid data in

(with RW-delay)

SR – 5 + t

– 2TCL - 45

+ t

RD to valid data in

(no RW-delay)

SR – 55 + t

– 3TCL - 20

+ t

ALE low to valid data in t16SR – 40

+ tA+ t

– 3TCL - 35

+ tA+ t

Address to valid data in t17SR – 60

+2tA+t

– 4TCL - 40

+2tA+t

Data hold after RD rising edge

SR 0 – 0 – ns

Data float after RD rising edge (with RW-delay)

SR – 35 + t

– 2TCL - 15

+ t

Data float after RD rising edge (no RW-delay)

SR – 15 + t

– TCL - 10

+ t

Data valid to WR t22CC 15 + t

– 2TCL - 35

+ t

–ns

Data hold after WR t24CC 15 + t

– TCL - 10 + t

–ns

ALE rising edge after RD, WR

CC -10 + t

– -10

+ t

–ns

Address hold after RD, WR t28CC -2.5 + t

– -2.5 + t

–ns

ALE falling edge to CS t38CC -5 - t

10 - t

-5 - t

10 - t

CS low to Valid Data In t39SR – 45

+ tC+2t

– 3TCL - 30

+ tC+2t

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ST10F167

CS hold after RD, WR t41CC 10 + t

– TCL - 15 + t

–ns

ALE falling edge to RdCS, WrCS (with RW-delay)

CC 20 + t

– TCL - 5 + t

–ns

ALE falling edge to RdCS, WrCS (no RW-delay)

CC -5 + t

–-5+t

–ns

RdCS to Valid Data In (with RW-delay)

SR – 15 + t

– 2TCL - 35

+ t

RdCS to Valid Data In (no RW-delay)

SR – 50 + t

– 3TCL - 25

+ t

RdCS, WrCS Low Time (with RW-delay)

CC 40 + t

– 2TCL - 10

+ t

–ns

RdCS, WrCS Low Time (no RW-delay)

CC 65 + t

– 3TCL - 10

+ t

–ns

Data valid to WrCS t50CC 35 + t

– 2TCL - 15+ t

–ns Data hold after RdCS t51SR 0 – 0 – ns Data float after RdCS

(with RW-delay)

SR – 30 + t

– 2TCL - 20

+ t

Data float after RdCS (no RW-delay)

SR – 5 + t

– TCL - 20

+ t

Address hold after RdCS, WrCS

CC -10 + t

– -10

+ t

–ns

Data hold after WrCS t57CC 10 + t

– TCL - 15 + t

–ns

Table 20.7 Demultiplexed Bus Characteristics (cont’d)

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

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ST10F167

Figure 20.11 External Memory Cycle:Demultiplexed Bus, With Read/Write Delay,

Normal ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

BUS

(D15-D8)

D7-D0

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

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ST10F167

Figure 20.12 External Memory Cycle:Demultiplexed Bus, With Read/Write Delay,

Extended ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

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ST10F167

Figure 20.13 External Memory Cycle:Demultiplexed Bus, No Read/Write Delay, Normal

ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

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ST10F167

Figure 20.14 External Memory Cycle:Demultiplexed Bus, No Read/Write Delay,

Extended ALE

Data Out

Data In

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

RdCSx

Write Cycle

WR,

WRL, WRH

WrCSx

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

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ST10F167

20.5.9 CLKOUT and READY

=5V±5%, VSS=0V,TA= -40 to +85 °C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF,CL(for Port 6, CS) = 100 pF

Notes 1:These timings are given for test purposes only, in order to assure recognition at aspecific clock

edge.

2:Demultiplexed bus is theworst case. Formultiplexed bus 2TCL areto beadded to themaximum

values. This adds even more time for deactivating READY. The2tAand 2tcrefer to the next bus cycle, tFrefers to the current bus cycle.

Table 20.8 CLKOUT and READY Characteristics

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

CLKOUT cycle time t29CC 50 50 2TCL 2TCL ns CLKOUT high time t30CC 20 – TCL – 5 – ns CLKOUT low time t31CC 15 – TCL – 10 – ns CLKOUT rise time t32CC – 5 – 5 ns CLKOUT fall time t33CC – 10 – 10 ns CLKOUT rising edge to

ALE falling edge

CC -5+ t

10 + t

-5 + t

10 + t

Synchronous READY setup time to CLKOUT

SR 30 – 30 – ns

Synchronous READY hold time after CLKOUT

SR 0 – 0 – ns

Asynchronous READY low time

SR 65 – 2TCL + 15 – ns

Asynchronous READY setup time

SR 15 – 15 – ns

Asynchronous READY hold time

SR 0 – 0 – ns

Async. READY hold time after RD, WRhigh (Demultiplexed Bus)

SR 0 0 + t

+2tA+t

0 TCL - 25

+ tc+2tA+t

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ST10F167

Figure 20.15 CLKOUT and READY

Notes 1:Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2:The leading edge of the respective command depends on RW-delay. 3:READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

4:READY may bedeactivated in response to the trailing (rising) edge of the corresponding com-

mand (RD or WR).

5:If the AsynchronousREADY signaldoes not fulfil theindicated setupand holdtimes withrespect

to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfil

in order to be safely syn-

chronized. This is guaranteed, if READY is removed in response to the command (seeNote4)).

6:Multiplexed bus modes have a MUX waitstate addedafter a bus cycle, and an additional MTTC

waitstate may be inserted here. For a multiplexed bus with MTTC waitstatethis delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero.

7:The next external bus cycle may start here.

CLKOUT

ALE

Sync

READY

Async

READY

waitstate

READY

MUX/Tristate

Running cycle

Command

RD, WR

see 6)

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ST10F167

20.5.10 External Bus Arbitration

=5V±5%, VSS=0V,TA= -40 to +85 °C

CL(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL(for Port 6, CS) = 100 pF

Table 20.9 External Bus Arbitration Characteristics

Parameter Symbol

Max. CPU Clock

=20MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

HOLD input setup time to CLKOUT

SR 35 – 35 – ns

CLKOUT to HLDA high or BREQ low delay

CC – 20 – 20 ns

CLKOUT to HLDA low or BREQ high delay

CC – 20 – 20 ns

CSx release t

CC – 20 – 20 ns

CSx drive t

CC -5 25 -5 25 ns

Other signals release t

CC – 20 – 20 ns

Other signals drive t

CC -5 25 -5 25 ns

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ST10F167

Figure 20.16 External Bus Arbitration, Releasing the Bus

Notes 1:The ST10F167 will complete the currently running bus cycle before granting bus access.

2:This is the first possibility for BREQ to get active. 3:The CS outputs will be resistive high (pullup) after

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

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ST10F167

Figure 20.17 External Bus Arbitration (Regaining the Bus)

Notes 1:This is the last chance for BREQ to trigger the indicated regain-sequence.

Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F167 requesting the bus.

2:The next ST10F167 driven bus cycle may start here.

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

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ST10F167

21 PACKAGE MECHANICAL DATA

Figure 21.1 Package Outline PQFP144 (28 x 28 mm)

22 ORDERING INFORMATION

Salestype Temperature range Package

ST10F167-Q6 -40°Cto85°C PQFP144 (28 x 28)

VR02061A

Dim

mm inches

min ty max min ty max A 4.07 0.106 A1 0.25 0.010 A2 3.17 3.42 3.67 0.125 0.315 0.144 B 0.22 0.38 0.009 0.015 C 0.13 0.23 0.005 0.009 D 30.95 31.20 31.45 1.129 1.228 1.238 D1 27.90 28.00 28.10 1.098 1.120 1.106 D3 22.75 0.896 e 0.65 0.02E 30.95 31.20 31.45 1.219 1.228 1.238 E1 27.90 28.00 28.10 1.098 1.102 1.106 E3 22.75 0.896 L 0.65 0.80 0.95 0.026 0.031 0.037 L1 1.60 0.063 K0°(min), 7°(max)

Number of Pins

144

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Notes

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics.

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Datasheet ST10F167-Q6 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual