Datasheet SSTL16857 Datasheet (Philips)

INTEGRATED CIRCUITS

SSTL16857

14-bit SSTL_2 registered driver with differential clock inputs

Product specification Supersedes data of 1999 Apr 29

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1999 Sep 30

Philips Semiconductors Product specification

14-bit SSTL_2 registered driver with differential clock inputs

FEA TURES

•Stub-series terminated logic for 2.5V VDDQ (SSTL_2)

•Optimized for DDR (Double Data Rate) SDRAM applications

•Supports SSTL_2 signal inputs and outputs

•Flow-through architecture optimizes PCB layout

•Meets SSTL_2 class I and class II specifications

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000 V per MIL STD 833 Method 3015

and 200 V per Machine Model

•Full DDR solution provided when used with PCK857 and CBT3857

DESCRIPTION

The SSTL16857 is a 14-bit SSTL_2 registered driver with differential clock inputs. Both V however. V V

REF

DDQ

normally at 0.5*V be used for standard stub-series applications or capacitive loads. Master reset (RESET

The SSTL16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of 200 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16857 is intended to be used for SSTL_2 input and output signals.

The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs.

The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.

and V

CC

must not exceed VCC. Inputs are SSTL_2 type with

DDQ

support 2.5V and 3.3V operation

DDQ

. The outputs support class I which can

) asynchronously resets all registers to zero.

PIN CONFIGURATION

1

Q1

2

Q2

3

GND

VDDQ

4 5

Q3

6

Q4 Q5

7 8

GND

9

VDDQ

Q6

10 11

Q7

12

VDDQ

13

GND

14

Q8 Q9

15 16

VDDQ

17

GND

Q10

18 19

Q11

20

Q12

21

VDDQ

GND

22

Q13

23 24

Q14

SSTL16857

48

D1

47

D2

46

GND

45

VCC

44

D3

43

D4

42

D5

41

D6

40

D7

39

CLK–

38

CLK+

37

VCC

36

GND

35

VREF

34

RESET

33

D8

32

D9

31

D10

30

D11

29

D12

28

VCC

27

GND

26

D13

25

D14

SW00311

QUICK REFERENCE DA TA

GND = 0 V; T

SYMBOL

t

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW) PD = CPD V

PD

= input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V;

f

i

ȍ (C

L

= 25°C; tr =tf v2.5 ns

amb

PHL/tPLH

C

I

2

V

fo) = sum of the outputs.

CC

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay; CLK to Qn CL = 30 pF; V

= 2.5 V 1.8 ns

DDQ

Input capacitance VCC = 2.5V 2.9 pF

2

x fi )ȍ (CL V

CC

2

fo) where:

CC

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

48-Pin Plastic TSSOP Type I 0°C to +70°C SSTL16857 DGG SOT362-1

1999 Sep 30 853-2155 22448

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITION

UNIT

I

mA

14-bit SSTL_2 registered driver with differential clock inputs

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

LVCMOS asynchronous master

34 RESET

48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29,

D1 – D14 SSTL_2 data inputs

26, 25

1, 2, 5, 6, 7, 10,

11, 14, 15, 18,

Q1 – Q14 SSTL_2 data outputs

19, 20, 23, 24

35 VREF SSTL_2 input reference level

3, 8, 13, 17, 22,

27, 36, 46

GND Ground (0 V)

28, 37, 45 V

4, 9, 12, 16, 21 V

38 39

DDQ

CLK+

CLK–

FUNCTION TABLE

INPUTS

RESET CLK CLK D

L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q

H = High voltage level L = High voltage level

↓ = High-to-Low transition ↑ = Low-to-High transition

X = Don’t care

reset (Active LOW)

Positive supply voltage

CC

Output supply voltage Differential clock inputs

OUTPUT

SSTL16857

LOGIC DIAGRAM

RESET

VREF

D1

D2

AD

D4

D5

D6

D7

D8

D9

Q

0

D10

D11

D12

D13

D14

REGISTER

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

CLK+

ABSOLUTE MAXIMUM RA TINGS

CLK–

1, 2

SW00312

LIMITS

MIN MAX

V

T

V

I V

I

OK OUT

OUT

STG

CC

IK

I

DC supply voltage –0.5 +4.6 V

DC input diode current VI < 0 –50 mA

DC input voltage

3

–0.5 V

+ 0.5 V

DDQ

DC output diode current VO < 0 –50 mA

DC output voltage

DC output current VO = 0 to V

Continuous current

3

4

Note 3 –0.5 V

DDQ

VCC, V

, or GND ±100

DDQ

+ 0.5 V

DDQ

±50

Storage temperature range –65 +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

, V

4. The continuous current at V

1999 Sep 30

CC

, or GND should not exceed ±100 mA.

DDQ

3

Philips Semiconductors Product specification

V

Data inputs, RESET

V

15V or 1.35V

A

I

CLK

V

15V or 1.35V

V

15V or 1.35V

A

I

CLK and CLK in o osite

mA

14-bit SSTL_2 registered driver with differential clock inputs

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V

CC

V

DDQ

V

REF

V

TT

V

I

V

IH

V

IL

V

IH

V

IL

I

OH

I

OL

Tamb Operating free-air temperature range 0 70 °C

NOTE:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage V

Output supply voltage 2.3 2.7 V

Reference voltage

(V

REF

= 0.5 x V

DDQ

)

T ermination voltage V

Input voltage 0 V AC HIGH-level input voltage All inputs V AC LOW-level input voltage All inputs V

DC HIGH-level input voltage All inputs V

DC LOW-level input voltage All inputs VSS – 0.5V V

HIGH-level output current –20 mA

LOW-level output current 20 mA

1

DDQ

1.15 1.25 1.35

– 40mV V

REF

+ 350mV V

REF

+ 180mV V

REF

SSTL16857

3.6 V

V

+ 40mV V

REF

CC

– 350mV V

REF

+ 0.5V V

DDQ

– 180mV V

REF

V

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = 0°C to +70°C UNIT

MIN TYP2MAX

V

CMR

V

CC

NOTES:

1. When CLK and CLK

2. All typical values are at V

I/O supply voltage VCC = 2.3V; II = –18mA –1.2

IK

VCC = 2.3V to 2.7V; IOH = –100µA VCC – 0.2 2.3

HIGH level output voltage

OH

VCC = 2.3V; IOH = –8mA 1.95 2.2 VCC = 2.3V; IOH = –16mA 1.95 2.1 VCC = 2.3V to 2.7V; IOL = –100µA 0.002 0.2

LOW level output voltage

OL

VCC = 2.3V; IOL = –8mA 0.14 0.35

VCC = 2.3V; IOL = –16mA 0.30 0.35 CLK, CLK Common mode range for reliable performance 0.97 1.53 V CLK, CLK Minimum peak-to-peak input to ensure logic state 360 mV

PP

V

= 2.7V ; VI = 1.7V or 0.8V 0.01 ±5

CC

V

p

I

,

REF

Quiescent supply current

1

state

pp

= 2.7V ; VI = 2.7V or 0V

CC

V

= 3.6V ; VI = 1.7V or 0.8V

CC

V

= 3.6V ; VI = 2.7V or 0V 0.01 ±5

CC

V

= 2.7V ; VI = 1.7V or 0.8V 0.05 ±5

CC

V

= 2.7V ; VI = 2.7V or 0V

CC

V

= 3.6V ; VI = 1.7V or 0.8V

CC

V

= 3.6V ; VI = 2.7V or 0V 0.05 ±5 mA

CC

V

= 2.7V

CC

V

= 3.6V

CC

V

= 2.7V ; VI = 1.7V or 0.8V 12 25

CC

V

= 2.7V ; VI = 2.7V or 0V 10 25

CC

V

= 3.6V ; VI = 1.7V or 0.8V 12 25

CC

V

= 3.6V ; VI = 2.7V or 0V 10 25

CC

REF

= 1.

0.01 ±5

0.05 ±5

are HIGH, typical ICC = 25mA.

= 3.3V and T

CC

= 25°C (unless otherwise specified).

amb

V

µ

µA

µ

1999 Sep 30

4

Philips Semiconductors Product specification

tsuSetup time

ns

(INPUT)

(OUTPUT)

14-bit SSTL_2 registered driver with differential clock inputs

TIMING REQUIREMENTS

Over recommended operating conditions; T

SYMBOL PARAMETER TEST CONDITIONS

f

clock

t

w

Clock frequency 200 200 MHz Pulse duration, CLK, CLK HIGH or LOW 1.0 1.0 ns

p

t

h

Hold time 0.5 0.5 ns

SWITCHING CHARACTERISTICS

Over recommended operating conditions; T Class I, V

REF

SYMBOL

f

max

t

PLH/tPHL

t

PHL

= VTT = V

x 0.5 and CL = 10pF (unless otherwise noted) (see Figure 1)

DDQ

FROM

Maximum clock frequency 200 200 MHz CLK and CLK Q 1.0 3.1 0.7 2.6 ns RESET Q 2.0 5.0 1.4 4.0 ns

= 0_C to +70_C (unless otherwise noted) (see Figure 1)

amb

Data before CLK↑, CLK↓ 0.8 0.9

RESET HIGH before CLK↑, CLK↓ 0.8 1.0

= 0_C to +70_C; V

amb

= 2.3 – 2.7V and V

DDQ

TO

SSTL16857

LIMITS

VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V

MIN MAX MIN MAX

does not exceed V

DDQ

LIMITS LIMITS

VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V

MIN MAX MIN MAX

CC.

UNIT

BACK SIDE

FRONT SIDE

184/200-pin DDR SDRAM DIMM

SDRAM

CBT CBT CBT CBT CBT CBT CBT CBT CBT

SDRAM

SSTL16857 PCK857SSTL16857

The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation

SDRAM

CBT3857 (9)

SDRAM

SW00393

1999 Sep 30

5

Philips Semiconductors Product specification

14-bit SSTL_2 registered driver with differential clock inputs

P ARAMETER MEASUREMENT INFORMATION AC WAVEFORMS

CLK

OUTPUT

Waveform 1. Propagation delay times inverting and

RESET

OUTPUT

V

REF

t

PLH

V

REF

t

PHL

V

REF

V

REF

SW00338

non-inverting outputs

V

IH

V

REF

V

IL

t

PHL

V

OH

V

REF

V

OL

SW00402

Waveform 2. Propagation delay RESET to output.

SSTL16857

V

IH

V

IL

V

OH

V

OL

INPUT

TIMING INPUT

DATA INPUT

Waveform 4. Setup and hold times

t

W

V

REF

V

REF

Waveform 3. Pulse duration

V

REF

t

su

V

REF

t

h

V

REF

V

SW00339

V

SW00340

IH

IL

IH

IL

IH

IL

TEST CIRCUIT

V

TT

TEST POINT

NOTES: C

includes probe and jig capacitance

L

All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr ≤ 1.25ns/V, t The outputs are measured one at a time with one transition per measurement.

= V

V

TT

REF

DDQ

x 0.5

Figure 1. Load circuitry

1999 Sep 30

25Ω = SSTL_2 Class II 50Ω = SSTL_2 Class I

25Ω

CL = 10pF or 30pF

1.25ns/V.

f

SW00337

50pF

500 Ω

SW00336

Figure 2.

50pF

SW00335

Figure 3.

6

Philips Semiconductors Product specification

14-bit SSTL_2 registered driver with differential clock inputs

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1

SSTL16857

1999 Sep 30

7

Philips Semiconductors Product specification

14-bit SSTL_2 registered driver with differential clock inputs

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

SSTL16857

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1999

Date of release: 09–99

Document order number: 9397–750–06455

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1999 Sep 30

8