Datasheet SST89V564-40-I-TQJ, SST89V564-40-I-TQI, SST89V564-40-I-PJ, SST89V564-40-I-PI, SST89V564-40-I-NJ Datasheet (Silicon Storage Technology)

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FEATURES:

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

SST89E/V564 SST89E/VE554 FlashFlex51 MCU

Preliminary Specifications

• 8-bit 8051 Family Compatible Microcontroller (MCU) with Embedded SuperFlash Memory

• SST89E564/SST 89E 554 is 5V Operatio n

– 0 to 40 MHz Operation at 5V

• SST89V564/SST 89V 554 is 3V Operatio n

– 0 to 25 MHz Operation at 3V

• Fully Software and Developmen t To olset Compatible as well as Pin -For -Pin Packa ge Compatible with Stan dar d 8xC5x Micr ocont r oller s

• 1 KByte Register/Data RAM

• Dual Block SuperFlash EEPROM

– SST89E564/SST89V564: 64 KByte primary

block + 8 KByte secondary block (128-Byte sector size)

– SST89E554/SST89V554: 32 KByte primary

block + 8 KByte secondary block

(128-Byte sector size) – Individual Block Security Lock – Concurrent Operation during In-Application

Programming (IAP) – Block Address Re-mapping

• Support External Address Range up to 64 KByte of Program and Data Memory

• Three High-Current Drive Pins (16 mA each)

• Three 16-bit Timers/Counters

• Full-Duplex Enhanced UART

– Framing error detection – Automatic address recognition

• Eight Interrupt Sources at 4 Priority Levels

• Watchdog Timer (WDT)

• Four 8-bit I/O Ports (32 I/O Pins)

• Second DPTR register

• Reduce EMI Mode (I nhibi t ALE t hro ugh AUXR SFR )

• SPI Serial Interface

• TTL- and CMOS-Compatible Logic Levels

• Brown-out Detection

• Extended Power-Saving Modes

– Idle Mode – Power Down Mode with External Interrupt Wake-up – Standby (Stop Clock) Mode

• PDIP-40, PLCC-44 and TQFP-44 Packages

• Temperature Ranges:

– Commercial (0°C to +70°C) – Industrial (-40°C to +85°C)

PRODUCT DESCRIPTION

SST89E564, SST89V564, SST89E554, and SST89V554 are members of the FlashF le x51 f amily of 8-bit microcontr ollers. The FlashFlex51 is a family of microcontroller products designed and m anufactured on the state-of-t he-art SuperFlash CMOS semiconductor process technology. The device uses th e same powerful instruction se t and is pin-forpin compatible with standard 8xC5x microcontroller devices.

The device comes with 72/40 KByte of on-chip flash EEPROM program memory using SST’s patented and proprietar y CMO S Super Flash E EPROM tech nolo gy with the SST’s field-enhancing, tunneling injector, split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occupies 64 /32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 8 KByte of i nt ernal program mem ory space. The 8-KByte second ary SuperFlash block ca n be mapped to the lowest location of the 64/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed via a standard 87C5x OTP EPR OM prog ramm er fitted with a specia l adapter and firmware for SST’s device. During the power-on reset, the

device can be configured as a slave to an external host for source code storage or as a master to an external host for In-Application Programming (IAP) o perati on. T he device is designed to be p rogrammed “In-System ” and “In-Applic ation” on the printed circuit board for maximum flexibility. The device is pre-programmed with an example of bootstrap loader in the memo ry, demonstrating the initial user program code loading or su bsequent user c ode updating v ia the “IAP” operatio n. An example of bootstrap loader is for the user’s reference and convenience only. SST does not guarantee the functionality or the usefulness of the sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pr e-pro gra mmed sa mple code .

In addition to 72/ 40 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64 KByte of external prog r a m memo ry. In additio n t o 10 24 x 8 bits of on-chip RAM, up to 64 KBy te of exter nal RAM ca n be addressed.

SST’s highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs. These advantages translate into significant cost and reliability benefits for our customers.

FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Page 2

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE OF CONTENTS

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2.1 Reset Configuration of Program Memory Block Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Dual Data Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5 Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 External Host Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.2 Arming Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.3 Detail Explanation of the External Host Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.4 External Host Mode Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.5 Flash Operation Status Detection Via External Host Handshake . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.6 Step-by-step instructions to perform

External Host Mode commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . 28

4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.1 In-Application Programming Mode Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.2 Memory Bank Selection for In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.3 IAP Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.4 In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.5 Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.6 Interrupt Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.0 TIMERS/COUNTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.1 Framing Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.2 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.0 SECURITY LOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.2 SoftLock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.5 Power-Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.5.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.5.2 Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.5.3 Standby Mode (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.6 Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.7 Recommended Capacitor Values for Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Absolute Maximum Stress Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

12.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Page 4

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

LIST OF FIGURES

FIGURE2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FIGURE3-1: Program Memory Organization for SST89E564 and SST89V564 . . . . . . . . . . . . . . . . . . . . . 10

FIGURE3-2: Program Memory Organization for SST89E554 and SST89V554 . . . . . . . . . . . . . . . . . . . . . 11

FIGURE4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FIGURE4-2: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

FIGURE4-3: Select-Block1 / Select-Block0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

FIGURE4-4: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FIGURE4-5: Block-Erase for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FIGURE4-6: Block-Erase for SST89E554/SST89V554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIGURE4-7: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIGURE4-8: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FIGURE4-9: Prog-SB1 / Prog-SB2 / Prog-SB3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FIGURE4-10: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE4-11: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE6-1: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

FIGURE6-2: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FIGURE6-3: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FIGURE7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FIGURE8-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

FIGURE9-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

FIGURE9-2: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FIGURE10-1: I FIGURE10-2: I FIGURE10-3: I FIGURE10-4: I

FIGURE10-5: AC Testing Input/Output, Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

FIGURE10-6: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

FIGURE10-7: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

FIGURE10-8: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

FIGURE10-9: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

FIGURE10-10: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Test Condition, Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Test Condition, Idle Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Test Condition, Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Test Condition, Standby (Stop Clock) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Page 5

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

LIST OF TABLES

TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E564/SST89V564 . . . . . . . . 11

TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E554/SST89V554 . . . . . . . . 12

TABLE 3-3: SFCF Values Under Different Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 3-4: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE 3-5: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 3-6: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 3-8: Timer/Counters SFRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

TABLE 4-1: External Host Mode Commands for SST89E564/SST89V564. . . . . . . . . . . . . . . . . . . . . . . . 24

TABLE 4-2: External Host Mode Commands for SST89E554/SST89V554. . . . . . . . . . . . . . . . . . . . . . . . 25

TABLE 4-3: Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

TABLE 4-4: IAP Address Resolution for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

TABLE 4-5: In-Application Programming Mode Commands for SST89E564/SST89V564 . . . . . . . . . . . . 35

TABLE 4-6: In-Application Programming Mode Commands for SST89E554/SST89V554 . . . . . . . . . . . . 35

TABLE 4-7: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

TABLE 8-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

TABLE 8-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

TABLE 9-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TABLE 9-2: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

TABLE 10-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TABLE 10-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TABLE 10-3: DC Electrical Characteristics: 40MHz devices; 4.5-5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

TABLE 10-4: DC Electrical Characteristics: 25MHz devices; 2.7-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

TABLE 10-5: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

TABLE 10-6: External Clock Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

TABLE 10-7: Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Page 6

1.0 FUNCTIONAL BLOCKS

FUNCTIONAL BLOCK DIAGRAM

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Watchdog Timer

SuperFlash

EEPROM

Primary

Block

32K/64K x8

Secondary

Block 8K x8

Timer 0 (16-bits)

Timer 1 (16-bits)

Interrupt

Control

8051

CPU Core

Security

Lock

RAM

1K x8

I/O Port 0

I/O Port 1

I/O Port 2

I/O Port 3

SPI

8 Interrupts

I/O

Timer 2 (16-bits)

1. 64K x8 for SST89E564 and SST89V564 32K x8 for SST89E554 and SST89V554

8-bit

Enhanced

UART

384 ILL B1.4

Page 7

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

2.0 PIN ASSIGNMENTS

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

DD P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)

(MOSI) P1.5 (MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

Reserved

(TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3

(T0) P3.4

(T1) P3.5

(T2) P1.0

(T2 Ex) P1.1

P1.2 P1.3

(SS#) P1.4 (MOSI) P1.5 (MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3

(T0) P3.4 (T1) P3.5

(WR#) P3.6

(RD#) P3.7

XTAL2 XTAL1

1 2 3 4 5 6 7

40-pin PDIP

T op View

9 10 11 12 13 14 15 16 17 18 19 20

P1.4 (SS#)

P1.3

P1.2

P1.1 (T2 Ex)

P1.0 (T2)

Reserved

VDDP0.0 (AD0)

P0.1 (AD1)

44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11

44-lead TQFP

T op Vie w

12 13 14 15 16 17 18 19 20 21 22

XTAL2

(RD#) P3.7

(WR#) P3.6

XTAL1

Reserved

(A8) P2.0

(A9) P2.1

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

33 32 31 30 29 28 27 26 25 24 23

(A12) P2.4

(A11) P2.3

P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# Reserved ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)

384 ILL F19.5

384 ILL F18.3

FIGURE 2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP FIGURE 2-2: PIN ASSIGNMENTS FOR 44-LEAD TQFP

P1.4 (SS#)

P1.3

P1.2

P1.1 (T2 Ex)

P1.0 (T2)

Reserved

VDDP0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12

44-lead PLCC

T op Vie w

13 14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

XTAL2

(RD#) P3.7

(WR#) P3.6

XTAL1

Reserved

(A8) P2.0

(A9) P2.1

(A10) P2.2

39 38 37 36 35 34 33 32 31 30 29

(A12) P2.4

(A11) P2.3

384 ILL F20.4

P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# Reserved ALE/PROG#

PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)

FIGURE 2-3: P

(MOSI) P1.5 (MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

Reserved

(TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3

(T0) P3.4 (T1) P3.5

IN ASSIGNMENTS FOR 44-LEAD PLCC

Page 8

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

2.1 Pin Descriptions

TABLE 2-1: PIN DESCRIPTIONS (1 OF 2)

pull-ups

Name and Functions

sink seve ral LS TTL inputs. Port 0 pins float that have “1”s written to them, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application, it uses strong internal pullups when transitioning to V

. Port 0 also receives the code bytes during the external host

mode programming, and outputs the code bytes during the external host mode verification. External pull-u ps are required during program verification.

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The P ort 1 output buffers can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled lo w will source cu rren t (I

, see Tables 10-3 and 10-4 ) beca use of t he inte rnal pull-

ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode p rogramming and verification.

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled low will source current (I

, see Tables

10-3 and 10-4) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from exte rnal Program memory and during acce sses to e xternal Data Mem ory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to V

. Port 2 also receives some control signals and a partial of high-

order address bits during the external host mode programming and verification. Port 3: Port 3 is an 8-bit bidirection al I / O po rt with internal pul l-u ps. The Port 3 output buff e rs

can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled lo w will source cu rren t (I

, see Tables 10-3 and 10-4 ) beca use of t he inte rnal pull-

ups. P ort 3 also receives some control signals and a partial of high-order addre ss bits during the external host mode programming and verification.

device is executing from Internal Program Memory, PSEN# is inactive (V

). When the

device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, ex ce pt whe n acce ss to Exte rnal Data Memory while one PSEN# activation is skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while the RST input is conti n ual ly hel d hi gh for more than ten machine cycles will ca us e the device to enter External Host mode for programming.

Symbol Type

P0[7:0] I/O Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can

P1[7:0] I/O with internal

P1[0] I/O T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 P1[1] I T2EX: Timer/Counter 2 capture/reload trigger and direction control P1[4] I/O SS#: Master Input or Slave Output for SPI P1[5] I/O MOSI: Master Output line, Slave Input line for SPI P1[6] I/O MISO: Master Input line, Slave Output line for SPI P1[7] I/O SCK: Master clock output, slave clock input line for SPI

P2[7:0] I/O with internal

P3[7:0] I/O with internal

P3[0] I RXD: Serial input line P3[1] O TXD: Serial output lin e P3[2] I INT0#: External Interrupt 0 Input P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe

PSEN# I/O Program Store Enable: PSEN# is the Read strobe to External Program Store. When the

Page 9

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2)

Symbol Type

RST I Reset: Whil e the oscill ator is running, a hi gh logic sta te on this pin for tw o machi ne cycles will

EA# I External Access Enable : EA# must be driven to V

ALE/PROG# I/O Address Latch Enable: ALE is the output signal for latching the low byte of the address dur-

XTAL1 XTAL2

Vss I Ground: Circuit ground. (0V reference)

1. I = Input; O = Output

2. It is not necessary to receive a 12V programming supply voltage during flash programming.

Name and Functions

reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held high, the device will enter the External Host mode, otherwise the device will enter the Normal operation mode.

in order to enable the device to fetch

code from the External Program Memory. EA# must be driven to V

for internal program exe-

cution. However, Security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage

of 12V

(see “Absolute Maximum Stress Ratings” on page 47).

ing acces s es to external memory. This pin is also the programming pulse input (PROG#) for the external host mode. ALE is activated twice each machine cycle, except when access to External Data Memory, one ALE activation is skipped in th e seco nd mac hine cy cle . Ho wever, if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20)

Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal clock generation circuits from an external clock source.

I Power Supp ly: Supply voltage during normal, Idle, Power Down, and Standby Mode opera-

tions.

T2-1.6 384

Page 10

3.0 MEMORY ORGANIZATION

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

The device has separate addr e ss s pa ce s for program an d data memory.

3.1 Program Memory

There are two internal flash memor y blocks in the device. The primary flash memory block (Block 0) has 64/32 KByte. The secondary flash memory block (Block 1) has 8 KByte. Since the total program address space is limited to 64/32 KByte, the SFCF[1:0] bit are used to control Program

FFFFH

EA# = 0

FFFFH

SFCF[1:0] = 00

Bank Selectio n. Please re fer to Figure 3-1 and F igure 3-2 for the program memory configurations. Program Bank Select is described in the next section.

The 64K/32K x8 primary SuperFlash block is organized as 512/256 sectors, each sector consists of 128 Bytes.

The 8K x8 secondary SuperFlash block is organized as 64 sectors, each sector consists also of 128 Bytes.

For both blocks, the 7 least significant program address bits select the byte within the sector. The remainder of the program addr ess bi ts selec t the sect or with in the bloc k.

EA# = 1

SFCF[1:0] = 01, 10, 11

FFFFH

56 KByte

Block 0

0000H

FIGURE 3-1: P

External

64 KByte

Block 0

2000H

1FFFH

8 KByte

Block 1

0000H

ROGRAM MEMORY ORGANIZATION FOR SST89E564 AND SST89V564

0000H

384 ILL F48.5

Page 11

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

FFFFH

0000H

EA# = 0

External

64 KByte

FFFFH

E000H

DFFFH

8000H

7FFFH

2000H

1FFFH

0000H

EA# = 1

SFCF[1:0] = 00

8 KByte

Block 1

External

24 KByte

Block 0

8 KByte

Block 1

FFFFH

E000H

DFFFH

8000H

7FFFH

0000H

EA# = 1

SFCF[1:0] = 01

8 KByte Block 1

External

24 KByte

32 KByte

Block 0

EA# = 1

SFCF[1:0] = 10, 11

FFFFH

External

32 KByte

8000H

7FFFH

32 KByte

Block 0

0000H

384 ILL F48b.3

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION FOR SST89E554 AND SST89V 554

3.2 Program Memory Block Switching

The prog r am mem ory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block 0 to be used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching.

TABLE 3-1: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST89E564/SST89V 564

SFCF[1:0] Program Memory Block Switching

01, 10, 11 Block 1 is not visible to the PC;

Block 1 is reachable only via In-Application Programming from 000H - 1FFFH.

00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.

When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0. Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through In-Application Programming.

T3-1.0 384

Page 12

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 3-2: SFCF V

SFCF[1:0] Program Memory Block Switching

10, 11 Block 1 is not visible to the PC;

Block 1 is reachable only via In-Application Programming from E000H - FFFFH.

01 Both Block 0 and Block 1 are visible to the PC.

Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH.

00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.

3.2.1 Reset Configuration of Program Memory Block Switching

Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0. The SC0 bit is programmed via an External Host Mode command or an IAP Mode command. Se e Table 4-2 and Table 4-6.

Once out of reset, the SFCF[0] bit can be changed dynamically by the progr am f or desir ed eff ects . Changing SFCF[0] will not change the SC0 bit.

Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different physical memory to be mapped to t he logical program address s pace. The user must avoid executing block switching instructions within the address range 0000H to 1FFFH.

ALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SS T8 9E554/S ST89V 554

3.3 D ata Memory

The device has 1024 x 8 bits of on-chip RAM and can address up to 64 KByte of external data memory .

The device has f our sect ions of internal dat a memory:

1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.

2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.

3. The Special Function Registers (SFRs, 80H to FFH) are directly addressable only.

4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register (AUXR)” on page 20)

T3-2.2 384

TABLE 3-3: SFCF VALUES UNDER DIFFERENT

ESET CONDITIONS

State of SFCF[1:0] after:

WDT

Power-on

SC1

SC0

11 00

10 01 x1 11 0 1 10 10 10 0 0 11 11 11

1. SC1 only applies to SST89E554 and SST89V554.

External

Reset

(default)

Reset

Brown-out

Reset

x0 10

Software

Reset

T3-3.2 384

3.4 Dual Data Pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1.

3.5 Special Function Registers (SFR)

Most of the unique features of the Flash Flex51 microcontroller family are contr o ll ed by bits in s pecial function r eg isters (SFRs) located in the SFR Memory Map shown in Table 3-4. Individual descriptions of each SFR are provided and Reset values indicated in T ables 3-5 to 3-9.

Page 13

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 3-4: FLASHFLEX51 SFR MEMORY MAP

8 BYTES

F8H IPA F0H B E8H IEA E0H ACC D8H DFH D0H PSW C8H T2CON C0H WDTC B8H IP B0H P3 A8H IE A0H P2 98H SCON 90H P1 88H TCON 80H P0

1. SFRs are bit addressable.

T2MOD RCAP2L RCAP2H TL2 TH2 CFH

SADEN BFH

SFCF SFCM SFAL SFAH SFDT SFST IPH B7H

SADDR SPSR AFH

AUXR1 A7H

SBUF 9FH

TMOD TL0 TL1 TH0 TH1 AUXR 8FH

SP DPL DPH WDTD SPDR PCON 87H

SPCR D7H

IPAH F7H

FFH

EFH E7H

C7H

97H

T3-4.3 384

Page 14

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 3-5: CPU RELATED SFRS

Bit Address, Symbol, or Alternative Port Function

Symbol Description

ACC

B PSW

Accumulator E0H ACC[7:0] 00H B Register F0H B[7:0] 00H

Program Status

Direct

Address

D0H CY AC F0 RS1 RS0 OV F1 P 00H

Word SP Stack Pointer 81H SP[7:0] 07H DPL Data Pointer

82H DPL[7:0] 00H

Low DPH Data Pointer

83H DPH[7:0] 00H

High

IE IEA

Interrupt Enable A8H EA - ET2 ES0 ET1 EX1 ET0 EX0 40H

Interrupt

E8H - - - - EBO - - - xxxx0xxxb

Enable A IP

Interrupt Priority

B8H - - PT2 PS PT1 PX1 PT0 PX0 xx000000b

Reg IPH Interrupt Priority

B7H - - PT2H PSH PT1H PX1H PT0H PX0H xx000000b

Reg High

IPA

Interrupt Priority

F8H - - - - PBO - - - xxxx0xxxb

Reg A IPAH Interrupt Priority

Reg A High

F7H - - - - PBO

- - - xxxx0xxxb

PCON Power Control 87H SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL 00010000b AUXR Auxiliary Reg 8EH - - - - - - EXTRAM AO xxxxxxx00b AUXR1 Auxiliary Reg 1 A2H - - - - GF2 0 - DPS xxxx00x0b

1. Bit Addressable SFRs

RESET

ValueMSB LSB

T3-5.10 384

TABLE 3-6: FLASH MEMORY PROGRAMMING SFRS

Bit Address, Symbol, or Alternative Port Function

Symbol Description

SFST SuperFlash

Direct

Address

B6H SECD1 SECD2 SECD3 - - FLASH_BUSY - - xxxxx0xxb

Status

SFCF SuperFlash

B1H - IAPEN - - - - SWR BSEL x0xxxxxxb

Configuration

SFCM SuperFlash

B2H FIE FCM 00H

Command

SFDT SuperFlash

B5H SuperFlash Data Register 00H

Data

SFAL SuperFlash

B3H SuperFlash Low Order Byte Address Register - A

toA0 (SFAL) 00H

Address Low

SFAH SuperFlash

B4H SuperFlash High Order Byte Address Register - A

toA8 (SF AH) 00H

Address High

RESET

ValueMSB LSB

T3-6.6 384

Page 15

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 3-7: WATCHDOG TIMER SFRS

Bit Address, Symbol, or Alternative Port Function

Symbol Description

WDTC

Watchdog Timer

Direct

Address

C0H - - - WDOUT WDRE WDTS WDT SWDT xxx00x00b

Control

WDTD Watchdog Timer

85H Watchdog Timer Data/Reload 00H

Data/Reload

1. Bit Addressable SFRs

TABLE 3-8: TIMER/COUNTERS SFRS

Direct

Symbol Description

TMOD Timer/Counter

Address

89H Timer 1 Timer 0 00H

Mode Control

TCON

Timer/Counter

88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

Control TH0 Timer 0 MSB 8CH TH0[7:0] 00H TL0 Timer 0 LSB 8AH TL0[7:0] 00H TH1 Timer 1 MSB 8DH TH1[7:0] 00H TL1 Timer 1 LSB 8BH TL1[7:0] 00H

T2CON

Timer / Counter 2

C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# 00H

Control T2MOD# Timer2

C9H---- --T2OEDCENxxxxxx00b

Mode Control TH2 Timer 2 MSB CDH TH2[7:0] 00H TL2 Timer 2 LSB CCH TL2[7:0] 00H RCAP2H Timer 2 Capture MSB CBH RCAP2H[7:0] 00H RCAP2L Timer 2 Capture LSB CAH RCAP2L[7:0] 00H

1. Bit Addressable SFRs

Bit Address, Symbol, or Alternative Port Function

GATE C/T# M1 M0 GATE C/T# M1 M0

RESET

ValueMSB LSB

RESET

ValueMSB LSB

T3-7.3 384

T3-8.3 384

Page 16

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 3-9: INTERFACE SFRS

Bit Address, Symbol, or Alternative Port Function

Symbol Description

Direct

Address

SBUF Serial Data Buffer 99H SBUF[7:0] Indete rminate

SCON

Serial Port Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H SADDR Slave Address A9H SADDR#[7:0] 00H SADEN Slave Address

B9H SADEN#[7:0] 00H

Mask SPCR SPI Control

D5H SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 04H

AAH SPIF WCOL 00H

P0 P1 P2 P3

Port 0 80H P0[7:0] FFH

Port 1 90H - - - - - - T2EX T2 FFH

Port 2 A0H P2[7:0] FFH

Port 3 B0H RD# WR# T1 T 0 INT1# INT0# TXD RXD FFH

1. Bit Addressable SFRs

RESET

ValueMSB LSB

T3-9.4 384

Page 17

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

SuperFlash Status Register (SFST) (Read Only Register)

Location76543 2 10Reset Value

0B6H SECD1 SECD2 SECD3 - -

FLASH_BUSY

Symbol Function

SECD1 Security bit 1. SECD2 Security bit 2. SECD3 Security bit 3.

Please refer to Table 4-6 for security lock options.

FLASH_BUSYFlash operation completion polling bit.

1: Device is busy with flash operation. 0: Device has fully completed the last command.

SuperFlash Configuration Register (SFCF)

Location76543210Reset Value

0B1H - IAPEN ----

Symbol Function

IAPEN Enable IAP operation

0: IAP commands are disabled 1: IAP commands are enabled

SWR Software Reset

See “9.2 Software Reset” on page 43

BSEL Program memory block switching bit

See Figures 3-1 and 3-2.

- - xxxxx0xxb

SWR BSEL

x0xxxxxxb

SuperFlash Command Register (SFCM)

Location76543210Reset Value

0B2H FIE FCM6 FCM5 FCM4 FCM3 FCM2 FCM1 FCM0 00000000b

Symbol Function

FIE Flash Interrupt Enable.

0: INT1# is not reassigned. 1: INT1# is re-assigned to signal IAP operation completion.

External INT1# interrupts are ignored.

FCM[6:0] Flas h ope ration com man d

000_1011b Sector-Erase 000_1101b Block-Erase 000_1100b Byte-Verify

000_1110b Byte-Program 000_1111b Prog-SB1 000_0011b Prog-SB2 000_0101b Prog-SB3 000_1001b Prog-SC0 All other combinations are not implemented, and reserved for future use.

1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.

Page 18

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

SuperFlash Data Register (SFDT)

Location76543210Reset Value

0B5H SuperFlash Data Register 00000000b

Symbol Function

SFDT Mailbox register for interfacing with flash memory block. (Data register).

SuperFlash Address Registers (SFAL)

Location76543210Reset Value

0B3H SuperFlash Low Order Byte Address Register 00000000b

Symbol Function

SFAL Mailbox register for interfacing with flash memory block. (Low order address register).

SuperFlash Address Registers (SFAH)

Location76543210Reset Value

0B4H SuperFlash High Order Byte Address Register 00000000b

Symbol Function

SFAH Mailbox register for interfacing with flash memory block. (High order address register).

Interrupt Enable (IE)

Location76543210Reset Value

A8H EA - ET2 ES ET1 EX1 ET0 EX0 00H

Symbol Function

EA Global Interrupt Enable.

0 = Disable

1 = Enable ET2 Timer 2 Interrupt Enable. ES Serial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 Extern al 1 Int errupt Enable. ET0 Timer 0 Interrupt Enable. EX0 Extern al 0 Int errupt Enable.

Interrupt Enable A (IEA)

Location76543210Reset Value

E8H----EBO---xxxx0xxxb

Symbol Function

EBO Brown-out Interrupt Enable.

1 = Enable the interrupt

0 = Disable the interrupt

Page 19

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Interrupt Priority (IP)

Location76543210Reset Value

B8H - - PT2 PS PT1 PX1 PT0 PX0 xx000000b

Symbol Function

PT2 Timer 2 interrupt priority bit. PS Serial Port interrupt priority bit. PT1 Timer 1 interrupt priority bit. PX1 External interrupt 1 priority bit. PT0 Timer 0 interrupt priority bit. PX0 External interrupt 0 priority bit.

Interrupt Priority High (I PH)

Location76543210Reset Value

B7H - - PT2H PSH PT1H PX1H PT0H PX0H xx000000b

Symbol Function

PT2H Timer 2 interrupt priority bit high. PSH Serial Port interrupt priority bit high. PT1H Timer 1 interrupt priority bit high. PX1H External interrupt 1 priority bit high. PT0H Timer 0 interrupt priority bit high. PX0H External interrupt 0 priority bit high.

Interrupt Priority A (IPA)

Location76543210Reset Value

F8H----PBO---xxxx0xxxb

Symbol Function

PBO Brown-out interrupt priority bit.

Interrupt Priority A High (IPAH)

Location76543210Reset Value

F7H----PBOH---xxxx0xxxb

Symbol Function

PBOH Brown-out Interrupt priority bit high.

Page 20

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Auxiliary Register (AUXR)

Location76543210Reset Value

8EH------EXTRAMAOxxxxxx00b

Symbol Function

EXTRAM 0: Internal Expanded RAM access. For details, refer to “Data Memory” on page 12.

1: External data memory access. AO 0: Normal ALE

1: ALE is normally o ff . ALE is activ e on ly during a M O VX or MO VC instructi on. Thi s will r educe

EMI.

Auxiliary Register 1 (AUXR1)

Location76543210Reset Value

A2H----GF20-DPSxxxx00x0b

Symbol Function

GF2 General purpose user-defined flag. DPS DPTR registers select bit.

0: DPTR0 is selected.

1: DPTR1 is selected.

Watchdog Timer Control Register (WDTC)

Location76543210Reset Value

0C0H---WDOUT

WDRE WDTS WDT SWDT xxx00x00b

Symbol Function

WDOUT Watchdog output enable.

0: Watchdog reset will not be exported on Reset pin.

1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks. WDRE Watchdog timer reset enable.

0: Disable watchdog timer reset.

1: Enable watchdog timer reset. WDTS Watchdog timer reset flag.

0: External hardware reset clears the flag.

Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow.

1: Hardware sets the flag on watchdog overflow. WDT Watchdog timer refres h.

0: Hardware resets the bit when refresh is done.

1: Software sets the bit to force a watchdog timer refresh. SWDT Start watchdog timer.

0: Stop WDT.

1: Start WDT.

Page 21

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Watchdog Timer Data/Reload Register (WDTD)

Location76543210Reset Value

085H Watchdog Timer Data/Reload 00000000b

Symbol Function

WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.

SPI Control Register (SPCR)

Location76543210Reset Value

D5H SPIE

Symbol Function

SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. SPE SPI enable bit.

DORD Data Transmission Order.

MSTR Master/Slave select.

CPOL Clock Polarity

CPHA Clock Phase control bit.

SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured

SPE DORD MSTR

CPOL CPHA SPR1 SPR0 00000100b

0: Disables SPI.

1: Enables SPI and conn ects SS#, MOSI, MISO , and SCK t o pins P1[4 ], P1[5] , P1[6], P1[7 ].

0: MSB first in data transmission.

1: LSB first in data transmission.

0: Selects Slave mode.

1: Selects Master mode.

0: SCK is low w hen idle (Active High).

1: SCK is high when idle (Active Low).

0: Shift triggered on the leading edge of the clock.

1: Shift triggered on the trailing edge of the clock.

as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK

and the oscillator frequency, f

, is as follows:

OSC

SPR1 SPR0 SCK = f

0 0 1 1

0 1 0 1

divided by

OSC

4 16 64

128

Page 22

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

SPI Statu s Register ( SPSR)

Location76543210Reset Value

AAH SPIF

Symbol Function

SPIF Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is

WCOL Set if the SPI data register is written to during data transfer. To clear, read SPSR and

SPI Data Register (SPDR)

Location76543210Reset Value

86H SPD7

Power Control Register (PCON)

Location76543210Reset Value

87H SMOD1

WCOL - -

----00xxxxxxb

then generated. To clear, read SPSR and then access SPDR.

then access SPD R.

SPD6 SPD5 SPD4

SMOD0 BOF POF

SPD3 SPD2 SPD1 SPD0 00H

GF1 GF0 PD IDL 00010000b

Symbol Function

SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate. SMOD0 FE/SM0 Selection bit.

0: SCON[7] = SM0 1: SCON[7] = FE,

BOF Brown-out detection status bit, this bit will not be affected by any other reset. BOF should

be cleared by software. Power-on reset will also clear the BOF bit. 0: No Brown-out. 1: Brown-out occurred

POF Power-on reset status bit, this bit will not be affected by any other reset. POF should be

cleared by software. 0: No Power-on reset.

1: Power-on reset occurred GF1 General-purpose flag bit. GF0 General-purpose flag bit. PD Power-down bit.

0: Power-down mode is not activated.

1: Activates Power-down mode. IDL Idle mode bit.

0: Idle mode is not activated.

1: Activates Idle mode.

Page 23

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Serial Port Control Register (SCON)

Location76543210Reset Value

98H SM0/FE

Symbol Function

FE Set SMOD0 = 1 to access FE bit.

SM0 SMOD0 = 0 to access SM0 bit.

SM1 Serial Port Mode Bit 1

SM1 SM2 REN

TB8 RB8 TI RI 00000000b

0: No framing error

1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to

be cleared by software.

Serial Port Mode Bit 0

SM0 SM1 Mode Description Baud Rate

000Shift Registerf

0 1 1 8-bit UART Variable 1029-bit UARTf

1 1 3 9-bit UART Variable

1. f

= oscillator frequency

OSC

12 (12 clock mode)

OSC

mode) or f f

OSC

/6 (6 clock mode) or f

/32 or f /32 (12 clock mode)

/16 (6 clock

OSC

/64 or

OSC

SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI

will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the

received byte is a Given or broadcast Address. In Mode 1, if SM2 = 1 then RI will not be

activated unless a valid stop bit was received, and the received byte is a Given or

Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception.

0: to disable reception.

1: to enable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as

desired. RB8 In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 - 0, RB8 is the

stop bit that was received. In Mode 0, RB8 is not used. TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the

beginning of the stop bit in the other modes, in any serial transmission, Must be cleared

by software. RI Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway

through the stop bit time in the other modes, in any serial reception (except see SM2).

Must be cleared by software.

Page 24

SST89E564 / SST89V564 / SST89E554 / SST89V554

4.0 FLASH MEMORY PROGRAMMING

FlashFlex51 MCU

Preliminary Specifications

The device internal fl ash memor y can be programmed or erased us ing the f o llowin g two m ethod s:

• External Host Mode

• In-Application Programming (IAP) Mode

logic high to a logic low while RST input is being held continuously high. The device will stay in External Host Mode as long as RST = 1 and PSEN# = 0.

A Read-ID operation is necessary to “arm” the device in External Host Mode, and no other External Host Mode com-

4.1 External Host Programming Mode

External Ho st Programming Mod e allows the user to pr ogram the flash memory directly without using the CPU. External Ho st Mode is entered by forcing PSEN# from a

mands can be enabled until a Read-ID is performed. In External Host Mode, the internal flash memory blocks are accessed through the re-assigned I/O port pins (see Figure 4-1 for details) b y an ex ternal host, such as a MCU programmer, a PCB tester or a PC-controlled dev elopment board.

TABLE 4-1: EXTERNAL HOST MODE COMMANDS FOR SST89 E564/SST 89V 564

PROG#/

Operation RST PSEN#

Read-ID V Chip-Erase V Block-Erase V Sector-Erase V Byte-Program V Byte-Ver ify (Read) V Select-Block0 V Select-Block1 V Prog-SC0 V Prog-SB1 V Prog-SB2 V Prog-SB3 V

Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of

the above input pins are invalid and may result in unexpected behaviors.

Note: V

= Input Low Voltage; VIH = Input High V oltage; V

AH = Address high order byte; DI = Data Input; DO = Data Output

IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1

ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0]

⇓ V ⇓ V ⇓ V ⇓ V

⇓ V ⇓ V ⇓ V ⇓ V ⇓ V ⇓ V

IH1

= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;

IL IL IL IH IH IL

Il IL IH IH IL

DO AH AL

DI AH AL

DO AH AL

P3[5:4] P2[5:0] P1[7:0]

XX X XX X XAHAL

X55H X XA5H X X5AH X XX X XX X XX X

T4-1.4 384

Page 25

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 4-2: EXTERNAL HOST MODE COMMANDS FOR SST89 E554/SST 89V 554

PROG#/

Operation RST PSEN#

Read-ID V Chip-Erase V Block-Erase V Sector-Erase V Byte-Program V Byte-Ver ify (Read) V Prog-SC0 V Prog-SC1 V Prog-SB1 V Prog-SB2 V Prog-SB3 V

Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of

the above input pins are invalid and may result in unexpected behaviors.

Note: V

= Input Low Voltage; VIH = Input High V oltage; V

AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1

IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1

ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0]

⇓ V ⇓ V ⇓ V ⇓ V

⇓ V ⇓ V ⇓ V ⇓ V ⇓ V

IH1

= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;

IL IL IL IH IH IL IL IL IH IH IL

DO AH AL

DI AH AL

DO AH AL

P3[5:4] P2[5:0] P1[7:0]

XX X X A[15:13] X XAHAL

X5AH X X AAH X XX X XX X XX X

T4-2.0 384

XTAL2

Ready/Busy#

Address Bus

A15-A14

Flash

Control Signals

XTAL1

A14 A15

Port 0

0 1

2 3

4 5

6 7

Port 2

Port 3

Port 1

EA# ALE /

PROG#

RST

PSEN#

0 6

7 0

1 2 3

4 5

6 7 0

6 7

Input/ Output Data Bus

Address Bus A13-A8

Flash Control Signals

Address Bus A7-A0

384 ILL F01.1

FIGURE 4-1: I/O PIN ASS IG NM ENT S FOR EXTERNAL HOST MODE

Page 26

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

4.1.1 Product Identification

The Read-ID command accesses the Signature Bytes that identify the device and the m anufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. The Read-ID command is selected by the command c ode of 0H on P3[7:6 ] and P2[7:6]. See Figure 4-2 for timing waveforms.

TABLE 4-3: S

Manufacturer’s ID 30H BFH Device ID

SST89E564 31H 93H SST89V564 31H 92H SST89E554 31H 9BH SST89V554 31H 9AH

IGNATURE BYTES

Address Data

T4-3.4 384

4.1.2 Arming Command

An arming command sequence must take place before any External Host Mode sequence command is recognized by the device. This prevents accidental trigg ering of External Hos t Mode Comman ds due to nois e or pro grammer error. The arming command is as follows:

1. PSEN# goes low while RST is high. This will get the machine in External Host Mode, re-configuring the pins, and turning on the on-chip oscillator.

2. A Read-ID command is issued, and after 1 ms the External Host Mode commands can be issued.

After the above sequence, all other Exte rnal Host Mode commands are enabled. Before the Read-ID command is received, all other External Host Mode commands received are igno red.

4.1.3 Detail Explanation of the External Host Mode Commands

The External Host Mode commands are Read-I D, ChipErase, Block-Erase, Sector-Erase, Byte-Program, ByteVerify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, ProgSC1, Select-Block0, Select-Block1. See T ables 4-1 and 4-2 for all signal logic assignments, Figure 4-1 for I/O pin assignments, and Table 4-7 for the timing parameters. The critical timing for all Erase and Program commands is generated by an on-chip flas h me mo ry contro ller. The high-t olow transition of the PROG # signal initiates the Erase or Program commands, which are synchronized internally. The Read comman ds are asynchronous read s, independent of the PROG# signal level.

Following is a detailed description of the External Host Mode commands:

The Select-Block0 com mand enables Block 0 to be programmed in Exter nal Host Mode. Once this co mmand is ex e cu te d , al l subsequent External Host Commands wil l be directed at Block 0. S ee Figure 4-3 for timing waveforms. This command app lies to SS T8 9E56 4/SST 89V 564 on ly.

The Select-Block1 command enables Block 1 (8 KByte Block) to be programmed. Once this command is executed, all subsequ ent External Host Command s that are directed to the address range below 2000H will be directed at Block 1. The Sele ct-Block1 command only a ffects the lowest 8 KByte of the program address space. For addresses greater than or equal to 2000H, Block 0 is accessed by default. Upon entering External Host Mode, Block 1 is selected by default. Se e Figure 4-3 for timing waveforms. This command applies to SST89E564/ SST89V564 only.

The Chip-Erase, Block-Erase, and Sector-Erase commands are used for erasing all or part of the memory array. Erased data bytes in the memory array will be erased to FFH. Memory locations that are to be programmed must be in the erase d state pr ior to program ming.

The Chip-Erase command erases all bytes in both memory blocks, regardless of any previous Select-Block0 or SelectBlock1 commands. Chip-Erase ignores the Security Lock status and will erase the Security Lock, returning the device to its Unlocked state. The Chip-Erase command will also erase the SC0 bit. Upon c ompletion of Chip-Erase command, Block 1 will be the selected block. See Figure 4-4 for timing waveforms.

The Block-Erase command erases all bytes in the selected memory blocks. This command will not be executed if the security lock is enabled. The selection of the memory block to be erased is d etermined by t he prior execution Selec tBlock0 or Select-Bl ock1 command. Se e Figur e 4-6 for the timing waveforms.

The Sector-Erase c ommand erases all of the bytes in a sector. The sector size for the fla sh memory is 128 B ytes. This command wi ll not be executed if the Sec urity lock is enabled. See Figure 4-7 for timing waveforms.

The Byte-Program command is used for programming new data into the memory array. Programming will not take place if any security locks are enabled. Se e Figure 4-8 for timing waveforms.

Page 27

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications The Byte-Verify command allows the user to verify that the

device correctly performed an Erase or Program command. This comm an d wi ll b e d is a bled if any sec u r it y l ocks are enabled. See Figure 4-11 for timing waveforms.

The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock secti on an d al s o i n Table 8-1. Once programmed, these bits can only be erased through a ChipErase command. See Figure 4-9 for timing waveforms.

Prog-SC0 comma nd pr ograms SC0 b it, whi ch de ter min es the state of SFCF[0] out of reset. Once programmed, SC0 can only be re stored to a n erased state v ia a Chip- Erase command. See Figure 4-10 for timing waveforms.

Prog-SC1 comma nd pr ograms SC1 b it, whi ch de ter min es the state of SFCF[1] out of reset. Once programmed, SC1 can only be re stored to a n erased state v ia a Chip- Erase command. See Figure 4-10 for timing waveforms. ProgSC1 is for SST89E554/SST89V554 only .

4.1.4 Externa l Host Mode Clock Source

In External Host Mode, an internal oscillator will provide clocking for the device. The on-chip oscillator will be turned on as the device enters External Host Mode; i.e. when PSEN# goes low while RST is high. Dur ing Exter nal Host Mode, the CPU core is held in reset. Upon exit from External Host Mode, the internal oscillator is turned off.

4.1.5 Flash Operation Status Detection Via External Host Handshake

The device provides two meth ods for an external host to detect the completi on of a flash me mory operatio n to opt imize the Program or Erase time. The e nd of a fla sh me mory operation cycle can be detected by:

1. monitoring the Ready/Busy# bit at P3[3];

2. monitoring the Data# Polling bit at P0[3].

4.1.5.2 Data# Polling (P0[3])

During a Program op eration, any attempts to read (Byt eVerify), wh ile the device is busy, will receive the comple ment of the data of the last byte loaded (logic low, i.e. “ 0” for an erase) on P0[3] with the rest of the bits “0”. During a Program operation, the Byte-Verify command is reading the data of the last byte loade d, not the data at the addres s specified.

4.1.6 Step-by-step instructions to perform External Host Mode commands

To program data into the memory array, apply power supply voltage (V

) to VDD and RST pins, and per-

form the following steps:

1. Maintain RST high and set PSEN# from logic high to low, in sequence according to the appropriate timing diagram.

2. Raise EA# Hig h (V

3. Issue Read-ID command to enable the External Host Mode.

4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command.

5. Select the memory location using the address lines (P3[5:4], P2[5:0], P1[7:0]).

6. Present the data in on P0[7:0].

7. Pulse ALE/PROG#, observing minimum pulse width.

8. Wait for low to high transition on READY/BUSY# (P3[3]).

9. Repeat steps 5 - 8 until programming is finished.

10. Verify the flash memory contents.

4.1.5.1 Ready/Busy# (P3[3])

The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming o peration is complet ed to indicate th e Ready status .

Page 28

SST89E564 / SST89V564 / SST89E554 / SST89V554

4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode

RST

PSEN#

ALE/PROG#

EA#

FlashFlex51 MCU

Preliminary Specifications

P2[7:6] ,P3[7:6]

P3[5:4] ,P2[5:0] ,P1

FIGURE 4-2: R

Device ID = 93H for SST89E564

92H for SST89V564 9BH for SST89E554 9AH for SST89V554

EAD-ID

0000b

0030H

BFH

Reads chip signature and identification registers at the addressed location.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

0000b

0031H

Device ID

384 ILL F02.3

P3[3]

PSB

P3[5:4], P2[5:0] A5H/55H

P3[7:6], P2[7:6]

FIGURE 4-3: S

ELECT-BLOCK1 / SELECT-BLOCK0

1001b

384 ILL F56.1

Enables the selection o f either of the flash memor y blocks prior to issuing a Byte-Verify, B lock-Erase, SectorErase, or Byte-Program. These commands apply to SST89E564/SST89V564 only .

Page 29

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

RST

PSEN#

ADS

ALE/PROG#

PROG

EA#

P3[3]

P3[7:6], P2[7:6]

0001b

FIGURE 4-4: CHIP-ERASE

Erases both flash memory blocks. Security lock is ignored and the security bits are erased too.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

384 ILL F03.1

P3[7:6], P2[7:6] 1101b

384 ILL F04.2

FIGURE 4-5: B

LOCK-ERASE FOR SST89E56 4/SST89V 564

Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.

Page 30

RST

PSEN#

ALE/PROG#

EA#

P3[3]

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

ADS

PROG

P3[7:6], P2[7:6]

P3[5:4], P2[5:0]

1101b

FIGURE 4-6: BLOCK-ERASE FOR SS T 89E55 4/SST89V 554

Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

384 ILL F21.1

P3[7:6], P2[7:6]

P3[5:4], P2[5:0]

FIGURE 4-7: S

ECTOR-ERASE

1011b

384 ILL F05.1

Erases the addressed sector if the security lock is not activated on that flash memory block.

Page 31

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

P3[5:4], P2[5:0]

P3[7:6], P2[7:6]

1110b

384 ILL F06.2

FIGURE 4-8: BYTE-PROGRAM

Programs the addressed cod e byte if the byte location has be en successfully erased and not yet programmed . Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

P3[7:6], P2[7:6]

FIGURE 4-9: P

ROG-SB1 / PROG-SB2 / PROG-SB3

1111b / 0011b / 0101b

384 ILL F49.2

Programs the Security bits SB1, SB2 and SB3 respectively . Only a Chip-Erase will erase a programmed security bit.

Page 32

SST89E564 / SST89V564 / SST89E554 / SST89V554

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

P3[5:4], P2[5:0] 5AH / AAH

FlashFlex51 MCU

Preliminary Specifications

P3[7:6], P2[7:6]

1001b

384 ILL F52.5

FIGURE 4-10: PROG-SC0 / PROG-SC1

Programs the star t-up configuration bit SC0/SC1. O nly a Chip-Erase will erase a programmed SC0/SC1 bit. Prog-SC1 applies to SST89E554/SST89V554 only.

RST

PSEN#

ALE/PROG#

EA#

P3[7:6], P2[7:6]

AHA

1100b

ALA

P3[5:4], P2[5:0]

FIGURE 4-11: B

YTE-VERIFY

384 ILL F08.1

Reads the code byte from the addres sed flas h memory location if the secur ity lock is not act ivated on that flas h memory block.

Page 33

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

4.2 In-Application Programming Mode

The device offers either 72 or 40 KByte of In-Application Programmable flash memory. During In-Application Programming, the CPU of the microcontroller enters IAP Mode. The two blocks of flash me mory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concu rre ntly. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SF AH, SFDT and SFCF) located in the Special Function Register (SFR), control and monitor the device’s erase and program process.

Table 4-6 outlines the commands and their associated mailbox re gister settings .

4.2.1 In-Application Programming Mode Clock Source

During IAP Mode, both the CPU core and the flash controller unit are dri ven off th e external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The inte rnal oscill ator is only tur ned on when required, and is turned off as soon as the flash operation is compl eted.

4.2.2 Memory Bank Selection for In-Application Programming Mode

With the addressing ran ge limited to 16 bit, only 64 KByte of program address sp ace is “visible” at a ny one time. As shown in Ta bl e 4-4, Bank Selection (the c onfiguration of EA# and SFCF[1:0]), allows Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The same c oncept is employed to allow both Block 0 and Block 1 flash to be acces sible to IAP operations. C ode fr om a b lo c k th at is not vi sib le ma y not be u sed

as a source to program another address. However , a b loc k that is not “visible” m ay be programmed by code from th e other block through mailbox registers.

The device allows IAP code in one block of memory to program the other block of memory, but may not program any location in the sam e block. If an IAP operation origi nates physically from Block 0, the target of this operation is implicitly defined to be in Blo ck 1. If the IAP op eratio n or igi nates physically from Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates from External program space, then, the target will depend on the address and the state of Bank Select.

4.2.3 IAP Enable Bit

The IAP Enable Bit, SFCF[6], e nables In-Application Pr ogramming mode. Until this bi t is set all flash pr ogramming IAP commands will be ignored.

4.2.4 In-Application Programming Mode Commands

All of the following commands c an only be initiat ed in the IAP Mode. In all situations, wri ting the control byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the security locks are enabled on the selected me mory bloc k.

The Program command is for programming new data int o the memory array. The portion of the memory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should first be erased with an appropriate Erase command. Warning: Do not attempt to

write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data.

The Block-Erase command erase s all bytes in one of the two memory blocks. The s elect ion of the memory block to be erased is determined by the source of Block-Erase Command, as defined in T abl e 4-4.

TABLE 4-4: IAP A

EA# SFCF[1:0] Address of IAP Inst. Target Addres s Block Being Programmed

1 00 >= 2000H (Block 0) >= 2000H (Block 0) None 1 00 >= 2000H (Block 0) < 2000H (Block 1) Block 1 1 00 < 2000H (Block 1) Any (Block 0) Block 0 1 01, 10, 11 Any (Block 0) >= 2000H (Block 0) None 1 01, 10, 11 Any (Block 0) < 2000H (Block 1) Block 1 0 00 From external >= 2000H (Block 0) Block 0 0 00 From external < 2000H (Block 1) Block 1 0 01, 10, 11 From external Any (Block 0) Block 0

1. No operation is performed because code from one block may not program the same originating block

DDRESS RESOLUTION FOR SST89E564/SST89V564

T4-4.5 384

Page 34

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

The Sector-Erase c ommand erases all of the bytes in a sector. The sector size for the flash memor y Blocks is 12 8 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SF AL.

The Byte-Program comm and programs data into a s ingle byte. The address is deter m ined by the contents of SFAH and SFAL. The data byte is in SFDT .

The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command.

Byte-Verify command returns th e data byte i n SFDT if the command is successful. The user is required to check that the previous flash operation has fully completed before issuing a Byte- Verify. By te-Verify comman d execution time is short enough that there is no need to poll for command completion and no interrupt is generated.

Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the Secur ity bits (see Table 8-1). Comp letion of any of these commands, the security options will be updated immediately.

Security bits previously in un-programmed state can be programmed by these commands. Prog-SB3, Prog-SB2 and Prog-SB1 commands should only reside in Block 1.

Prog-SC0 comman d is used to p rogram the SC0 bi t. This command only chang es the SC0 bit a nd has no effect on BSEL bit until after a reset cycle.

SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 command should reside only in Bl ock 1.

Prog-SC1 comman d is used to p rogram the SC1 bi t. This command only chang es the SC1 bit a nd has no effect on BSEL bit until after a reset cycle.

SC1 bit previously in un-programmed state can be programmed by this command. The Prog-SC1 command should reside only in Block 1.

There are no IAP counterparts for the External Host commands Select-Block0 and Select-Block1.

4.2.5 Polling

A command that uses the polling method to detect flash operation completi on s hould poll on the FLA SH_BUS Y bit (SFST[2]). When FLASH_BUSY de-asserts (logic 0), the device is ready for the next operation.

MOVC instruction may als o be used for verifi cation of th e Programming and Erase operation of the flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy.

4.2.6 Interrupt Termination

If interrupt ter mination is selected, (SFCM[7] is set), the n an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal in terrupt s ource. The INT 1# pin can now be us ed as a general purp ose po rt pin and it ca nnot be the so urce of External Interrupt 1 during In-Application Programming.

In order to use an interrupt to signal flash operation termination. EX1 and E A bi ts of IE r egi ster mus t be s et. The IT1 bit of TCON register must also be set for edge trigger detection.

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 4-5: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89 E564/S ST89V5 64

Operation SFCM [6:0]

Block-Erase Sector-Erase Byte-Program Byte-Ver ify (Read) Prog-SB1 Prog-SB2 Prog-SB3 Prog-SC0

1. SFCF[6]= 1 enables IAP commands; SFCF[6] =0 disables IAP commands.

2. Interrupt/Polling enable for flash operation completion

3. Refer to Table 4-4 for address resolution

4. X can be V

5. AH = Address high order byte

6. AL = Address low order byte

7. DI = Data Input

8. DO = Data Output

9. Instruction must be located in Block 1

3 9 9 9 9

SFCM[7] =1: Interrupt enable for flash operation completion

All other values are in hex

0: polling enable for flash operation completion

or VIH, but no other value.

0DH 55H X 0BH X AH 0EH DI 0CH DO

SFDT [7:0] SFAH [7:0] SFAL [7:0]

AH AL

AH AL 0FH AAH X X 03H AAH X X 05H AAH X X 09H AAH 5AH X

T4-5.8 384

TABLE 4-6: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89 E554/S ST89V5 54

Operation SFCM [6:0]

Block-Erase Sector-Erase Byte-Program Byte-Ver ify (Read) Prog-SB1 Prog-SB2 Prog-SB3 Prog-SC0 Prog-SC1

1. SFCF[6]= 1 enables IAP commands; SFCF[6] =0 disables IAP commands.

2. Interrupt/Polling enable for flash operation completion

3. Refer to Table 4-4 for address resolution

4. SFAH[7]=0: Selects Block 0; SFAH[7:5] = 111b selects Block 1

5. X can be VIL or VIH, but no other value.

6. AH = Address high order byte

7. AL = Address low order byte

8. DI = Data Input

9. DO = Data Output

10. Instruction must be located in Block 1

3 10 10 10 10 10

SFCM[7] =1: Interrupt enable for flash operation completion

0: polling enable for flash operation completion

All other values are in hex

0DH 55H AH 0BH X AH 0EH DI 0CH DO

SFDT [7:0] SFAH [7:0] SFAL [7:0]

4 6

AH AL

AH AL 0FH AAH X X 03H AAH X X 05H AAH X X 09H AAH 5AH X 09H AAH AAH X

T4-6.0 384

Page 36

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 4-7: F

Parameter

Reset Setup Time T Read-ID Command Width T PSEN# Setup Time T Address, Command, Data Setu p Time T Chip-Erase Time T Block-Erase Time T Sector-Erase Time T Program Setup Time T Address, Command, Data Hold T Byte-Program Time Select-Block Program Time T Security bit Program Time T Verify Command Delay Time T Verify High Order Address Delay Time T V eri fy Lo w Ord er Addres s Delay Time T

1. Program and Erase times will scale inversely proportional to programming clock frequency.

2. All timing measurements are from the 50% of the input to 50% of the output.

3. Each byte must be erased before programming.

LASH MEMORY PROGRAMMING/VERIF IC A TION PARAMETERS

1,2

Symbol Min Max Units

SU RD

ADS

BE SE

PROG

PSB

OA AHA ALA

3µs 1 µs

1.125 µs 0ns

1.2 µs 0ns

125 ms

100 ms

30 ms

50 µs

500 ns

80 µs 50 ns 50 ns 50 ns

T4-7.5 384

5.0 TIMERS/COUNTERS

The device has three 16 -bit regist ers that c an be used as either timers or event counters. The three Timers/Counters are denoted Timer 0 (T0), Timer 1 (T1) , and Time r 2 (T2). Each is design ated a pair of 8-bit regi sters in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2.

6.0 SERIAL I/O

6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART)

The device Serial I/O port is a full duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer ( SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the cont ents of the receive regi ster.

The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmis sion is initiated by any instructio n

that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set.

6.1.1 Framing Error Detection

Framing Error Detection allows the se ria l por t to au tomatically check for valid stop bits in Mo des 1, 2 or 3. If a stop bit is missing the Framing Error bit (F E) will be set. The software can then check this bit after a reception to detect communication errors. The FE bit must be cleared by software.

The FE bit is loc ated in SCON and sh ares the same bit address as SM0. The SMOD0 bit located in the PCON register determines which of these two bits is accessed. When SMOD0 = 0, SCON[7] will act as SM0. When SMOD0 = 1, SCON[7] will act as FE.

6.1.2 Automatic Address Recognition

Automatic Address Re cognition (AAR) reduces the CP U time required to ser vice th e seri al por t in a multi processor environment. When using AAR, the serial port hardware will only generate an interrupt when it receives its own address, thus eliminating the software overhead required to compare addresses.

Page 37

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications AAR is only available when using the serial port in either

mode 2 or 3. Setting the SM2 bit in SCON enables AAR. Each slave must have its SM2 bit set when waiting for an address (9th bi t = 1) . The R eceiv e Inte rrupt (R I) fla g will only be set when the recei ved byte matche s eithe r the G iven or Broadcast Address. The slave then clears its SM2 bit to enable reception of data bytes (9th bit = 0) from the master.

The master can selectively communicate with groups of slaves by sending the Given Address. Addressing all slaves is also possible by sending the Broadcas t address. The SADDR and SADEN special function registers define these addresses for each slave.

SADDR specifies a slaves indivi dua l ad dr es s and SADEN is a mask byte that defines don’t-care bits to form the Given address when com bi ned wi th S AD DR. The following is a n exampl e:

UART Slave 1

SADDR = 1111 0001

SADEN = 1111 1010

GIVEN = 1111 0x0x

UART Slave 2

SADDR = 1111 0011

SADEN = 1111 1001

GIVEN = 1111 0xx1

In this example Slave 1 can be distinguished from Slave 2 by using bits 0 and 1. Slave 1 will not respond to an address that ha s bi t 1 s et to 1 wh ile Slave 2 will. S imila r ly,

Slave 2 will not respond to an address that has bit 0 set to 0 while Slave 1 will. Both slaves will respond to an address of 1111 0x01b so this is t he Broa dcast Addre ss. The Broa dcast Addresses is formed by the logical OR of SADDR and SADEN with 0s treated as don’t-care bits.

6.2 Serial Peripheral Interface (SPI)

The device SPI allows for high-speed ful l-duplex synchronous data transfer between the device and o ther compat ible SPI devices.

Figure 6-1 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively . The SPI clock generator will start following a write to the master devices SPI data register. The written d ata is then shi fted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator i s stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are both set.

An external master dr ives the Slave Select inpu t pin, S S#/ P1[4], low to select the SPI module as a slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5] port can also be used as an input port pin.

CPHA and CPOL control the phase and polarity of the SPI clock. Figures 6-2 and 6-3 show the four possible combinations of these two bits.

MSB MASTER LSB

MISO MISO

8-bit Shift Register

MOSI MOSI

SPI

Clock Generator

FIGURE 6-1: SPI M

ASTER-SLAVE INTERCONNECTION

SCK SCK

SS# SS#

MSB SLAVE LSB

8-bit Shift Register

384 ILL F53.1

Page 38

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

SCK Cycle #

(for reference)

SCK (CPOL=0) SCK (CPOL=1)

MOSI

(from Master)

MISO

(from Slave)

SS# (to Slave)

* Not defined, but normally MSB of next received byte

12345678

MSB

654321LSB

FIGURE 6-2: SPI TRANSFER FORMAT WITH CPHA = 0

SCK Cycle #

(for reference)

SCK (CPOL=0)

12345678

4 3 2 1 LSB

384 ILL F54.1

SCK (CPOL=1)

(from Master)

MOSI

MISO

(from Slave)

SS# (to Slave)

* Not defined but normally LSB of previously transmitted character

MSB

654321 LSB

FIGURE 6-3: SPI TRANSFER FORMAT WITH CPHA = 1

4 3 2 1 LSB

384 ILL F55.1

Page 39

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

7.0 WATCHDOG TIMER

The devic e off ers a pro gram mable Wa tchdog Ti mer (WDT ) for fail safe protection against software dea dlock an d aut omatic recovery.

To protect th e system a gainst sof tware deadlo ck, the user software must refresh the W DT w ithin a us er-d efine d tim e period. If the software fails to do this perio dical refresh , an internal hardware reset will be initiated if enabled (WDRE=

1). The software can be designed such that the WDT times out if the program does not work properly .

The WDT in the device uses the syst em cl ock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a watchdog timer. The WDT registe r will i ncrement every 344064 cr ys tal clocks. The u pper 8- bits of th e time base register (WDTD) are used as the reload register of the WDT.

344064

clks

WDT Upper Byte

Ext. RST

CLK (XTAL1)

Counter

The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing “1” to it.

Figure 7-1 provides a block diagram of the WDT . Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle.

The time-out period of the WDT is calculated as follows:

Period = (255 - WDT) * 344064 * 1/f

OSC

where WDT is the value loaded in to the WDT regi s ter and

is the oscillator frequency.

OSC

WDT Reset

Internal Reset

FIGURE 7-1: B

WDTC

WDTD

LOCK DIAGRAM OF PROGRAMMA BLE WATCHDOG TIMER

384 ILL F10.2

Page 40

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

8.0 SECURITY LOCK

The Security Lock protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from acc idental erasing and pro gramming to the internal flash memory. There are two different types of security locks i n the d evic e security loc k system: Hard Loc k and SoftLock.

8.1 Hard Lock

When Hard Lock is activated, MOVC or IAP instructio ns executed from an unlocked or SoftLocked program address space, are disabled from reading code bytes in Hard Locked memory blocks (See Table 8-2). Hard Lock can either lock both flash memory blocks or just lock the 8 KByte flash memory block (Block 1). All External Host an d IAP commands except for Chip-Erase are ignored for memory blocks that are Hard Locked.

8.2 SoftLock

SoftLoc k allow s flash cont ents to be alt ered unde r a secure environment. This lock option allows the user to update program code in the SoftLocked memory block through InApplication Programming Mode under a predetermined secure environmen t. For example, if Block 1 ( 8K) m em or y block is locked (Hard Locked or SoftLocked), and Block 0 (64K for SST89E564/SS T89V564) memor y block is SoftLocke d, code residing in Bloc k 1 can prog ra m Bloc k 0. The following IAP mode commands issued through the com-

mand mailbox register, SFCM, executed from a Locked (Hard Locked or SoftLocked) block, can be operated on a SoftLocked block: Block-Erase, Sector-Erase, Byte-Program and B yte-Verify.

In External Host Mode, SoftLock behaves the sam e as a Hard Lock.

8.3 Security Lock Status

The three bits that indicate the device security lock status are located in S FST [7: 5]. A s shown in Fig ur e 81 and Table 8-1, the three s ec urity lock bits control th e lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the secur ity lock bits are programmed and both blocks are unlo cked. In the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via Byte-Verify. In t he t hir d level, three different options are available: Block 1 Hard Lock / Block 0 SoftLock, SoftLock on both blocks, and Hard Lock on both blocks. Locking both blocks is the same as Level 2 except read operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/program of internal memory or boot from external memory. Please note that for unused combinations of the security lock bits, the chip will default to Level 4 status. For details on how to program the security lock bits refer to the External Host Mode and In-Application Programming Section.

Level 1

Level 2

UPU/SS

UUU/NN

PUU/SS

UUP/LS

Level 3

UPP/LL PPU/LS

FIGURE 8-1: S

Notes: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked.

ECURITY LOCK LEVELS

PUP/LL UPP/LL

PPP/LL

Level 4

384 ILL F38.2

Page 41

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 8-1: SECURITY LOCK OPTIONS

Security Lock Bits

Level

1 000 U U U Unlock Unlock No Security Features are Enabled. 2 100 P U U SoftLock SoftLock MOVC instructions executed from

3 011

101

U P

010 U P U SoftLock SoftLock Level 2 plus Verify disabled. Code in

110 001

P U

4 111 P P P Hard Lock Hard Lock Same as Level 3 Hardlock/Hardlock,

1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1).

2. SFST[7:5 ] = Security Lock Decoding Bits (SECD)

1,2 1

SB3

Security Status of:

Block 1 Block 0

Security TypeSFST[7:5] SB1 SB2

external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled.

P U

Hard Lock Hard Lock Level 2 plus Verify disabled, both

blocks locked.

Block 1 ma y prog ram Blo ck 0 an d vice versa.

P U

Hard Lock SoftLock Level 2 plus Verify disabled. Code in

Block 1 may program Block 0.

but MCU will start code execution from the internal memory regardless of EA#.

T8-1.7 384

Page 42

SST89E564 / SST89V564 / SST89E554 / SST89V554

TABLE 8-2: SECURITY LOCK ACCESS TABLE

Source

Level SFST[7:5]

(Hard Lock on both blocks)

111b

011b/101b

(Hard Lock on both blocks)

001b/110b

(Block 0 = SoftLock, Block 1 = Hard Lock)

010b

(SoftLock on both blocks)

1. Location of MOVC instruction

2. External Host Byte-Verify access does not depend on a source address.

100b

000b

(Unlock)

Address

Block 0/1

External

Block 0/1

External

Block 0

Block 1

External

Block 0

Block 1

External

Block 0

Block 1

External

Block 0

Block 1

External

FlashFlex51 MCU

Preliminary Specifications

External Host

Target

Address

Byte-Verify

Allowed

Block 0/1 N N Y Y

External N/A N N N

Block 0/1 N N N N

External N/A N N N

Block 0/1 N N Y Y

External N N N Y

Block 0/1 N N N N

External N/A N Y Y

Block 0 N N Y Y Block 1 N N N N

External N/A N N Y

Block 0 N Y Y Y Block 1 N N Y Y

External N/A N N Y

Block 0/1 N N N N

External N/A N Y Y

Block 0 N N Y Y Block 1 N Y Y Y

External N/A N N Y

Block 0 N Y Y Y Block 1 N N Y Y

External N/A N N Y

Block 0/1 N N N N

External N/A N Y Y

Block 0 Y N Y Y Block 1 Y Y Y Y

External N/A N N Y

Block 0 Y Y Y Y Block 1 Y N Y Y

External N/A N N Y

Block 0/1 Y N N N

External N/A N Y Y

Block 0 Y N Y Y Block 1 Y Y Y Y

External N/A N N Y

Block 0 Y Y Y Y Block 1 Y N Y Y

External N/A N N Y

Block 0/1 Y Y N Y

External N/A N Y Y

IAP

Byte-Verify

Allowed

MOVC

Allowed

on 564

MOVC

Allowed

on 554

T8-2.1 384

Page 43

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

9.0 RESET

A system reset initializes the MCU and begins program execution at program memor y location 0000H. The r eset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycle s (24 clo cks), after the oscil lator becomes stable. ALE, PSE N# are weakly pulled hi gh dur ing reset. During reset, ALE and PSEN# output a high level in order to perform a prop er reset. This level must not be affected by external element. A system reset will not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-5 to 3-9.

9.1 Power-On Reset

At initial power up, the port pins will be in a random state until the oscill ator has star ted and the internal reset algorithm has weakly pulled all pins high. Powering up the

device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash.

When power is applied to the device, the RST pin must be held high long enoug h for the oscilla tor to st art up (usual ly sev eral milliseco nds f or a lo w freq uency crystal), i n addition to two machine cycles for a valid Power-On Reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to V through a 10 µF capac itor and to VSS through an 8.2KΩ resistor as shown in Figure 9-1. Note that if an RC circuit is being used, provi sion s s hou ld b e m ade to ensure th e V rise time does not exceed 1 mil lisecond and the osci llator start-up time doe s not e x ceed 10 millis econd s.

For a low frequency oscillator wit h slow start-up tim e the reset signal must be extended in order to a ccount for the slow start-up ti me. This method maintains the necessar y relationship between V

and RST to avoid programming

at an indeterm inate locati on, which may cause corr uption in the code of the fl ash. For more information on sy stem level design techniques, please r ev iew Design Considerations for the SST FlashFlex51 Family Microcontroller Application Note.

10µF

8.2K

FIGURE 9-1: P

OWER-ON RESET CIRCUIT

RST

SST89E5x4/V5x4

XTAL2

XTAL1

384 ILL F31.2

9.2 Software Reset

The software reset is executed by changing SFCF[1] (SWR) from “0” to “1”. A software reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.

9.3 Brown-out Detection Reset

The device includes a Brown-out detection circuit to protect the system from severe V

fluctuations. For Brown-out

voltage parameters, please refer to Tables 10-3 and 10-4. Brown-out interr upt ca n be ena bled by setting th e EBO bi t

in IEA register (address E8H, bit 3). If EBO bit is set and a Brown-out conditi on occurs, a Brown-out interr upt will be generated to execute the program at location 0 04BH. It is required that the EB O bit be cleare d by software after the Brown-out interrupt is serviced. Clearing EBO bit when the Brown-out condition is active will properly reset the device.

If Brown-out interrupt is not enabled, a Brown-out conditi on will reset the program to resume execution at location 0000H.

9.4 Interrupt Priority and Polling Sequence

The device suppor ts eight interrupt so urces under a four level priority scheme. Table 9-1 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector.

Page 44

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 9-1: I

Description Interrupt Flag

Ext. Int0 IE0 0003H EX0 PX0/H 1(highest) yes Brown-out BOF 004BH EBO PBO/H 2 no T0 TF0 000BH ET0 PT0/H 3 no Ext. Int1 IE1 0013H EX1 PX1/H 4 yes T1 TF1 001BH ET1 PT1/H 5 no UART/SPI TI/RI/SPIF 0023H ES PS/H 6 no T2 TF2, EXF2 002BH ET2 PT2/H 7 no

9.5 Power-Saving Modes

The device provides three power saving modes of operation for applications where p ower consumption is c ritical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock).

9.5.1 Idle Mode

Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program counter (PC) is stopped. The

NTERRUPT POLLING SEQUENCE

Vector

Address

Interrupt

Enable

The device exits Power Down mode through either an enabled external level sensitive interrupt or a hardware reset. The star t of the int errup t clears the PD bit a nd exits Power Do wn. Holding the external interrupt pin low restarts the oscillator, the signal must hol d low at least 1024 c lock cycles before bringing back high to complete the exit. After exit the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked Power Down mode. A hardware reset starts the device similar to power-on reset.

Interrupt

Priority

Arbitration

Ranking

Wake-Up

Power Down

system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode.

To exit properly out of Power Down, the reset or external interrupt should not be executed before the V restored to its normal operating voltage. Be sure to hold

The device exits Idle mo de through either a s ystem interrupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and

voltage long enough at its normal operating level for

the oscillator to restart and stabilize (normally less than 10 ms).

exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode. A ha rdware r ese t starts the device similar to a power-on reset.

9.5.2 Power Down Mode

The Power Down mode is entered by setting the PD bit in the PCON register. In the Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. T o retain the on-chip RAM and all of the special function registers’ values, the minim um V

level is 2.0V.

9.5.3 Standby Mode (Stop Clock)

Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software command and Standby mode is in itiated by extern al hardware gating off the external clock to the device.The on-chip SRAM and SFR data are maintained in Standby mode. The device resumes oper a tio n at t he n ext instruction when the clo ck is reapplied to the part.

T a ble 9- 2 outlines t he diff erent po wer-sa ving mo des, incl uding entry and exit procedures and MCU functionality .

T9-1.2 384

line is

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 9-2: POWER SAVING MODES

Mode Initiated by State of MCU Exited by

Idle Mode Software

(Set IDL bit in

PCON)

Power Down

Mode

Standby (Stop

Clock) Mode

External hardware gates OFF the external clock input to the MCU. This gating should be synchronized with an input clock transition (low-to-high or high-to-low).

Software

(Set PD bit in

PCON)

CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged.

CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during Power Down. External Interrupts are only active for level sensitive interrupts , if enabled.

CLK is frozen. On-chip SRAM and SFR data is maintained. ALE and PSEN# are maintained at the levels prior to the clock being frozen.

Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruc tion, program r esumes execution beginning at the instruction following the one that invoked Idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts t he device similar t o a power-on rese t.

Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power Down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power Down mode. A user could consider placing two or three NOP instructions after th e instruction that invokes Power Down mode to eliminate any problems. A hardware reset restarts the de vice s imilar to a power-on reset.

Gate ON external clock. Program execution resumes at the instruction following the one during which the clock was gated off.

T9-2.6 384

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FlashFlex51 MCU

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Preliminary Specifications

9.6 C lock Input Options

Shown in Figure 9-2 are the input and output of an internal inverting ampli fier (XTAL1, XTA L2), which can be configured for use as an on-chip oscillator.

When driving the device from an external clock source, XTAL2 sho uld be left disconnect ed and XTAL1 should be driven.

At star t-up, the external oscillat or may encoun ter a high er capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the V

and VIH specifications.

9.7 Recommended Capacitor Values for Crystal Oscillator

Crystal manufacturer, supply voltage, and other factors may cause circuit perfor mance to differ from one application to another. C1 and C2 shou ld be adjusted appropr iately for each design. The table be low, sh ows the typical values for C1 and C2 at a given fr equen cy. If following the satisfactory selection of all external components, the circuit is still over driven, a series resistor, Rs, may be added.

RECOMMENDED VALUES FOR CRYSTAL OSCILLATOR

Frequency C1 and C2 RS (Optional)

< 8MHz 90-110pF 100Ω

8-12MHz 18-22pF 200Ω

>12MHz 18-22pF 200Ω

More specific information about on-chip oscillator design can be found in FlashFlex 51 Oscillator Circuit Design Con- siderations Application Note.

Using the On-Chip Oscillator

FIGURE 9-2: O

SCILLATOR CHARACTERISTICS

XTAL2

XTAL1 Vss

EXTERNAL

OSCILLATOR

SIGNAL

External Clock Drive

XTAL2

XTAL1

Vss

384 ILL F12.0

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

10.0 ELECTRICAL SPECIFICATION

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to + 150°C

Voltage on EA# Pin to V Transient Voltage (<20ns) on Any Other Pin to V Maximum I Maximum I

per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

Package Power Dissipation Capability (T

Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption.

Note: This specification contains preliminary information on new products in production.

The specifications are subject to change without notice.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +6.5V

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

10.1 Operation Range

TABLE 10-1: OPERATING RANGE

Symbol Description Min. Max Unit

V f

OSC

Ambient Temperature Under Bias

Standard 0 +70 Industrial -40 +85 °C

Supply Voltage 2.7 5.5 V Oscillator Frequency

For In-Application Programming

040MHz

0.25 40 MHz

10.2 Reliability Characteristics

TABLE 10-2: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

END

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

mA JEDEC Standard 78

°C

T10-1.1 384

T10-2.0 384

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FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

10.3 DC Electrical Characteristics

TABLE 10-3: DC ELECTRICAL CHARACTERISTICS

= 0°C TO +70°C OR -40°C TO +85°C, 40MHZ DEVICES; 4.5-5.5V; V

amb

Symbol Parameter Test Conditions Min Max Units

IH1

OL1

Input Low Voltage 4.5 < VDD < 5.5 -0.5 0.2VDD - 0.1 V Input High Voltage 4.5 < VDD < 5.5 0.2VDD + 0.9 VDD + 0.5 V Input High Voltage (XTAL1, RST) 4.5 < VDD < 5.5 0.7V Output Low Voltage (Ports 1.5, 1.6, 1.7) VDD = 4.5V

= 16mA 1.0 V

Output Low Voltage (Ports 1, 2, 3)

Output Low Voltage (Port 0, ALE, PSEN#)

1,3

Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)

VDD = 4.5V

= 100µA

= 1.6mA

IOL = 3.5mA

2 2 2

VDD = 4.5V

= 200µA

IOL = 3.2mA

2 2

VDD = 4.5V

= -10µA VDD - 0.3 V

= -30µA VDD - 0.7 V

IOH = -60µA VDD - 1.5 V

OH1

Output Hi gh Voltage (Port 0 in External Bus Mode)

VDD = 4.5V

= -200µA VDD - 0.3 V

IOH = -3.2mA VDD - 0.7 V V I I I R C I

BOD IL TL LI

RST

IO DD

Brown-out Detection Vo ltage 3.85 4.15 V Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.4V -1 -75 µA Logical 1-to-0 Transition Current (Ports 1, 2, 3)

VIN = 2V -650 µA Input Leakage Current (Port 0) 0.45 < VIN < VDD-0.3 ±10 µA RST Pulldown Resistor 40 225 kΩ Pin Capacitance Power Supply Current

@ 1 MHz, 25°C 15 pF

In-Application Mode

@ 20 MHz 70 mA @ 40 MHz 88 mA

Active Mode

@ 20 MHz 25 mA @ 40 MHz 45 mA

Idle Mode

@ 20 MHz 9.5 mA @ 40 MHz 20 mA

Standby (Stop Clock) Mode T

= 0°C to +70°C 100 µA

amb

= -40°C to +85°C 125 µA

amb

Power Down Mode Minimum VDD = 2V

= 0°C to +70°C 40 µA

amb

= -40°C to +85°C 50 µA

amb

= 0V

VDD + 0.5 V

0.3 V

0.45 V

1.0 V

0.3 V

0.45 V

T10-3.4 384

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 10-4: DC ELECTRICAL CHARACTERISTICS

= 0°C TO +70°C OR -40°C TO +85°C, 25MHZ DEVICES; 2.7-3.6V; V

amb

Symbol Parameter Test Conditi ons Min Max Units

IH1

OL1

Input Low Voltage 2.7 < VDD < 3.3 -0.5 0.7 V Input High Voltage 2.7 < VDD < 3.3 0.2VDD + 0.9 VDD + 0.5 V Input High Voltage (XTAL1, RST) 2.7 < VDD < 3.3 0.7V Output Low Voltage (Ports 1.5, 1.6, 1.7) VDD = 2.7V

= 16mA 1.0 V

Output Low Voltage (Ports 1, 2, 3)

Output Low Voltage (Port 0, ALE, PSEN#)

1,3

Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)

VDD = 2.7V

= 100µA

= 1.6mA

= 3.5mA

VDD = 2.7V

= 200µA

= 3.2mA

VDD = 2.7V

2 2 2

2 2

IOH = -10µA VDD - 0.3 V

= -30µA VDD - 0.7 V

= -60µA VDD - 1.5 V

VDD = 2.7V

= -200µA VDD - 0.3 V

= -3.2mA VDD - 0.7 V

VIN = 2V -650 µA

@ 1 MHz, 25°C 15 pF

V I I I R C I

OH1

IL TL LI

BOD

RST IO

Output High Voltage (Port 0 in External Bus Mode)

Brown-out Detection Voltage 2.25 2.55 V Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.4V -1 -75 µA Logical 1-to-0 Transition Current (Ports 1, 2, 3)

Input Leakage Current (Port 0) 0.45 < VIN < VDD-0.3 ±10 µA RST Pulldown Resistor 225 kΩ Pin Capacitance Power Supply Current

In-Application Mode 70 mA Active Mode 22 mA Idle Mode 6.5 mA Standby (Stop Clock) Mode T

= 0°C to +70°C 70 µA

amb

= -40°C to +85°C 88 µA

amb

Power Down Mode Minimum VDD = 2V

= 0°C to +70°C 40 µA

amb

= -40°C to +85°C 50 µA

amb

1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum I Maximum I Maximum I

exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the

If I

listed test conditions.

2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.

per port pin: 15mA

per 8-bit port: 26mA

total for all outputs:71mA

s of ALE and Ports 1 & 3. The noise due

= 0V

VDD + 0.5 V

0.3 V

0.45 V

1.0 V

0.3 V

0.45 V

T10-4.4 384

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FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

4. Capacitive loading on Ports 0 & 2 may cause the V

on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when

the address bits are stabilizing.

5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2V.

6. Pin capacitance is characterized but not tested. EA# is 25pF (max).

7. See Figures 10-1, 10-2, 10-3 and 10-4 for test conditions. Minimum V

384 ILL F26.2

CLOCK SIGNAL

All other pins disconnected

(NC)

XTAL2 XTAL1

89x564

EA#RST

for Power Down is 2.0V.

(NC)

All other pins disconnected

XTAL2 XTAL1

DD = 2V

89x564

EA#RST

384 ILL F25.2

FIGURE 10-1: IDD TEST CONDITION,

CTIVE MODE

CLOCK SIGNAL

All other pins disconnected

(NC)

XTAL2 XTAL1

89x564

EA#RST

FIGURE 10-2: IDD TEST CONDITION,

DLE MODE

384 ILL F24.2

FIGURE 10-3: IDD TEST CONDITION,

OWER-DOWN M OD E

EA#RST

(NC)

All other pins disconnected

XTAL2 XTAL1

DD = 5V

89x564

FIGURE 10-4: IDD TEST CONDITION,

TANDBY (STOP CLOCK) MODE

384 ILL F33.2

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

10.4 AC Electrical Characteristics

AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load

Capacitance for All Other Outputs = 80pF)

TABLE 10-5: AC E

amb

Symbol Parameter

1/T T

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

CLCL

Oscillator Frequency ALE Pulse Width Address Valid to ALE Low

Address Hold After ALE Low

ALE Low to Valid Instr In

ALE Low to PSEN# Low

PSEN# Pulse Width PSEN# Low to Valid Instr In

Input Instr Hold After PSEN# Input Instr Float After PSEN#

Address to Valid Instr In

PSEN# Low to Address Float RD# Pulse Width

Write Pulse Width (WE#) RD# Low to Valid Data In

Data Hold After RD# Data Float After RD#

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD# or WR# Low Address to RD# or WR# Low

Data Valid to WR# High to Low Transition

Data Hold After WR#

LECTRICAL CHARACTERISTICS (1 OF 2)

= 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6 @25MHZ, 4.5-5.5 @ 40MHZ, VSS = 0

Oscillator

25MHz 40MHz Variable

Min Max Min Max Min Max

040MHz 65 35 2T 15 T

10 T

15 T

10 T

95 4T

55 4T

15 T

10 T

3T 3T

65 3T

25 3T

- 15 ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 65 (3V) ns

CLCL

- 45 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 25 (3V)

CLCL

- 15 (5V)

CLCL

- 55 (3V) ns

CLCL

- 50 (5V) ns

CLCL

0ns

35 T

10 T

120 5T

65 5T

- 5 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 80 (3V) ns

CLCL

- 60 (5V) ns

CLCL

10 10 10 ns

200

120

200

120

110 5T

75 5T

6T 6T

CLCL CLCL

- 40 (3V)

- 30 (5V)

- 40 (3V)

- 30 (5V)

- 90 (3V) ns

CLCL

- 50 (5V) ns

CLCL

00 0 ns

55 2T

38 2T

230 8T

150 8T

270 9T

150 9T

95 145

60 90

85 4T

70 4T

- 25 (3V)

CLCL

- 15 (5V)

CLCL

- 75 (3V) ns

CLCL

- 30 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 12 (5V) ns

CLCL

- 90 (3V) ns

CLCL

- 50 (5V) ns

CLCL

- 90 (3V) ns

CLCL

- 75 (5V) ns

CLCL

+ 25 (3V)

CLCL

+ 15 (5V)

CLCL

00 0 ns

13 T

- 27 (3V) ns

CLCL

- 20 (5V) ns

CLCL

Units

Page 52

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 10-5: AC ELECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2)

= 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6 @25MHZ, 4.5-5.5 @ 40MHZ, VSS = 0

amb

Oscillator

25MHz 40MHz Variable

Symbol Parameter

QVWH

RLAZ

WHLH

Data Valid to WR# High

RD# Low to Address Float 0 0 0 ns

RD# to WR# High to ALE High 43 123 T

Min Max Min Max Min Max

433 7T

125 7T

10 40 T

- 70 (3V) ns

CLCL

- 50 (5V) ns

CLCL

- 25 (3V) T

CLCL

- 15 (5V) T

CLCL

+ 25 (3V) ns

CLCL

+ 15 (5V) ns

CLCL

10.5 AC Characteristics

Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for

time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.

A: Address Q: Output data C: Clock R: RD# signal D: Input data T: Time H: Logic level HIGH V: Valid I: Instruction (program memory contents) W: WR# signal L: Logic level LOW or ALE X: No longer a valid logic level P: PSEN# Z: High Impedance (Float)

Units

T10-5.5 384

For example:

= Time from Address Valid to ALE Low

AVLL

= Time from ALE Low to PSEN# Low

LLPL

IHT

ILT

AC Inputs during testing are driven at V V

(0.45V) for a Logic "0". Measurement reference points for inputs and

ILT

outputs are at V

FIGURE 10-5: AC T

(VDD -0.5V) for Logic "1" and

IHT

(0.2VDD + 0.9) and VLT (0.2VDD - 0.1)

Note: VHT- V VLT- V V

IHT-VINPUT

ILT

ESTING INPUT/OUTPUT, FLOAT WAVEFORM

- V

HIGH LOW

INPUT

Test

HIGH Test LOW Test

+0.1V

LOAD

-0.1V

LOAD

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/I

Timing Reference

Points

384 ILL F28b.0384 ILL F28a.2

-0.1V

+0.1V

= ± 20mA.

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FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

LHLL

ALE

PLAZ

LLIV

PLIV

PXIZ

PXIX

INSTR IN

AVLL

LLPL

PSEN#

LLAX

PORT 0

PORT 2

A7 - A0

AVIV

A15 - A8

FIGURE 10-6: EXTERNAL PROGRAM MEMORY READ CYCLE

PLPH

A7 - A0

A15 - A8

384 ILL F13.0

LHLL

ALE

PSEN#

RD#

PORT 0

PORT 2

AVLL

A7-A0 FROM RI or DPL

AVWL

P2[7:0] or A15-A8 FROM DPH

AVDV

LLWL

LLAX

RLAZ

LLDV

FIGURE 10-7: EXTERNAL DATA MEMORY READ CYCLE

RLRH

RLDV

DATA IN

WHLH

RHDZ

RHDX A7-A0 FROM PCL

A15-A8 FROM PCH

INSTR IN

384 ILL F14.0

Page 54

ALE

PSEN#

LHLL

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

WHLH

LLWL

WR#

PORT 0

PORT 2

AVLL

A7-A0 FROM RI or DPL

LLAX

QVWX

AVWL

P2[7:0] or A15-A8 FROM DPH

FIGURE 10-8: EXTERNAL DATA MEMORY WRITE CYCLE

TABLE 10-6: EXTERNAL CLOCK DRIVE

25MHz 40MHz Variable

Symbol Parameter

1/T T

CHCX

CLCX

CLCH

CHCL

CLCL

Oscillator F requency 0 40 MHz High Time 0.35T Low Time 0.35T Rise Time 20 10 ns Fall Time 20 10 ns

MinMaxMinMax Min Max

WLWH

QVWH

DATA OUT

WHQX

A7-A0 FROM PCL

Oscillator

INSTR IN

A15-A8 FROM PCH

384 ILL F15.0

CLCL CLCL

0.65T

CLCL CLCL

Units

ns ns

T10-6.2 384

DD = -0.5

0.45 V

0.7 V

0.2 VDD -0.1

CHCL

CLCX

CLCL

CHCX

CLCH

384 ILL F30.0

FIGURE 10-9: EXTERNAL CLOCK DRIVE WAVEFORM

Page 55

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 10-7: SERIAL PORT TIMING

25MHz 40MHz Variable

Symbol Parameter

XLXL

QVXH

XHQX

XHDX

XHDV

Serial Port Clock Cycle Time 0 0.36 12T Output Data Setup to Clock Rising Edge 700 117 10T Output Data Hold After Clock Rising Edge 5 0 2T

Input Data Hold After Clock Rising Edge 0 0 0 ns Clock Rising Edge to Input Data Valid 700 117 10T

Min Max Min Max Min Max

02T

Oscillator

CLCL

- 133 ns

- 117 ns

- 50 ns

- 133 ns

CLCL

T10-7.2 384

Units

INSTRUCTION

ALE

1 2 3 4 5 6 7 8

XLXL

CLOCK

XHDV

XHQX

XHDX

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

QVXH

01 234 567

VALID VALID VALID VALID VALID VALID VALID VALID

FIGURE 10-10: SHIFT REGIST ER MODE TIMING WAVEFORMS

SET TI

SET R I

384 ILL F29.0

Page 56

SST89E564 / SST89V564 / SST89E554 / SST89V554

11.0 PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

FlashFlex51 MCU

Preliminary Specifications

SST89

x5x4 -XX -X-X X

Package Modifier

I = 40 pins J = 44 pins

Package Type

P = PDIP N = PLCC TQ = TQFP

Operation Temperature

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Operating Frequency

25 = 0-25MHz 40 = 0-40MHz

Feature Set and Flash Memory Size

564 = C52 feature set + 64(72)* KByte 554 = C52 feature set + 32(40)* KByte * = 8K additional flash can be enabled

Voltage Range

E = 4.5-5.5V V = 2.7-3.6V

Device Family

89 = C51 Core

11.1 Valid Combinations

Valid combinations for SST89E564

SST89E564-40-C-PI SST89E564-40-C-NJ SST89E564-40-C-TQJ SST89E564-40-I-PI SST89E564-40-I-NJ SST89E564-40-I-TQJ

Valid combinations for SST89V564

SST89V564-25-C-PI SST89V564-25-C-NJ SST89V564-25-C-TQJ SST89V564-25-I-PI SST89V564-25-I-NJ SST89V564-25-I-TQJ

Valid combinations for SST89E554

SST89E554-40-C-PI SST89E554-40-C-NJ SST89E554-40-C-TQJ SST89E554-40-I-PI SST89E554-40-I-NJ SST89E554-40-I-TQJ

Valid combinations for SST89V554

SST89V554-25-C-PI SST89V554-25-C-NJ SST89V554-25-C-TQJ SST89V554-25-I-PI SST89V554-25-I-NJ SST89V554-25-I-TQJ

Note: Valid combination s are those prod ucts in mass product ion or w il l be in mass pro ducti on.

Consult your SST sales repre sent ati v e to confirm availability of valid combinations an d to det ermine availability of new combinations.

Page 57

FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

12.0 PACKAGING DIAGRAMS

Pin #1 Identifier

.065 .075

2.020

2.070

12˚

4 places

.600 .625

.530 .557

Base Plane

Seating Plane

.015 Min.

.063 .090

Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent.

† = JEDEC min is .115; SST min is less stringent

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.045 .055

40-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

ACKAGE CODE: PI

SST P

TOP VIEW SIDE VIEW BOTTOM VIEW

.685

Optional

Pin #1 Identifier

.685 .695

.042 .048

.646 .656

.042 .048

†

.695 .646 .656

144

†

.015 .022

.020 R. MAX.

.026 .032

.042 .056

.100 BSC

x45˚

.147 .158

.013 .021

.025 .045

.100 † .200

.500 REF.

.220 Max.

.590 .630

.008 .012

.600 BSC

40.pdipPI-ILL.7

0˚

15˚

.050 BSC.

.020 Min.

.165 .180

.100 .112

.026 .032

44.PLCC.NJ-ILL.7

.050 BSC.

Note: 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent.

44-

LEAD PLASTIC LEA D CHIP CARRIER (PLCC)

ACKAGE CODE: NJ

SST P

† = JEDEC min is .650; SST min is less stringent

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

Page 58

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

10.00 BSC

12.00 BSC

.09 .20

.30 .45

.80 BSC

.95

1.05

Pin #1 Identifier

1.2

max.

Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±0.05) mm.

4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.

10.00 BSC

12.00 BSC

44-LEAD THIN QUAD FLAT PACK (TQFP)

ACKAGE CODE: TQJ

SST P

.05 .15

1.00 ref

44.tqfp-TQJ-ILL.6

.45 .75

0˚- 7˚

Silicon Storage Technolog y, Inc. • 1171 Sonora Court • Sunnyvale , CA 940 86 • Telephone 408-735-9110 • Fax 408-735 -90 36

www.SuperFlash.com or www.ssti.com

Datasheet SST89V564-40-I-TQJ, SST89V564-40-I-TQI, SST89V564-40-I-PJ, SST89V564-40-I-PI, SST89V564-40-I-NJ Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual