Datasheet FSST89E52RD2, SST89E54RD2, SST89E58RD2, SST89E516RD2, SST89V52RD2 Datasheet (Silicon Storage Technology)

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查询SST89E516RD2供应商

SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

FlashFlex51 MCU

SST89E/V516 / 58 / 54 / 52RD2 FlashFlex51 MCU

FEATURES:

• 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory

– Fully Software Compatible – Development Toolset Compatible – Pin-For-Pin Package Compatible

• SST89E5xxRD2 Operation

– 0 to 40 MHz at 5V

• SST89V5xxRD2 Operation

– 0 to 33 MHz at 3V

• 1 KByte Internal RAM

• Dual Block SuperFlash EEPROM

– 8/16/32/64 KByte primary block +

8 KByte secondary block

(128-Byte sector size for both blocks) – Individual Block Security Lock with SoftLock – Concurrent Operation during

In-Application Programming (IAP) – Memory Overlay for Interrupt Support during IAP

• Support External Address Range up to 64 KByte of Program and Data Memory

• Three High-Current Drive Ports (16 mA each)

• Three 16-bit Timers/Counters

• Full-Duplex, Enhanced UART

– Framing Error Detection – Automatic Address Recognition

Preliminary Specifications

• Ten Interrupt Sources at 4 Priority Levels

– Four External Interrupt Inputs

• Programmable Watchdog Timer (WDT)

• Programmable Counter Array (PCA)

• Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port

• Second DPTR register

• Low EMI Mode (Inhibit ALE)

• SPI Serial Interface

• Standard 12 Clo c k s p e r cycle, the de vi ce h as an option to dou b le th e sp eed t o 6 c l oc ks pe r c yc l e.

• TTL- and CMOS-Compatible Logic Levels

• Brown-out Detection

• Low Power Modes

– Power-down Mode with External Interrupt Wake-up – Idle Mode

• Temperature Ranges:

– Commercial (0°C to +70°C) – Industrial (-40°C to +85°C)

• Packages Available

– 44-lead PLCC – 40-pin PDIP (Port 4 feature not available) – 44-lead TQFP

PRODUCT DESCRIPTION

The SST89E5xxRD2 and SST89V5xxRD2 are mem bers of the FlashFlex51 family of 8-bit microcontroller products designed and m anufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design a nd thick-oxide tunn elin g injector offer significant cost and reliability benefits for SST’s customers. The device s use the 8051 ins truction set and are pin-for-pin compatible with standard 8051 microcontroller devices .

The devices come with 16/24/40/72 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 8/16/32/64 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.

The 8-KByte seco ndary bloc k can be map ped to the lowest location of th e 8/16 /32 /64 KB yte addr ess spac e; i t can a lso be hidden from the program counter and used as an independent EEPROM-like data memory.

The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.

In addition to the 16/24/ 40 /72 KByte of EE PROM program memory on- chip, the devices can addre ss up to 64 KByte of external program memor y. In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.

The flash memor y blocks can be programmed via a sta ndard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST’s devices. During poweron reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in- appli ca tion prog r amm ing (I AP) oper ation. The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The devices are pre-programmed wit h an example of the bootstrap loader in the memory , demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the user’s reference and convenience only; SST does not guarantee its functionality or usefulness. Chip-Erase or Block-Erase operations will erase the pr e-pro gra mmed sa mple code .

These specifications are subject to change without notice.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE OF CONTENTS

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Data RAM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Expanded Data RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 Dual Data Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1 External Host Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.0 TIMERS/COUNTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2 Timer Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3 Programmable Clock-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1 Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.0 PROGRAMMABLE COUNTER ARRAY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.1 PCA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.2 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.3 Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

9.0 SECURITY LOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.0 INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.1 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

13.0 SYSTEM CLOCK AND CLOCK OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

13.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . . . . . . 67

13.2 Clock Doubling Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

14.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

14.2 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

14.3 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . . . . . 82

15.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

16.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

LIST OF FIGURES

FIGURE2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FIGURE2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FIGURE2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FIGURE3-1: Program Memory Organization for 8 KByte SST89E/V52RD2. . . . . . . . . . . . . . . . . . . . . . . . 11

FIGURE3-2: Program Memory Organization for 16 KByte SST89E/V54RD2. . . . . . . . . . . . . . . . . . . . . . . 12

FIGURE3-3: Program Memory Organization for 32 KByte SST89E/V58RD2. . . . . . . . . . . . . . . . . . . . . . . 12

FIGURE3-4: Program Memory Organization for 64 KByte SST89E/V516RD2. . . . . . . . . . . . . . . . . . . . . . 13

FIGURE3-5: Internal and External Data Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FIGURE3-6: Dual Data Pointer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

FIGURE4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FIGURE6-1: Framing Error Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

FIGURE6-2: UART Timings in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FIGURE6-3: UART Timings in Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FIGURE6-4: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

FIGURE6-5: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FIGURE6-6: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FIGURE7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

FIGURE8-1: PCA Timer/Counter and Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

FIGURE8-2: PCA Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

FIGURE8-3: PCA Compare Mode (Software Timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

FIGURE8-4: PCA High Speed Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FIGURE8-5: PCA Pulse Width Modulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

FIGURE8-6: PCA Watchdog Timer (Module 4 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

FIGURE9-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

FIGURE10-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

FIGURE11-1: Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

FIGURE13-1: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

FIGURE14-1: I FIGURE14-2: I

FIGURE14-3: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

FIGURE14-4: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

FIGURE14-5: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

FIGURE14-6: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

FIGURE14-7: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FIGURE14-8: AC Testing Input/Output Test Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FIGURE14-9: Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

FIGURE14-10: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

FIGURE14-11: I FIGURE14-12: I FIGURE14-13: I

FIGURE14-14: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

vs. Frequency for 3V SST89V5xxRD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

vs. Frequency for 5V SST89E5xxRD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Test Condition, Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Test Condition, Idle Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Test Condition, Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

FIGURE14-15: Select-Block1 / Select-Block0 (For SST89E/V516RD2 only) . . . . . . . . . . . . . . . . . . . . . . . 82

FIGURE14-16: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

FIGURE14-17: Block-Erase for SST89E/V516RD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

FIGURE14-18: Block-Erase for SST89E/V5xRD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

FIGURE14-19: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

FIGURE14-20: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

FIGURE14-21: Prog-SB1 / Prog-SB2 / Prog-SB3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

FIGURE14-22: Prog-SC0 / Prog-SC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

FIGURE14-23: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

LIST OF TABLES

TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E/V516RD2 . . . . . . . . . . . . . 13

TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E/V5xRD2 . . . . . . . . . . . . . . 13

TABLE 3-3: SFCF Values Under Different Reset Conditions (SST89E/V5xRD2) . . . . . . . . . . . . . . . . . . . 14

TABLE 3-4: SFCF Values Under Different Reset Conditions (SST89E/V516RD2) . . . . . . . . . . . . . . . . . . 14

TABLE 3-5: External Data Memory RD#, WR# with EXTRAM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 3-6: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 3-7: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TABLE 3-8: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TABLE 3-9: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TABLE 3-10: Timer/Counters SFRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TABLE 3-11: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TABLE 3-12: PCA SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TABLE 4-1: External Host Mode Commands for SST89E/V5xRD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TABLE 4-2: External Host Mode Commands for SST89E/V516RD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

TABLE 4-3: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

TABLE 4-4: Additional Read Commands in External Host Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TABLE 4-5: IAP Address Resolution for SST89E/V516RD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TABLE 4-6: IAP Commands for SST89E/V516RD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

TABLE 4-7: IAP Commands for SST89E/V5xRD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

TABLE 5-1: Timer/Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TABLE 5-2: Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TABLE 5-3: Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TABLE 8-1: PCA Timer/Counter Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

TABLE 8-2: PCA Timer/Counter Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

TABLE 8-3: CMOD Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

TABLE 8-4: PCA High and Low Register Compare/Capture Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

TABLE 8-5: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

TABLE 8-6: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

TABLE 8-7: Pulse Width Modulator Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Page 6

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 9-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

TABLE 9-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

TABLE 11-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

TABLE 12-1: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

TABLE 13-1: Recommended Values for C1 and C2 by Crystal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

TABLE 13-2: Clock Doubling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

TABLE 14-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

TABLE 14-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

TABLE 14-3: AC Conditions of Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

TABLE 14-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

TABLE 14-5: Pin Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

TABLE 14-6: DC Electrical Characteristics for SST89E5xxRD2: V TABLE 14-7: DC Electrical Characteristics for SST89V5xxRD2: V

TABLE 14-8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

TABLE 14-9: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

TABLE 14-10: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

TABLE 14-11: External Mode Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . 81

TABLE 16-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

= 4.5-5.5V . . . . . . . . . . . . . . . . . . . 70

= 2.7-3.6V . . . . . . . . . . . . . . . . . . . 72

Page 7

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

1.0 FUNCTIONAL BLOCKS

FUNCTIONAL BLOCK DIAGRAM

8051

CPU Core

ALU,

ACC,

B-Register,

Instruction Register,

Program Counter,

Timing and Control

Oscillator

Interrupt

Control

Preliminary Specifications

10 Interrupts

Watchdog Timer

SuperFlash

EEPROM

Primary

Block

8K/16K/32K/64K x8

Secondary

Block 8K x8

Timer 0 (16-bit)

Timer 1 (16-bit)

Timer 2 (16-bit)

PCA

Security

Lock

Flash Control Unit

RAM

1K x8

I/O Port 0

I/O Port 1

I/O Port 2

I/O Port 3

I/O Port 4

SPI

Enhanced

UART

1255 B1.0

I/O

Page 8

SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

2.0 PIN ASSIGNMENTS

(T2) P1.0

(T2 EX) P1.1

(ECI) P1.2

(CEX0) P1.3

(CEX1 / SS#) P1.4

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

(T1) P3.5

(WR#) P3.6

(RD#) P3.7

XTAL2

XTAL1

40-pin PDIP

To p Vi ew

DD P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

ALE/PROG#

PSEN#

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

(RXD) P3.0

INT2#/P4.3

(TXD) P3.1

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

(T1) P3.5

FlashFlex51 MCU

P1.4 (SS# / CEX1)

P1.3 (CEX0)

P1.2 (ECI)

P1.1 (T2 EX)

P1.0 (T2)

P4.2/INT3#

VDDP0.0 (AD0)

P0.1 (AD1)

44 43 42 41 40 39 38 37 36 35 34

44-lead TQFP

Top View

12 13 14 15 16 17 18 19 20 21 22

P4.0

XTAL2

XTAL1

(A8) P2.0

(A9) P2.1

(RD#) P3.7

(WR#) P3.6

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

(A12) P2.4

(A11) P2.3

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

P4.1

ALE/PROG#

PSEN#

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

1255 44-tqfp TQJ P2.0

1255 40-pdip PI P1.0

FIGURE 2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP

P1.4 (SS# / CEX1)

P1.3 (CEX0)

6 5 4 3 2 1 44 43 42 41 40

RST

18 19 20 21 22 23 24 25 26 27 28

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

(RXD) P3.0

INT2#/P4.3

(TXD) P3.1

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

(T1) P3.5

P1.2 (ECI)

P1.1 (T2 EX)

P1.0 (T2)

44-lead PLCC

Top View

FIGURE 2-2: P

P4.2/INT3#

VDDP0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

IN ASSIGNMENTS FOR 44-LEAD TQFP

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

P4.1

ALE/PROG#

PSEN#

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

XTAL1

P4.0

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

1255 44-plcc NJ P3.0

(A12) P2.4

XTAL2

(RD#) P3.7

(WR#) P3.6

FIGURE 2-3: P

IN ASSIGNMENTS FOR 44-LEAD PLCC

Page 9

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

2.1 Pin Descriptions

TABLE 2-1: PIN DESCRIPTIONS (1 OF 2)

pull-ups

pull-up

Name and Functions

sink several LS TTL inputs. Port 0 pins float that have ‘1’s written to them, and in this state can be used as high-imped ance inputs . P ort 0 is also the multi ple x ed low -order addres s and data bus during accesse s to e xte rnal memory. In this applic ation, it uses stro ng internal pull ups when transitioning to V mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification.

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode programming and verification.

This signal is the external clock input for the PCA timer/counter.

Each compare/capture module connects to a Port 1 pin for external I/O. When not used by the PCA, this pin can handle standard I/O.

OR CEX1: Compare/Capture Module External I/O

OR CEX2: Compare/Capture Module External I/O

OR CEX3: Compare/Capture Module External I/O

OR CEX4: Compare/Capture Module External I/O

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled

high by the in ternal pul l-up s when “1”s are written to them an d c an be used as inputs in th is state. As inputs , Port 2 pins that are ex ternally pulled low will s ource c urre nt because of the internal pull-ups. Port 2 sends the high-ord er ad dre ss byte during fetch es from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to

. Port 2 also receives some control signals and a partial of high-order address bits dur-

ing the external host mode programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buff-

ers can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification.

Port 0 also receives the code bytes during the external host

OH.

Symbol Type

P0[7:0] I/O Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can

P1[7:0] I/O with internal

P1[0] I/O T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 P1[1] I T2EX: Timer/Counter 2 capture/reload trigger and direction control P1[2] I ECI: PCA Timer/Counter External Input:

P1[3] I/O CEX0: Compare/Capture Module External I/O

P1[4] I/O SS#: Master Input or Slave Output for SPI.

P1[5] I/O MOSI: Master Output line, Slave Input line for SPI

P1[6] I/O MISO: Master Input line, Slave Output line for SPI

P1[7] I/O SCK: Master clock output, slave clock input line for SPI

P2[7:0] I/O with internal

P3[7:0] I/O with internal

P3[0] I RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input P3[1] O TXD: UART - Transmit output P3[2] I INT0#: External Interrupt 0 Input

Page 10

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 2-1: PIN DE SCRIPTIONS (CONTINUED) (2 OF 2)

Symbol Type

P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe

PSEN# I/O Program Store Enable: PSEN# is the Read strobe to External Program Store. When the

RST I Reset: While the oscillator is running, a high logic state on this pin for two machine cycles

EA# I External Access Enable: EA# must be driven to V

ALE/PROG# I/O Address Latch Enable: ALE is the output signal for latching the low byte of the address

P4[3:0]

I/O with internal

P4[0] I/O Bit 0 of port 4

P4[1] I/O Bit 1 of port 4 P4[2] / INT3# I/O Bit 2 of port 4 / INT3# External interrupt 3 input P4[3] / INT2# I/O Bit 3 of port 4 / INT2# External interrupt 2 input

XTAL1 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

XTAL2 O Crystal 2: Output from the inverting oscillator amplifier

1. I = Input; O = Output

2. It is not necessary to receive a 12V programming supply voltage during flash programming.

3. ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor of 3-50 KΩ to V

4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency.

5. Port 4 is not present on the PDIP package.

Name and Functions

device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except when access to External Data Memory while one PSEN# activation is skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while the RST input is co ntinually held high for more than ten machine cycles will cause the device to enter External Host mode for programming.

will reset the device . After a reset, if the PSEN# pin is driv en by a high-to-lo w input trans ition while the RST input pi n is he ld hig h, the device will ent er th e External Ho st mode , o therwi se the device will enter the Normal operation mode.

code from the External Program Memory. EA# must be driven to V execution. However, Security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage2 of 12V.

during an access to external memory. This pin is also the programming pulse input (PROG#) for flash prog r a mm in g. No rmally the ALE3 is emitted at a constant rate of 1/6 the crystal frequency skipped during each access to external data memory. However, if AO is set to 1, ALE is disabled.

Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. The port 4 output buff-

pull-ups

ers can drive LS T TL inputs . P ort 4 pins are p ulled hig h by the internal pull -ups when ‘ 1’ s are written to them and can be used as inputs in this state. As inputs, port 4 pins that are externally pulled low will source current because of the internal pull-ups.

circuits.

I Power Suppl y I Ground

in order to enable the device to fetch

and can be used for external timing and clocking. One ALE pulse is

, e.g. for ALE pin.

for internal program

T2-1.0 1255

Page 11

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

3.0 MEMORY ORGANIZATION

Preliminary Specifications

The device has separate addr e ss s pa ce s for program an d data memory.

3.1 Program Flash Memory

There are two internal flash memory blocks in the device. The primar y flash memor y block (Block 0) has 8/16/3 2/64 KByte. The secondary flash memory block (Block 1) has 8 KByte. Since the total program address space is limited to 64 KByte, the SF CF[1:0] bit are used to control pro gram

EA# = 1

SFCF[1:0] = 00

E000H

8 KByte

Block 1

FFFFH

EA# = 0

FFFFH

DFFFH

bank selectio n. Pleas e re fer to Figur es 3-1 t hrou gh 3- 4 for the program memor y configuration. Program bank sele ction is described in the next section.

The 8K/16K/32K/64K x8 primary SuperFlash block is organized as 64/128/256/51 2 sectors, each sector consists of 128 Bytes.

The 8K x8 secondary SuperFlash block is organized as 64 sectors, each sector consists also of 128 Bytes.

For both blocks, the 7 least significant program address bits select the byte within the sector. The remainder of the program addr ess bi ts selec t the sect or with in the bloc k.

EA# = 1

SFCF[1:0] = 10, 11

FFFFH

E000H

DFFFH

EA# = 1

SFCF[1:0] = 01

8 KByte

Block 1

FFFFH

External

64 KByte

0000H

FIGURE 3-1: P

Not

Accessible

2000H

1FFFH

0000H

ROGRAM MEMORY ORGANIZATION FOR 8 KBYTE SST89E/V52RD2

8 KByte

Block 1

8000H

7FFFH

0000H

Not

Accessible

8 KByte

Block 0

7FFFH

8000H

0000H

Not

Accessible

8 KByte

Block 0

1255 F01.0

Page 12

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

FFFFH

0000H

EA# = 0

External

64 KByte

FFFFH

E000H

DFFFH

8000H

7FFFH

2000H

1FFFH

0000H

EA# = 1

SFCF[1:0] = 00

8 KByte

Block 1

Not

Accessible

8 KByte

Block 0

8 KByte

Block 1

FFFFH

E000H

DFFFH

8000H

7FFFH

0000H

EA# = 1

SFCF[1:0] = 01

8 KByte

Block 1

Not

Accessible

16 KByte

Block 0

SFCF[1:0] = 10, 11

FFFFH

8000H

7FFFH

0000H

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION FOR 16 KBYTE SST89E/V54RD2

EA# = 1

Not

Accessible

16 KByte

Block 0

1255 F02.0

FFFFH

0000H

FIGURE 3-3: P

EA# = 0

External

64 KByte

FFFFH

E000H

DFFFH

8000H

7FFFH

2000H

1FFFH

0000H

EA# = 1

SFCF[1:0] = 00

8 KByte

Block 1

External

24 KByte

Block 0

8 KByte

Block 1

FFFFH

E000H

DFFFH

8000H

7FFFH

0000H

EA# = 1

SFCF[1:0] = 01

8 KByte

Block 1

External

24 KByte

32 KByte

Block 0

SFCF[1:0] = 10, 11

FFFFH

8000H

7FFFH

0000H

ROGRAM MEMORY ORGANIZATION FOR 32 KBYTE SST89E/V58RD2

EA# = 1

External

32 KByte

Block 0

1255 F03.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

EA# = 1

64 KByte

Block 0

1255 F04.0

FFFFH

0000H

EA# = 0

External

64 KByte

FFFFH

2000H

1FFFH

0000H

EA# = 1

SFCF[1:0] = 00

56 KByte

Block 0

8 KByte

Block 1

SFCF[1:0] = 01, 10, 11

FFFFH

0000H

FIGURE 3-4: PROGRAM MEMORY ORGANIZATION FOR 64 KBYTE SST89E/V516RD2

3.2 Program Memory Block Switching

The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block 0 to be used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching.

TABLE 3-1: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST8 9E/V5 16RD2

SFCF[1:0] Program Memory Block Switching

01, 10, 11 Block 1 is not visible to the program counter (PC).

Block 1 is reachable only via in-application programming from 0000H - 1FFFH.

00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.

When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0. Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through in-application programming.

T3-1.0 1255

TABLE 3-2: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST8 9E/V5 XRD2

SFCF[1:0] Program Memory Block Switching

10, 11 Block 1 is not visible to the PC;

Block 1 is reachable only via in-application programming from E000H - FFFFH.

01 Both Block 0 and Block 1 are visible to the PC.

Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH.

00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH.

T3-2.0 1255

Page 14

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

3.2.1 Reset Configuration of Program Memory Block Switching

Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0 and/or SC1. The SC0 an d SC1 bits are programmed via an external host mode co mmand or an IAP Mode command. See T able 4-1, Table 4-6, and Tabl e 4-7.

Once out of reset, the SFCF[0] bit can be changed dynamically by the progr am f or desir ed eff ects . Changing SFCF[0] will not change the SC0 bit.

Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different physical memory to be mapped to the logical pr ogram address space. The user must avoid executing block switching instructions within the address range 0000H to 1FFFH.

TABLE 3-3: SFCF V

SC1

U (1) U (1) 00

U (1) P (0) 01 x1 11 P (0) U (1) 10 10 10 P (0) P (0) 11 11 11

1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1)

SC0

ALUES UNDER DIFFERENT

ESET CONDITIONS (SST89E/V5XRD2)

State of SFCF[1:0] after:

Power-on

External

Reset

(default)

WDT Reset

Brown-out

Reset

x0 10

Software

Reset

T3-3.0 1255

TABLE 3-4: SFCF VALUES UNDER DIFFERENT

ESET CONDITIONS (SST89E/V516RD2)

State of SFCF[1:0] after:

Power-on

External

SC0

U (1) 00

P (0) 01 x1 11

1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1)

Reset

(default)

WDT Reset

Brown-out

Reset

x0 10

Software

Reset

T3-4.0 1255

3.3 Data RAM Memory

The data RAM has 1024 bytes of internal memor y. The RAM can be addressed up to 64KB for external data memory .

3.4 Expanded Data RAM Addressing

The SST89E/V554A both have the capability of 1K of RAM. See Figure 3-5.

The devi ce has f our sections of inte rnal data mem ory:

1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.

2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.

3. The special funct ion registers (80H to FFH) are directly addressable only.

4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register (AUXR)” in Section 3.6, “Special Function Registers”)

Since the upper 128 bytes occupy the same addresses as the SFRs , the RAM mus t be acce ssed i ndir ec tly. The RAM and SFRs space are physically separate even though they have the same addresses.

When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct , then an SFR is accessed. See the examples below.

Indirect Access:

MOV @R0, #data ; R0 contains 90H

Register R0 points to 90H which is locate d in the upper address range. Data in “#data” is writ ten to RAM l ocation 90H rather than port 1.

Direct Access:

MOV 90H, #data ; write data to P1

Data in “#data” is wr itten to por t 1. Instructions that write directly to the address write to the SFRs.

To acce ss the expanded RAM, t he EXTRAM bit mus t be cleared and MOVX instruc tions must be used. The extra 768 bytes of memory is physically loc at ed on the chip an d logically occu pies the first 768 bytes of externa l memory (addresses 000H to 2FFH).

When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following e xample.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Expanded RAM Access (Indirect Addressing only):

MOVX @DPTR, A ; DPTR contains 0A0H

DPTR points to 0A0H and data in “A” is w r itt en to addr es s 0A0H of the expanded R AM ra the r th an external memory. Access to extern al memory higher than 2 FFH using the MOVX instruction will access extern al memor y (0300H t o FFFFH) and will perform in the same way as the standard 8051, with P0 an d P2 a s data /addr ess bus, and P3 .6 an d P3.7 as write and read timing signals.

When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0.

address bits. This provides external paging capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external addressing up the 64K. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and MOVX @DPTR generates the necessary read and writ e signals (P3.6 - WR # and P3.7 - RD#) for external memory use. Table 3-5 shows external data memory RD#, WR# operation with EXTRAM bit.

The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 128 bytes and upper 128 bytes). The st ack pointer may not be located in any part of the expanded RAM.

Other output port pins c an be u sed to outp ut high er order

TABLE 3-5: E

AUXR ADDR < 0300H ADDR >= 0300H ADDR = Any

EXTRAM = 0 RD# / WR# not asserted RD# / WR# asserted RD# / WR# not asserted EXTRAM = 1 RD# / WR# asserted RD# / WR# asserted RD# / WR# asserted

1. Acc ess limi ted to ERAM addres s within 0 to 0FFH; cannot access 100H to 02FFH.

XTERNAL DATA MEMORY RD#, W R# WITH EXTRAM BIT

MOVX @DPTR, A or MOVX A, @DPTR MOVX @Ri, A or MOVX A, @Ri

T3-5.0 1255

Page 16

Preliminary Specifications

2FFH

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

000H

Expanded

RAM

768 Bytes

(Indirect Addressing)

FFH

80H

7FH

00H

FFFFH

(Indirect Addressing) (Direct Addressing)

Upper 128 Bytes

Internal RAM

Lower 128 Bytes

Internal RAM

(Indirect & Direct

Addressing)

(Indirect Addressing) (Indirect Addressing)

External

Data

Memory

FFH

Special

Function

Registers

(SFRs)

80H

FFFFH

External

Data

Memory

0300H

2FFH

Expanded RAM

000H

EXTRAM = 0 EXTRAM = 1

0000H

1255 F05.0

FIGURE 3-5: INTERNAL AND EXTERNAL DATA MEMORY STRUCTURE

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

3.5 Dual Data Pointers

The device has two 16-bit data pointers. The DPT R Select (DPS) bit in AUXR1 determines which of the two dat a pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-6)

AUXR1 / bit0

DPS

DPTR1

DPS = 0 → DPTR0

DPTR0

DPS = 1 → DPTR1

DPH 83H

DPL 82H

External Data Memory

1255 F06.0

FIGURE 3-6: D

UAL DATA POINTER ORGANIZATION

3.6 Special Function Registers

Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR memory map shown in Table 3-6. Individual descriptions of each SFR are provided and reset values indicated in Tables 3-7 to 3-11.

TABLE 3-6: F

F8H IP1 F0H B E8H IEA E0H ACC D8H CCON D0H PSW C8H T2CON C0H WDTC B8H IP B0H P3 A8H IE A0H P2 98H SCON 90H P1 88H TCON 80H P0

1. Bit addressable SFRs

LASHFLEX51 SFR MEMORY MAP

CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H FFH

CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L EFH

CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 DFH

T2MOD RCAP2L RCAP2H TL2 TH2 CFH

SADEN BFH

SFCF SFCM SFAL SFAH SFDT SFST IPH B7H

SADDR SPSR XICON AFH

AUXR1 P4 A7H

SBUF 9FH

TMOD TL0 TL1 TH0 TH1 AUXR 8FH

SP DPL DPH WDTD SPDR PCON 87H

8 BYTES

IP1H F7H

E7H

SPCR D7H

C7H

97H

T3-6.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 3-7: CPU RELATED SFRS

Direct

Symbol Description

ACC

Accumulator E0H ACC[7:0] 00H B Register F0H B[7:0] 00H

PSW1Program Status

Address

D0H CY AC F0 RS1 RS0 OV F1 P 00H

Word SP Stack P o in ter 81H SP[ 7:0] 07H DPL Data Pointer

82H DPL[7:0] 00H

Low DPH Data Pointer

83H DPH[7:0] 00H

High

IE IEA

Interrupt Enable A8H EA EC ET2 ES ET1 EX1 ET0 EX0 00H

Interrupt

E8H - - - - EBO - - - xxxx0xxxb

Enable A IP

Interrupt Priority

B8H - PPC PT2 PS PT1 PX1 PT0 PX0 x0000000b

Reg IPH Interrupt Priority

B7H - PPCH PT2H PSH PT1H PX1H PT0H PX0H x0000000b

Reg High

IP1

Interrupt Priority

F8H - - - - PBO - - - xxxx0xxxb

Reg A IP1H Interrupt Priority

F7H - - - - PBOH - - - xxxx0xxxb

Reg A High PCON Power Control 87H SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL 00010000b AUXR Auxiliary Reg 8EH - - - - - - EXTRAM AO xxxxxxx00b AUXR1 Auxiliary Reg 1 A2H - - - - GF2 0 - DPS xxxx00x0b XICON External

AEH 0 EX3 IE3 IT3 0 EX2 IE2 IT2 00H

Interrupt Control

1. Bit Addressable SFRs

Bit Address, Symbol, or Alternative Port Function

Reset ValueMSB LSB

T3-7.0 1255

TABLE 3-8: FLASH MEMORY PROGRAMMING SFRS

Direct

Symbol Description

SFCF SuperFlash

Address

B1H - IAPEN - - - - SWR BSEL x0xxxx00b

Configuration SFCM SuperFlash

B2H FIE FCM[6:0] 00H

Command SFAL SuperFlash

B3H SuperFlash Low Order Byte Address Register - A

Address Low SFAH SuperFlash

B4H SuperFlash High Order Byte Address Register - A

Address High SFDT SuperFlash

B5H SuperFlash Data Register 00H

Data SFST SuperFlash

B6H SB1_i SB2_i SB3_i - EDC_i FLASH_BUSY - - 000x00xxb

Status

Bit Address, Symbol, or Alternative Port Function

to A0 (SFAL) 00H

to A8 (SFAH) 00H

Reset ValueMSB LSB

T3-8.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 3-9: WATCHDOG TIMER SFRS

Direct

Symbol Description

WDTC

Watchdog Tim er

Address

C0H - - - WDOUT WDRE WDTS WDT SWDT xxx00x00b

Control

WDTD Watchdog Tim er

85H Watchdog Timer Data/Reload 00H

Data/Reload

1. Bit Addressable SFRs

TABLE 3-10: TIMER/COUNTERS SFRS

Direct

Symbol Description

TMOD Timer/Counter

Mode Control

TCON

Timer/Counter

Control TH0 Timer 0 MSB 8CH TH0[7:0] 00H TL0 Timer 0 LSB 8AH TL0[7:0] 00H TH1 Timer 1 MSB 8DH TH1[7:0] 00H TL1 Timer 1 LSB 8BH TL1[7:0] 00H T2CON1Timer / Counter 2

Control T2MOD# Timer2

Mode Control TH2 Timer 2 MSB CDH TH2[7:0] 00H TL2 Timer 2 LSB CCH TL2[7:0] 00H RCAP2H Timer 2

Capture MSB RCAP2L Timer 2

Capture LSB

1. Bit Addressable SFRs

Address

89H Timer 1 Timer 0 00H

GATE C/T# M1 M0 GATE C/T# M1 M0

88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# 00H

C9H---- - -T2OEDCENxxxxxx00b

CBH RCAP2H[7:0] 00H

CAH RCAP2L[7:0] 00H

Bit Address, Symbol, or Alternative Port Function

Reset ValueMSB LSB

T3-9.0 1255

Reset ValueMSB LSB

T3-10.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 3-11: INTERFACE SFRS

Direct

Symbol Description

Address

SBUF Serial Data Buffer 99H SBUF[7:0] Indeterminate

SCON

Serial Port Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H SADDR Slave Address A9H SADDR[7:0] 00H SADEN Slave Address

B9H SADEN[7:0] 00H

Mask SPCR SPI Control

D5H SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 04H

AAH SPIF WCOL 00H

P0 P1 P2 P3 P4

1. Bit Addressable SFRs

2. P4 is similar to P1 and P3 ports

Port 0 80H P0[7:0] FFH

Port 1 90H - - - - - - T2EX T2 FFH

Port 2 A0H P2[7:0] FFH

Port 3 B0H RD# WR# T1 T0 INT1# INT0# TXD RXD FFH

Port 4 A5H 1 1 1 1 P4.3 P4.2 P4.1 P4.0 FFH

Bit Address, Symbol, or Alternative Port Function

RESET

ValueMSB LSB

T3-11.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 3-12: PCA SFRS

Direct

Symbol Description

PCA Timer/Counter

CCON CMOD

PCA Timer/Counter Control Register

PCA Timer/Counter Mode Register

CCAP0H PCA Module 0 CCAP0L EAH CCAP0L[7:0] 00H

Compare/Capture

Address

F9H E9H

D8H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b D9H CIDL WDTE - - - CPS1 CPS0 ECF 00xxx000b

FAH CCAP0H[7:0] 00H

Bit Address, Symbol, or Alternative Port Function

CH[7:0]

CL[7:0]

Registers CCAP1H PCA Module 1 CCAP1L EBH CCAP1L[7:0] 00H

Compare/Capture

FBH CCAP1H[7:0] 00H

Registers CCAP2H PCA Module 2 CCAP2L ECH CCAP2L[7:0] 00H

Compare/Capture

Registers CCAP3H PCA Module 3 CCAP3L EDH CCAP3L[7:0] 00H

Compare/Capture

Registers CCAP4H PCA Module 4 CCAP4L EEH CCAP4L[7:0] 00H

Compare/Capture

Registers CCAPM0 PCA CCAPM1 DBH - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x0000000b CCAPM2 DCH - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x0000000b

Compare/Capture

Module Mode

Registers

FCH CCAP2H[7:0] 00H

FDH CCAP3H[7:0] 00H

FEH CCAP4H[7:0] 00H

DAH - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x0000000b

CCAPM3 DDH - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x0000000b CCAPM4 DEH - ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 x0000000b

1. Bit Addressable SFRs

RESET

ValueMSB LSB

00H 00H

T3-12.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

SuperFlash Configuration Register (SFCF)

Location76543210Reset Value

B1H - IAPEN ----SWRBSEL x0xxxx00b

Symbol Function

IAPEN Enable IAP operation

0: IAP commands are disabled 1: IAP commands are enabled

SWR Software Reset

See Section 10.2, “Software Reset”

BSEL Program memory block switching bit

See Figures 3-1 through 3-4 and Tables 3-3 and 3-4

SuperFlash Command Register (SFCM)

Location76543210Reset Value

B2H FIE FCM6 FCM5 FCM4 FCM3 FCM2 FCM1 FCM0 00H

Symbol Function

FIE Flash Interrupt Enable.

0: INT1# is not reassigned. 1: INT1# is re-assigned to signal IAP operation completion.

External INT1# interrupts are ignored.

FCM[6:0] Flash operation command

000_0001b Chip-Erase 000_1011b Sector-Erase 000_1101b Block- Erase 000_1100b Byte-Verify 000_1110b Byte-Program 000_1111b Prog-SB1 000_0011b Prog-SB2 000_0101b Prog-SB3 000_1001b Prog-SC0 000_1001b Prog-SC1 000_1000bEnable-Clock-Double All other combinations are not implemented, and reserved for future use.

1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.

SuperFlash Address Registers (SFAL)

Location76543210Reset Value

B3H SuperFlash Low Order Byte Address Register 00H

Symbol Function

SFAL Mailbox register for interfacing with flash memory block. (Low order address register).

SuperFlash Address Registers (SFAH)

Location76543210Reset Value

B4H SuperFlash High Order Byte Address Register 00H

Symbol Function

SFAH Mailbox register for interfacing with flash memory block. (High order address register).

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

SuperFlash Data Register (SFDT)

Location76543210Reset Value

B5H SuperFlash Data Register 00H

Symbol Function

SFDT Mailbox register for interfacing with flash memory block. (Data register).

SuperFlash Status Register (SFST) (Read Only Register)

Location76543 2 10Reset Value

B6H SB1_i SB2_i SB3_i - EDC_i

Symbol Function

SB1

_i Security Bit 1 status (inverse of SB1 bit)

SB2

_i Security Bit 2 status (inverse of SB2 bit)

SB3

_i Security Bit 3 status (inverse of SB3 bit)

Please refer to Table 9-1 for security lock options.

EDC

_i Double Clock Status

0: 12 clocks per machine cycle 1: 6 clocks per machine cycle

FLASH_BUSY Flash operation completion polling bit.

0: Device has fully completed the last IAP command. 1: Device is busy with flash operation.

FLASH_BUSY

- - xxxxx0xxb

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Interrupt Enable (IE)

Location76543210Reset Value

A8H EA EC ET2 ES ET1 EX1 ET0 EX0 00H

Symbol Function

EA Global Interrupt Enable.

0 = Disabl e

1 = Enable EC PCA Interrupt Enable. ET2 Timer 2 Interrupt Enable. ES S erial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable.

Interrupt Enable A (IEA)

Location76543210Reset Value

E8H----EBO---xxxx0xxxb

Symbol Function

EBO Brown-out Interrupt Enable.

1 = Enable the interrupt

0 = Disable the interrupt

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Interrupt Priority (IP)

Location76543210Reset Value

B8H - PPC PT2 PS PT1 PX1 PT0 PX0 x0000000b

Symbol Function

PPC PCA interrupt priority bit PT2 Timer 2 interrupt priority bit PS Serial Port inter r upt priority bit PT1 Timer 1 interrupt priority bit PX1 External interrupt 1 priority bit PT0 Timer 0 interrupt priority bit PX0 External interrupt 0 priority bit

Interrupt Priority High (IPH)

Location76543210Reset Value

B7H - PPCH PT2H PSH PT1H PX1H PT0H PX0H x0000000b

Symbol Function

PPCH PCA interrupt priority bit high PT2H Timer 2 interrupt priority bit high PSH Serial Port interrupt priority bit high PT1H Timer 1 interrupt priority bit high PX1H External interrupt 1 priority bit high PT0H Timer 0 interrupt priority bit high PX0H External interrupt 0 priority bit high

Interrupt Priority 1 (IP1)

Location76543210Reset Value

F8H 1 - - 1 PBO PX3 PX2 1 1xx10001b

Symbol Function

PBO Brown-out interrupt priority bit PX2 External Interrupt 2 priority bit PX3 External Interrupt 3 priority bit

Interrupt Priority 1 High (IP1H)

Location76543210Reset Value

F7H 1 - - 1 PBOH PX3H PX2H 1 1xx10001b

Symbol Function

PBOH Brown-out Interrupt priority bit high PX2H External Interrupt 2 priority bit high PX3H External Interrupt 3 priority bit high

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Auxiliary Register (AUXR)

Location76543210Reset Value

8EH------EXTRAMAOxxxxxx00b

Symbol Function

EXTRAM Internal/External RAM access

0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri / @DPTR. Beyond 300H, the MCU always accesses external data memory. For details, refer to Section 3.4, “Expanded Data RAM Addressing” . 1: External data memory access.

AO Disable/Enable ALE

0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 f 12 clock mode. 1: ALE is active only during a MOVX or MOVC instruction.

Auxiliary Register 1 (AUXR1)

Location76543210Reset Value

A2H----GF20-DPSxxxx00x0b

OSC

Symbol Function

GF2 General purpose use r -defi ned fla g. DPS DPTR registers select bit.

0: DPTR0 is selected. 1: DPTR1 is selected.

Watchdog Timer Control Register (WDTC)

Location76543210Reset Value

C0H - - - WDOUT WDRE WDTS WDT SWDT xxx00000b

Symbol Function

WDOUT Watchdog output enable.

0: Watchdog reset will not be exported on Reset pin. 1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.

WDRE Watchdog timer reset enable.

0: Disable watchdog timer reset. 1: Enable watchdog timer reset.

WDTS Watchdog timer reset flag.

0: External hardware reset or power-on reset clears the flag.

Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow.

1: Hardware sets the flag on watchdog overflow.

WDT Watchdog timer refresh.

0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh.

SWDT Start watchdog timer.

0: Stop WDT. 1: Start WDT.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Watchdog Timer Data/Reload Register (WDTD)

Location76543210Reset Value

85H Watchdog Timer Data/Reload 00H

Symbol Function

WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.

PCA Timer/Counter Control Register1 (CCON)

Location76543210Reset Value

D8H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b

1. Bit addressable

Symbol Function

CF PCA Counter Overflow Flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software, but can only cleared by software.

CR PCA Counter Run control bit

Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off.

- Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

PCA Timer/Counter Mode Register

Location76543210Reset Value

D9H CIDL WDTE - - - CPS1 CPS0 ECF 00xxx000b

1. Not bit addressable

Symbol Function

CIDL Counter Idle Control:

0: Programs the PCA Counter to continue functioning during idle mode 1: Programs the PCA Counter to be gated off during idle

WDTE Watchdog Timer Enable:

0: Disables Watchdog Timer function on PCA module 4 1: Enables Watchdog Timer function on PCA module 4

- Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

CPS1 PCA Count Pulse Select bit 1 CPS0 PCA Count Pulse Select bit 2

(CMOD)

Selected

CPS1 CPS0

PCA Input

00 0 01 1 10 2 11 3

1. f

= oscillator frequency

OSC

Internal clock, f Internal clock, f Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = f

ECF PCA Enable Counter Overflow interrupt:

0: Disables the CF bit in CCON 1: Enables CF bit in CCON to generate an interrupt

/6 in 6 clock mode (f

OSC

/2 in 6 clock mode (f

OSC

/4 in 6 clock mode, f

OSC

/12 in 12 clock mode)

OSC

/4 in 12 clock mode)

OSC

/8 in 12 clock mode)

OSC

Page 29

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

PCA Compare/Capture Module Mode Register

Location76543210Reset Value

DAH - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 00xxx000b

DBH - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 00xxx000b DCH - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 00xxx000b DDH - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 00xxx000b

DEH - ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 00xxx000b

1. Not bit addressable

Symbol Function

- Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

ECOMn Enable Comparator

0: Disables the comparator function 1: Enables the comparator function

CAPPn Capture Positive

0: Disables positive edge capture on CEX[4:0] 1: Enables positive edge capture on CEX[4:0]

CAPNn Capture Negative

0: Disables negative edge capture on CEX[4:0] 1: Enables negative edge capture on CEX[4:0]

MATn Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode

0: Disables software timer mode 1: A match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt.

TOGn Toggle

0: Disables toggle function 1: A match of the PCA counter with this module’s compare/capture register causes the the CEXn pin to toggle.

PWMn Pulse Width Modulation mode

0: Disables PWM mode 1: Enables CEXn pin to be used as a pulse width modulated output

ECCFn Enable CCF Interrupt

0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request. 1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request.

(CCAPMn)

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

SPI Control Register (SPCR)

Location76543210Reset Value

D5H SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 00H

Symbol Function

SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. SPE SPI enable bit.

0: Disables SPI. 1: Enables SPI and connects SS#, MOSI, MI SO , a nd SCK to pins P1.4, P1.5, P1.6, P1 .7.

DORD Data Transmission Order.

0: MSB first in data transmission. 1: LSB first in data transmission.

MSTR Master/Slave select.

0: Selects Slave mode. 1: Selects Master mode.

CPOL Clock Polarity

0: SCK is low when idle (Active High). 1: SCK is high when idle (Active Low).

CPHA Clock Phase control bit.

0: Shift triggered on the leading edge of the clock. 1: Shift triggered on the trailing edge of the clock.

SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device

configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, f

, is as follows:

OSC

SPR1 SPR0 SCK = f

0 0 1 1

0 1 0 1

divided by

OSC

4 16 64

128

SPI Statu s Register (S PSR)

Location76543210Reset Value

AAHSPIFWCOL------00xxxxxxb

Symbol Function

SPIF SPI Interrupt Flag.

Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is then generated. This bit is cleared by software.

WCOL Write Collision Flag.

Set if the SPI data register is written to during data transfer. This bit is cleared by software.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

SPI Data Register (SPDR)

Location76543210Reset Value

86H SPDR[7:0] 00H

Power Control Register (PCON)

Location76543210Reset Value

87H SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL 00010000b

Symbol Function

SMOD1 Double Ba ud r at e bi t. If S MOD 1 = 1, T imer 1 is u sed to gen er ate the ba ud r at e , an d the

serial port is used in modes 1, 2, and 3.

SMOD0 FE/SM0 Selection bit.

0: SCON[7] = SM0 1: SCON[7] = FE,

BOF Brown-out detection status bit, this bit will not be affected by any other reset. BOF

should be cleared by software. Power-on reset will also clear the BOF bit. 0: No brown-out. 1: Brown-out occurred

POF Pow er-on reset status bit, this bit will not be affected by any other reset. POF should be

cleared by software. 0: No Power-on reset.

1: Power-on reset occurred GF1 General-purpose flag bit. GF0 General-purpose flag bit. PD Power-down bit, this bit is cleared by hardware after exiting from power-down mode.

0: Power-down mode is not activated.

1: Activates Power-down mode. IDL Idle mode bit, this bit is cleared by hardware after exiting from idle mode.

0: Idle mode is not activated.

1: Activates idle mode.

Page 32

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Serial Port Control Register (SCON)

Location76543210Reset Value

98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00000000b

Symbol Function

FE Set SMOD0 = 1 to access FE bit.

0: No framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software.

SM0 SMOD0 = 0 to access SM0 bit.

Serial Port Mode Bit 0

SM1 Serial Port Mode Bit 1

SM0 SM1 Mode Description Baud Rate

0 0 0 Shift Register f

0 1 1 8-bit UART Variable 1029-bit UARTf

1 1 3 9-bit UART Variable

1. f

= oscillator frequency

OSC

or f

OSC

/6 (6 clock mode) or /12 (12 clock mode)

/32 or f /64 or f

/16 (6 clock mode)

OSC

/32 (12 clock m ode)

OSC

SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI

will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a given or broadcast address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be 0.

REN Enables serial reception.

0: to disable reception. 1: to enable reception.

TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as

desired.

RB8 In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the

stop bit that was received. In Mode 0, RB8 is not used.

TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at

the beginning of the stop bit in the other modes, in any serial transmission, Must be cleared by software.

RI Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or

halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.

Page 33

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Timer/Counter 2 Control Register (T2CON)

Location76543210Reset Value

C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# 00H

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2

will not be set when either RCLK or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative

transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for

its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clo ck flag. When set, ca us es t h e se ria l p ort to us e Tim e r 2 overflow pulse s for

its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock.

EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result

of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.

EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/stop control for Timer 2. A logic 1 starts th e timer. C/T2# Timer or counter select (Timer 2)

0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode)

1: External event counter (falling edge triggered) CP/RL2# Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if

EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or

negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1,

this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Timer/Counter 2 Mode Control (T2MOD)

Location76543210Reset Value

C9H------T2OEDCENxxxxxx00b

Symbol Function

- Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down

counter.

Page 34

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

External Interrupt Control (XICON)

Location76543210Reset Value

AEH 0 EX3 IE3 IT3 0 EX2 IE2 IT2 00H

Symbol Function

EX2 External Interrupt 2

Enable bit if set

IE2 Interrupt Enable

If IT2=1, IE2 is set/cleared automatically by hardware when interrupt is detected/ serviced.

IT2 External Interrupt 2 is falling-edge/low-level triggered when this bit is cleared by

software.

EX3 External Interrupt 3

Enable bit if set

IE3 Interrupt Enable

If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is detected/ serviced.

IT3 External Interrupt3 is falling-edge/low-level triggered when this bit is cleared by

software.

Page 35

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

4.0 FLASH MEMORY PROGRAMMING

Preliminary Specifications

The device internal fl ash memor y can be programmed or erased us ing the f o llowin g two m ethod s:

• External Host Programming mode

• In-Application Programming (IAP) mode

logic high to a logic low while RST input is being held continuously high. The device will stay in external host m ode as long as RST = 1 and PSEN# = 0.

A Read-ID operation is necessary to “ar m” the device in external host mode, and no other external host mode com-

4.1 External Host Programming Mode

External ho st programming mode allows the user to program the flash memory directly without using the CPU. External host mo de is entered by forcing PSEN# from a

mands can be enabled until a Read-ID is performed. In external host mode, the internal flash memory blocks are accessed through the re-assigned I/O port pins (see Figure 4-1 for details) b y an ex ternal host, such as a MCU programmer, a PCB tester or a PC-controlled dev elopment board.

TABLE 4-1: EXTERNAL HOST MODE COMMANDS FOR SST89E/V5XRD2

PROG#/

Operation RST PSEN#

Read-ID V Chip-Erase V Block-Erase V Sector-Erase V Byte-Program V Byte-Verify (Read) V Prog-SC0 V Prog-SC1 V Prog-SB1 V Prog-SB2 V Prog-SB3 V Enable-Clock-Double V

1. Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.

All other combinations of the above input pins are invalid and may result in unexpected behaviors.

Note: VIL = Input Low Voltage; VIH = Input High V oltage; V

AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1

IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1

ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0]

⇓

⇓ V ⇓ V ⇓ V

⇓ V ⇓ V ⇓ V ⇓ V ⇓ V ⇓ V

= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;

IH1

IL IL IL IH IH IL IL IL IH IH IL IL

DO AH AL

XXX

XAHAL

DI AH AL

DO AH AL

X5AHX

X AAH X

XXX

X 55H X

P3[5:4] P2[5:0] P1[7:0]

A[15:13]

T4-1.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 4-2: EXTERNAL HOST MODE COMMANDS FOR SST89E/V516RD2

PROG#/

Operation RST PSEN#

Read-ID V Chip-Erase V Block-Erase V Sector-Erase V Byte-Program V Byte-Verify (Read) V Select-Block0 V Select-Block1 V Prog-SC0 V Prog-SB1 V Prog-SB2 V Prog-SB3 V Enable-Clock-Double V

IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1 IH1

1. Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations

of the above input pins are invalid and may result in unexpected behaviors.

Note: VIL = Input Low Voltage; VIH = Input High V oltage; V

AH = Address high order byte; DI = Data Input; DO = Data Output

ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0]

⇓

⇓ V ⇓ V ⇓ V

⇓ V ⇓ V ⇓ V ⇓ V ⇓ V ⇓ V ⇓ V

= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;

IH1

IL IL IL IH IH IL IL IL IL IH IH IL IL

DO AH AL

DI AH AL

DO AH AL

P3[5:4] P2[5:0] P1[7:0]

XXX

XAHAL

X 55H X

XA5HX

X5AHX

XXX

X 55H X

T4-2.0 1255

VDDRST

Por t 0

6 7

Ready/Busy#

Address Bus

A15-A

Flash

Control Signals

Por t 3

EA# ALE /

Por t 2

Por t 1

PSEN#

PROG#

FIGURE 4-1: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE

Input/ Output Data Bus

Address Bus A

13-A8

Flash Control Signals

Address Bus A

7-A0

1255 F07.0

Page 37

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

4.1.1 Product Identification

The Read-ID command accesses the Signature Bytes that identify the device and the m anufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. The Read-ID command is selected by the command c ode of 0H on P3[7:6 ] and P2[7:6 ]. See Fi gure 14 -14 f o r timi ng wa v ef orms .

TABLE 4-3: P

Manufacturer’s ID 30H BFH Device ID

SST89E52RD2 31H 9CH SST89V52RD2 31H 9DH SST89E54RD2 31H 9EH SST89V54RD2 31H 9FH SST89E58RD2 31H 9BH SST89V58RD2 31H 9AH SST89E516RD2 31H 92H SST89V516RD2 31H 93H

RODUCT IDENTIFICATION

Address Data

T4-3.0 1255

4.1.2 Arming Command

An arming command sequence must take place before any external host mode sequence command is recognized by the device. This prevents accidental tr iggerin g of external host mode commands due to noise or programmer error. The arming command is as follows:

1. PSEN# goes low while RST is high. This will get the machine in external host mode, re-configuring the pins, and turning on the on-chip oscillator.

2. A Read-ID command is issued, and after 1 ms the external host mode commands can be issued.

After the above sequence, all other external host mode commands are enabled. Before the Read-ID command is received , al l ot her external host mode commands r eceived are ignored.

4.1.3 External Host Mode Commands

The external host mode commands are Read-ID, ChipErase, Block-Erase, Sector-Erase, Byte-Program, ByteVerify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, ProgSC1, Select-Block0, Select-Block1. See Table 4-1 for all signal logic assignments, Figure 4-1 for I/O pin assignments, an d Table 14-1 1 for the timin g parame ters . The critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The highto-low transition of the PROG# signal initiates the Erase or

Program commands, which are synchronized internally. The Read comman ds are asynchronous read s, independent of the PROG# signal level.

A detailed description of the external host mode commands follows.

The Select-Block0 com mand enables Block 0 to be programmed in external host mode. Once this command is executed, all subsequent extern al host Com mands will be directed at Bloc k 0. See Fig ure 14-15 for timing wav ef orms .

The Select-Block1 command enables Block 1 (8 KByte Block) to be programmed. Once this command is executed, all subsequent external host Commands that are directed to the address range below 2000H will be directed at Block 1. The Sele ct-Block1 command only a ffects the lowest 8 KByte of the program address space. For addresses greater than or equal to 2000H, Block 0 is accessed by default. Upon entering external host mode, Block 1 is selecte d by def ault .

The Chip-Erase, Block-Erase, and Sector-Erase commands are used for erasing all or part of the memory array . Erased data bytes in the memo ry array will be erased to FFH. Memor y locations that are to be programmed must be in the erased state prior to programming.

The Chip-Erase command erases all bytes in both memory blocks, regardless of any previous Select-Block0 or SelectBlock1 commands. Chip-Erase ignores the Security Lock status and will erase the Security Lock, returning the device to its Unlocked state. The Chip-Erase command will also erase the SC0 bit. Upon completion of the Chip-Erase command, Block 1 wi ll be the selec ted block. See Figur e 14-16 for timing waveforms.

The Block-Erase command erases all bytes in the selected memory blocks. This command will not be executed if the security lock is enabled. The selection of the memory block to be erased is d etermined by t he prior execution Selec tBlock0 or Select-B lock1 command. See Figure 14-18 for the timing waveforms.

The Sector-Erase c ommand erases all of the bytes in a sector. The sector size for the fla sh memory is 128 B ytes. This command wi ll not be executed if the Sec urity lock is enabled. See Figure 14-19 for timing waveforms.

The Byte-Program command is used for programming new data into the memory array. Programming will not take place if any security locks are enabled. See Fig ure 14-20 for timing waveforms.

The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program command. This comm an d wi l l b e d isabled if any security l ocks are enabled. See Figure 14-23 for timing waveforms.

Page 38

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock secti on an d al s o i n Table 9-1. Once programmed, these bits can only be erased through a ChipErase command. See Figure 14-21 for timing waveforms.

Prog-SC0 comma nd pr ograms SC0 b it, whi ch de ter min es the state of SFCF[0] out of reset. Once programmed, SC0 can only be re stored to a n erased state v ia a Chip- Erase command. See Figure 14-22 for timing waveforms.

Prog-SC1 comma nd pr ograms SC1 b it, whi ch de ter min es the state of SFCF[1] out of reset. Once programmed, SC1 can only be re stored to a n erased state v ia a Chip- Erase command. See Figure 14-22 for timing waveforms.

4.1.4 External Host Mode Clock Source

In external host mode, an internal oscillator will provide clocking for the device, and the os cillator is un affected by the clock dou b ler l ogic. Th e on- chip oscil lat or wi ll be turned on as the device enters external host mode; i.e. when PSEN# goes low while RST is high . During external host mode, the CPU core is held in reset. Upon exit from external host mode, the internal oscillator is turned off.

4.1.6 Instructions to Perform External Host Mode Commands

To program data into the memory array, ap ply power supply voltage (V

) to VDD and RST pins, and per-

form the following steps:

1. Maintain RST high and set PSEN# from logic high to low, in sequence according to the appropriate timing diagram.

2. Raise EA# High (V

3. Issue Read-ID command to enable the external host mode.

4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command.

5. Select the memory location using the address lines (P3[5:4], P2[5:0], P1[7:0]).

6. Present the data in on P0[7:0].

7. Pulse ALE/PROG#, observing minimum pulse width.

4.1.5 Flash Operation Status Detection Via External Host Handshake

The device provides two meth ods for an external host to detect the completi on of a flash me mory operatio n to opt imize the Program or Erase time. The e nd of a fla sh me mory operation cycle can be detected by:

1. monitoring the Ready/Busy# bit at P3[3];

2. monitoring the Data# Polling bit at P0[3] .

4.1.5.1 Ready/Busy# (P3[3])

The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming o peration is complet ed to indicate th e ready status.

4.1.5.2 Data# Polling (P0[3])

During a Program op eration, any attempts to read (Byt eVerify), wh ile the device is busy, will rece ive the complement of the data of the last byte loaded (logic low, i.e. “ 0” for an Erase) on P0[3] wi th the rest of the bits “ 0”. During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at the address specified.

8. Wait for low to high transition on Ready/Busy# (P3[3]).

9. Repeat steps 5 - 8 until programming is finished.

10. Verify the flash memory contents.

4.1.7 Additional Read Commands in External Host Mode

The procedure to issue additional read commands, shown in Table 4-4 below, is the same as the read ID command format, only the ad dres s i s c ha nge d. He re is a s ho rt list o f useful features:

• Read the status of the security bits (SB1_i, SB2_i, SB3_i).

• Read the configuration bits (SC0_i, SC1_i) status.

• Read the clock mode (EDC_i) status.

Note: Commands shown in Table 4-4 are not the

ARMING type.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 4-4: A

Address Data

60H X X X SC1_i SC0_i SB1_i SB2_i SB3_i 61H XXXXXXEDC_iX

X = Don’t care

DDITIONAL READ COMMANDS IN EXTERNAL HOST MODE

4.2 In-Application Programming Mode

The device offers either 16/24/40/72 KByte of in-application programmable flash memory. During in-application programming, the CPU of the microcontroller enters IAP mode. The two blocks of flash me mory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concu rre ntly. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SF AH, SFDT and SFCF) located in the special function register (SFR), control and monitor the device’s erase and program process.

Table 4-6 and Table 4-7 outline the c ommands and their associated mailb ox re gister set tings .

4.2.1 In-Application Programming Mode Cloc k Source

During IAP mode, both the CPU core and the flash controller unit are dri ven off th e external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The inte rnal oscill ator is only tur ned on when required, and is turned off as soon as the flash operation is compl eted.

T4-4.0 1255

4.2.2 Memory Bank Selection for In-Application

Programming Mode

With the addressi ng range limit ed to 16 bit, on ly 64 KByt e of program address sp ace is “visible” at any o ne time. As shown in Table 4-5, the ba nk selec tio n (th e conf igu r ati on of EA# and SFCF[1:0]), allows Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The same c oncept is employed to allow both Block 0 and Block 1 flash to be acces sible to IAP operations. C ode fr om a b lo c k th at is not vi sib l e ma y not be u sed as a source to program another address. However , a b loc k that is not “visible” may be programm ed by code from th e other block through mailbox registers.

The device allows IAP code in one block of memory to program the other block of memory, but may not program any location in the sam e block. If an IAP operation origi nates physically from Block 0, the target of this operation is implicitly defined to be in Blo ck 1. If the IAP op eratio n or igi nates physically from Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates from external program space, then, the target will depend on the address and the state of bank selection.

4.2.3 IAP Enable Bit

The IAP enable bit, SFCF[6], enables in-application programming mode. Until this bit is set, all flash programming IAP commands will be ignored.

TABLE 4-5: IAP ADDRESS RESOLU TIO N FOR SST89E /V516RD2

EA# SFCF[1:0] Address of IAP Inst. Target Address Block Being Programmed

1 00 >= 2000H (Block 0) >= 2000H (Block 0) None 1 00 >= 2000H (Block 0) < 2000H (Block 1) Block 1 1 00 < 2000H (Block 1) Any (Block 0) Block 0 1 01, 10, 11 Any (Block 0) >= 2000H (Block 0) None 1 01, 10, 11 Any (Block 0) < 2000H (Block 1) Block 1 0 00 From external >= 2000H (Block 0) Block 0 0 00 From external < 2000H (Block 1) Block 1 0 01, 10, 11 From external Any (Block 0) Block 0

1. No operation is performed because code from one block may not program the same originating block

T4-5.0 1255

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

4.2.4 In-Application Programming Mode Commands

All of the following commands can only be initiated in the IAP mode. In all situations, wri ting the control byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the security locks are enabled on the selected me mory bloc k.

The Program command is for programming new data int o the memory array. The portion of the memory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should first be erased with an appropriate Erase command. Warning: Do not attempt to

write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data.

4.2.4.1 Chip-Erase

The Chip-Erase command erases all bytes in both memory blocks. This command is only allowed when EA#=0 (external memor y execution). Additi onally this command i s not permitted when the device is in level 4 locking. In all oth er instances, this co mmand ignor es the Secu rity Lo ck status and will erase the security lock bits and re-map bits.

IAP Enable

ORL SFCF, #40H

FlashFlex51 MCU

IAP Enable

ORL SFCF, #40H

Erase Block 0

MOV SFAH, #00H

Polling scheme

MOV SFCM, #0DH

SFST[2] indicates

operation completion

Set-Up

MOV SFDT, #55H

4.2.4.3 Sector-Erase

The Sector-Erase c ommand erases all of the bytes in a sector. The sector size for the flash memor y blocks is 128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SF AL.

Erase Block 1

MOV SFAH, #F0H

Interrupt scheme

MOV SFCM, #8DH

INT1 interrupt

indicates completion

1255 F09.0

Set-Up

MOV SFDT, #55H

Polling scheme

MOV SFCM, #01H

SFST[2] indicates

operation completion

Interrupt scheme

MOV SFCM, #81H

INT1 interrupt

indicates completion

1255 F08.0

4.2.4.2 Block-Erase

The Block-Erase command erase s all bytes in one of the two memory blocks (Blo ck 0 or Block 1). The selecti on of the memory block to be erased is determined by the (SFAH[7]) of the SuperFlash Address Register. For SST89x516RD2, re fer to Ta ble 4-5. For SST89 x5xRD2, i f SFAH[7] = 0b, the primary flash memory Block 0 is selected. If SFAH[7:4] = EH, t he second ar y flash memor y Block 1 is selected. The Block-Erase command sequence for SST89x5xRD2 is as follows:

Program sector address

MOV SFAH, #sector_addressH

MOV SFAL, #sector_addressL

Polling scheme

MOV SFCM, #0BH

SFST[2] indicates

operation completion

IAP Enable

ORL SFCF, #40H

Interrupt scheme

MOV SFCM, #8BH

INT1 interrupt

indicates completion

1255 F10.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

4.2.4.4 Byte-Program

The Byte-Program comm and programs data into a s ingle byte. The address is deter m ined by the contents of SFAH and SFAL. The data byte is in SFDT .

IAP Enable

ORL SFCF, #40H

MOV SFAH, #byte_addressH

IAP Enable

ORL SFCF, #40H

Program byte address

MOV SFAL, #byte_addressL

Preliminary Specifications

Program byte address

MOV SFAH, #byte_addressH

MOV SFAL, #byte_addressL

Move data to SFDT

MOV SFDT, #data

Polling scheme

MOV SFCM, #0EH

SFST[2] indicates

operation completion

Interrupt scheme

MOV SFCM, #8EH

INT1 interrupt

indicates completion

1255 F11.0

4.2.4.5 Byte-Verify

The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command. Byte-Verify command returns the data byte in SFDT if the command is successful. The user is required to check that the previous flash operation has fully completed before issuing a Byte- Verify. Byte-Verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated.

MOV SFCM, #0CH

SFDT register

contains data

1255 F12.0

4.2.4.6 Prog-SB3, Prog-SB2, Prog-SB1

Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the security bits (see Table 9-1). Completion of any of these commands, the security options will be updated immediately.

Security bits previously in un-programmed state can be programmed by these commands. Prog-SB3, Prog-SB2 and Prog-SB1 comm an ds sho ul d on ly re si de in Bl ock 1 or external code memory .

IAP Enable

ORL SFCF, #40H

Set-Up

MOV SFDT, #0AAH

Program SB1

MOV SFCM, #0FH

MOV SFCM, #8FH

Program SB2

MOV SFCM, #03H

OR OR

MOV SFCM, #83H

Program SB3

MOV SFCM, #05H

MOV SFCM, #85H

Polling SFST[2]

indicates completion

INT1# Interrupt

indicates completion

1255 F13.0

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

4.2.4.7 Prog-SC0, Prog-SC1

Prog-SC0 comman d is used to p rogram the SC0 bi t. This command only chang es the SC0 bit a nd has no effect on BSEL bit until after a reset cycle.

SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 command should resi de only i n Bloc k 1 or e xte rnal code memory.

Prog-SC1 comman d is used to p rogram the SC1 bi t. This command only chang es the SC1 bit a nd has no effect on SFCF[1] bit un til a fter a r eset cycle .

SC1 bit previously in un-programmed state can be programmed by this command. The Prog-SC1 command should resi de only i n Bloc k 1 or e xte rnal code memory.

ORL SFCF, #40H

Set-up Enable-Clock-Double

MOV SFAH, #55H

MOV SFDT, #0AAH

Program Enable-Clock-Double

Polling scheme

MOV SFCM, #08H

Polling SFST[2]

indicates completion

FlashFlex51 MCU

IAP Enable

Program Enable-Clock-Double

Interrupt scheme

MOV SFCM, #88H

INT1# Interrupt

indicates completion

1255 F15.0

IAP Enable

ORL SFCF, #40H

Set-up Program SC0

MOV SFAH, #5AH

MOV SFDT, #0AAH

Program SC0 or SC1 -

Polling scheme

MOV SFCM, #09H

Polling SFST[2]

indicates completion

Set-up Program SC1

MOV SFAH, #0AAH

MOV SFDT, #0AAH

Program SC0 or SC1 -

Interrupt scheme

MOV SFCM, #89H

INT1# Interrupt

indicates completion

1255 F14.0

4.2.4.8 Enable-Clock-Double

Enable-Clock-Double command is used to make the MCU run at 6 clocks per machine cycle. The standard (default) is 12 clocks per machine cycle (i.e. clock double command disabled).

There are no IAP counterparts for the external host commands Select-Block0 and Select-Block1.

4.2.5 Polling

A command that uses the polling method to detect flash operation completi on s hould poll on the FLA SH_BUS Y bit (SFST[2]). When FLASH_BUSY de-asserts (logic 0), the device is ready for the next operation.

MOVC instruction may als o be used for verifi cation of th e Programming and Erase operation of the flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy.

4.2.6 Interrupt Termination

If interrupt ter mination is selected, (SFCM[7] is set), the n an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal in terrupt s ource. The INT 1# pin can now be us ed as a general purp ose po rt pin and it ca nnot be the so urce of External Interrupt 1 during in-application programming.

In order to use an interrupt to signal flash operation termination. EX1 and E A bi ts of IE r egi ster mus t be s et. The IT1 bit of TCON register must also be set for edge trigger detection.

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 4-6: IAP COMMANDS1 FOR SST89E/V516RD2

Operation SFCM [6:0]

Chip-Erase Block-Erase Sector-Erase Byte-Program Byte-Verify (Read) Prog-SB1 Prog-SB2 Prog-SB3 Prog-SC0 Enable-Clock-Double

1. SF CF [6]=1 enables IAP commands; SFCF[6] =0 disables IAP commands.

2. Interr upt /Polling enable for flash operation completion

3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.

4. X can be V

5. Refer to Table 4-5 f or address resolution

6. AH = Address high order byte

7. AL = Address low order byte

8. DI = Data Input, DO = Data Output, all other values are in hex.

9. Instr uc tion must be located in Block 1 or external code memory.

Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.

5 9 9 9

SFCM[7] =1: Interrupt enable for flash operation completion

0: polling enable for flash operation completion

or VIH, but no other value.

01H 55H X 0DH 55H AH X 0BH X AH 0EH DI 0CH DO 0FH AAH X X 03H AAH X X 05H AAH X X 09H AAH 5AH X 08H AAH 55H X

SFDT [7:0] SFAH [7:0] SFAL [7:0]

AH AL AH AL

T4-6.0 1255

TABLE 4-7: IAP COMMANDS1 FOR SST89E/V5XRD2

Operation SFCM [6:0]

Chip-Erase

01H 55H X Block-Erase 0DH 55H AH Sector-Erase 0BH X AH AL Byte-Program 0EH DI Byte-Verify (Read) Prog-SB1 Prog-SB2 Prog-SB3 Prog-SC0 Prog-SC1

9 9 9

9 9

Enable-Clock-Double

1. SF CF [6]=1 enables IAP commands; SFCF[6] =0 disables IAP commands.

2. Interr upt /Polling enable for flash operation completion SFCM[7] =1: Interrupt enable for flash operation completion

3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.

4. X can be VIL or VIH, but no other value.

5. AH = Address high order byte

6. AL = Address low order byte

7. DI = Data Input, DO = Data Output, all other values are in hex.

8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0

9. Instr uc tion must be located in Block 1 or external code memory.

Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.

0: polling enable for flash operation completion

0CH DO 0FH AAH X X 03H AAH X X 05H AAH X X 09H AAH 5AH X 09H AAH AAH X 08H AAH 55H X

SFDT [7:0] SFAH [7:0] SFAL [7:0]

AH AL AH AL

X X

T4-7.0 1255

Page 44

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

5.0 TIMERS/COUNTERS

5.1 Timers

The device has three 16 -bit regist ers that c an be used as either timers or event counters. The thr ee timers/counters are denoted Timer 0 (T0), Timer 1 (T1) , and Time r 2 (T2). Each is design ated a pair of 8-bit regi sters in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2.

5.2 Timer Set-up

Refer to Table 3-10 for TMOD, TCON, and T2CON registers regarding time rs T0, T1, and T2. The following tables provide TMOD values to be used to se t up T imers T0, T1, and T2.

Except for the baud rate generator mode, the values given for T2 CON do not incl ude t he s ett ing o f the TR2 b it. The refore, bit TR2 must be set separately to turn the timer on.

TABLE 5-1: T

Mode Function

Used as Timer

Used as Counter

1. The Timer is tur ned ON/OFF by setting/clearing bit TR0 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0# (P3.2) when TR0 = 1 (hardware control).

IMER/COUNTER 0

TMOD

Internal

Control

External Control

0 13-bit Timer 00H 08H 1 16-bit Timer 01H 09H 2 8-bit Auto-Reload 02H 0AH 3 Two 8-bit Timers 03H 0 BH 0 13-bit Timer 04H 0CH 1 16-bit Timer 05H 0DH 2 8-bit Auto-Reload 06H 0EH 3 Two 8-bit Timers 07H 0FH

T5-1.0 1255

TABLE 5-2: TIMER/COUNTER 1

TMOD

Mode Function

Internal

Control

External Control

0 13-bit Timer 00H 80H

Used as Timer

1 16-bit Timer 10H 90H 2 8-bit Auto-Reload 20H A0H 3 Does not run 30H B0H 0 13-bit Timer 40H C0H

Used as Counter

1 16-bit Timer 50H D0H 2 8-bit Auto-Reload 60H E0H 3 Not available - -

1. The Timer is tur ned ON/OFF by setting/clearing bit TR1 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1# (P3.3) when TR1 = 1 (hardware control).

T5-2.0 1255

TABLE 5-3: TIMER/COUNTER 2

T2CON

External Control

T5-3.0 1255

Internal

Mode

Control

16-bit Auto-Reload 00H 08H

Used as Timer

16-bit Capture 01H 09H

Baud rate generator

34H 36H

receive and transmit

same baud rate

Receive only 24H 26H

Transmit only 14H 16H

Used as Counter

1. Capture/Reload occurs only on timer/counter overflow.

2. Capture/Reload occurs on timer/counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode.

16-bit Auto-Reload 02H 0AH

16-bit Capture 03H 0BH

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

5.3 Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode).

To configure Timer/Counter 2 as a clock generator, bit C/#T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the relo ad value of Timer 2 captu re registers (RCAP2H, RCAP2L) as shown in this equation:

Oscillator Frequency

n x (65536 - RCAP2H, RCAP2L) n = 2 (in 6 clock mode)

4 (in 12 clock mode)

Where (RCAP2H, RCAP2L) = the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

In the Clock-Out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequenc y will not be the same.

6.0 SERIAL I/O

6.1 Full-Duplex, Enhanced UART

The device serial I/O port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is perfor ming other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive regi ster.

The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is ini tiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set.

6.1.1 Framing Error Detection

Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two CPUs.

Framing Error Detection is selected by goin g to the P CO N register and chang ing SMOD0 = 1 (see Figure 6 -1). If a stop bit is missing, th e Framing Error bit (FE ) will be set. Software may examine the FE bit after each reception to check for data errors. After the F E bit has b een set, it can only be cleared by software. V alid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the last data bit (see Figure 6-2 and Figure 6-3).

SM0/FE SM1

SMOD0SMOD1 POF GF1 GF0 PD IDL

FIGURE 6-1: F

RAMING ERROR BLOCK DIAGRAM

SM2

BOF

REN TB8 RB8 TI RI

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

To UART framing error control

SCON

(98H)

PCON

(87H)

1255 F16.0

Page 46

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

RXD

Start

SMOD0=X

SMOD0=1

D0 D1 D2 D3 D4 D5 D6 D7

bit

FIGURE 6-2: UART TIMINGS IN MODE 1

Data byte

Stop

bit

1255 F17.0

RXD

Start

SMOD0=0

SMOD0=1

FIGURE 6-3: UART T

D0 D1 D2 D3 D4 D5 D6 D7 D8

Data byte

bit

IMINGS IN MODES 2 AND 3

Ninth

bit

Stop

bit

1255 F18.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

6.1.2 Automatic Address Recognition

Automatic Address Recog nition helps to redu ce the MCU time and power required to talk to multiple se rial devices. Each device is hooked t ogether sharing the same serial link with its own addr ess. In this confi guration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses.

This same feature helps to save power because it can be used in conjunction with id le mode to redu ce the syst em’s overall power consumption. Since there may be multiple slaves hooked up serial to one master, only one slave would have to be interrupted from idl e m ode to res po nd to the master’s transmission. Automati c A dd re ss Re c ogn ition (AAR) allows the other slaves to remain in idle mode while only one is interr upted. By li miting the numb er of interru ptions, the total current draw on the system is reduced.

There are two ways to communicate with slaves: a group of them at once , or all of the m at once. To communicate with a group of slaves, the master sends out an addr ess called the given address. To communi c ate with all the slaves, the master sends out an address called the “broadcast” address.

AAR can be configur ed as mo de 2 or 3 (9-b it mode s) an d setting the SM2 bit in SCON. Each slave has its own SM2 bit set waiting for an address byte (9th bit = 1). The Receive Interrupt (RI ) flag will only be s et when the received byte matches either the given address or the broadcast address. Next, the slave then clears its SM2 bit to enable reception of the data bytes (9th bit = 0) from the master. When the 9th bit = 1 , the master is sending a n address. When the 9th bit = 0, the master is sending actual data.

6.1.2.1 Using the Given Address to Select Slaves

Any bits masked off by a 0 from SADEN become a “don’t care” bit for the given address. Any bit masked off by a 1, becomes ANDED with SADDR. The “do n’t cares” provide flexibility in the user-defined addresses to address more slav es when using t he giv en a ddres s.

Shown in the example above, Slave 1 has been given an address of 1111 0001 (SADDR). The SADEN byte has been used t o mask o ff bits to a gi ve n address to allo w mor e combinations of selecting Slave 1 and Slave 2. In this case for the given addresses, the last b it (LSB) of Slave 1 is a “don’t care” and the l ast bit of Slave 2 is a 1. To communicate with Slave 1 and Slave 2, the master would ne ed to send an address with the last bit equal to 1 (e.g. 1111

0001) since Slave 1’s last bit is a don’t care and S lave 2’s last bit has to be a 1. To communicate with Slave 1 alone, the master wo uld send an a ddre ss wi th t he l ast bit equa l to 0 (e.g. 1111 0000), since Slave 2’s last bit is a 1. See the table belo w f o r other p ossib le com binat ions .

Slave 1 Given Address Possible Addresses

Slave 2

SADDR = 1111 0011

SADEN = 1111 1001

GIVEN = 1111 0XX1

Select Slave 1 Only

1111 0X0X 1111 0000

Preliminary Specifications

1111 0100

If mode 1 is used, the stop bit takes the place of the 9th bit. Bit RI is set only when the received command frame address matches the device’s address and is termin ated by a valid stop bit. Note that mode 0 ca nnot be use d. Se tting SM2 bit in the SCON register in mode 0 will have no

Slave 2 Given Address Possible Address es

Select Slave 2 Only

1111 0XX1 1111 0111

1111 0011

effect. Each slave’s individual address is specified by SFR

SADDR. SFR SADEN is a ma sk byte that defines “don’t

Slaves 1 & 2 Possible Addresses

care” bits to form t he given address when combined with SADDR. See the example below:

Slave 1

SADDR = 1111 0001 SADEN = 1111 1010

GIVEN = 1111 0X0X

If the user added a third slave such as the example below:

Select Slaves 1 & 2

1111 0001 1111 0101

Slave 3

SADDR = 1111 1001 SADEN = 1111 0101 GIVEN = 1111 X0X1

Page 48

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Select Slave 3 Only

Slave 2 Given Address Possible Addresses

1111 X0X1 1111 1011

1111 1001

The user could use the possible addresses above to select slav e 3 only. Another combinatio n could be to select sl av e 2 and 3 only as shown below.

Select Slaves 2 & 3 Only

Slaves 2 & 3 Possible Addresses

1111 0011

More than one slave may have the same SADDR address as well, and a given address could be used to modify th e address so that it is unique.

6.1.2.2 Using the Broadcast Address to Select Slaves

Using the broadcast address, the master can communicate with all the slaves at once. It is formed by performing a logical OR of SADDR and SADEN with ‘0’s in the result treated as “don’t cares”.

Slave 1

1111 0001 = SADDR

+1111 1010 = SADEN

1111 1X11 = Broadcast

“Don’t cares” all ow for a wider range in def in ing the broadcast address, but in most cases, the broadcast address will be FFH.

On reset, SADDR and SADEN are “0”. This produces an given address of all “don’t cares” as well as a b roadcast address of all “don ’t cares.” This effectively disables Automatic Addressing m ode and allows the microcon troller to function as a standa rd 8051, wh ich does no t make use of this feature.

6.2 Serial Peripheral Interface

6.2.1 SPI Features

• Master or slave operation

• 10 MHz bit frequency (max)

• LSB first or MSB first data transfer

• Four programmable bit rates

• End of transmission (SPIF)

• Write collision flag protection (WCOL)

• Wake up from idle mode (slave mode only)

6.2.2 SPI Description

The serial periphe ral int erf ace (SPI) al lows hi gh-speed synchronous data transfer between the SST89E/V554A and peripheral devices or between several SST89E/V554A devices .

Figure 6-4 shows the correspondence between master and slav e SPI de vices . The S CK pin is the cl ock output and input for the master and slave modes, respectively . The SPI clock generator will start following a write to the master devices SPI data register. The written d ata is then shi fted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator i s stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI Interr upt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both set.

An external master dr ives the Slave Select inpu t pin, S S#/ P1[4], low to select the SPI module as a slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5] port can also be used as an input port pin.

CPHA and CPOL control the phase and polarity of the SPI clock. Figures 6-5 and 6-6 show the four possible combinations of these two bits.

MSB Master LSB

8-bit Shift Register

SPI

Clock Generator

FIGURE 6-4: SPI M

ASTER-SLAVE INTERCONNECTION

MISO MISO

MOSI MOSI

SCK SCK

SS# SS#

MSB Slave LSB

8-bit Shift Register

1255 F19.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

6.2.3 SPI Transfer Formats

Preliminary Specifications

SCK Cycle #

(for reference)

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(from Master)

MISO

(from Slave)

SS# (to Slave)

12345678

MSB

MSB 654321LSB

FIGURE 6-5: SPI TRANSFER FORMAT WITH CPHA = 0

SCK Cycle #

(for reference)

SCK (CPOL=0)

12345678

4 3 2 1 LSB

1255 F20.0

SCK (CPOL=1)

(from Master)

SS# (to Slave)

FIGURE 6-6: SPI T

MOSI

MISO

(from Slave)

RANSFER FORMAT WITH CPHA = 1

MSB

MSB6543 21 LSB

4 3 2 1 LSB

1255 F21.0

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

7.0 WATCHDOG TIMER

FlashFlex51 MCU

The devic e off ers a pro gram mable Wa tchdog Ti mer (WDT ) for fail safe protection against software dea dlock an d aut omatic recovery.

To protec t the syste m against s oftware dead lock, the user software must refresh the W DT w ithin a us er-d efine d tim e period. If the software fails to do this perio dical refresh , an internal hardware reset will be initiated if enabled (WDRE=

1). The software can be designed such that the WDT times out if the program does not work properly .

The WDT in the device uses the syst em clock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a watchdog timer. The WDT registe r will i ncrement every 344,064 crystal clocks. The up pe r 8 -bits of the time base register (WDTD) are used as the reload register of the WDT.

344064

clks

WDT Upper Byte

Ext. RST

CLK (XTAL1)

Counter

The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing “1” to it.

Figure 7-1 provides a block diagram of the WDT . Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle.

The time-out period of the WDT is calculated as follows:

Period = (255 - WDTD) * 344064 * 1/f

CLK (XTAL1)

where WDTD is the value loaded into the WDTD register and f

is the oscillator frequency.

OSC

WDT Reset

Internal Reset

FIGURE 7-1: B

WDTC

WDTD

LOCK DIAGRAM OF PROGRAMMA BLE WATCHDOG TIMER

1255 F22.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

8.0 PROGRAMMABLE COUNTER ARRAY

Preliminary Specifications

The Programmable Counter Array (PCA) prese nt on the SST89E/V5xRD2 is a special 16-bit timer that has five 16bit capture/ compa re mod ules . Each of the mo dule s can be programmed to operate in one of four modes: rising and/or falling edge capture, sof tware timer, high-speed output, or pulse width modulator. The 5th module can be programmed as a Watchdog Timer in addition to the other four modes. Each module has a pin associated with it in port 1. Module 0 is connect ed to P1. 3 (CEX0) , modu le 1 to P 1[4] (CEX1), module 2 to P1[5] (CEX2), module 3 to P1[6] (CEX3), and module 4 to P1[7] (CEX4). PCA configuration is shown in Figure 8-1.

8.1 PCA Overview

PCA provides more timing capabilities with less CPU intervention than the standard timer/counter. Its advantages include reduced software overhead and improv ed accuracy.

The PCA consists of a dedicated timer/counter which serves as the ti me base for an array of five compar e/capture modules. Figure 8-1 shows a block diagram of the

PCA. External events associated with modules are shared with corresponding Port 1 pins. Modules not using the port pins can still be used for standard I/O.

Each of the five modules can be programmed in any of the following modes:

• Rising and/or falling edge capture

• Software timer

• High speed output

• Watchdog Timer (Module 4 only )

• Pulse Width Modulator (PWM)

8.2 PCA Timer/Counter

The PCA timer is a free-running 16-bit timer consisting of registers CH and CL ( the high and low bytes of the count values). The PCA time r is common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency , Timer 0 overflow , or the input on the ECI pin (P1.2). The timer/counter source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see “PCA Timer/C ounter Mode Register (CMOD)” on page 28):

TABLE 8-1: PCA TIMER/COUNTER SOURCE

CPS1 CPS0 12 Clock Mode 6 Clock Mode

00 f 01 f 1 0 Timer 0 overflow Timer 0 overflow 1 1 External clock at ECI pin

(maximum rate = f

16 Bits

PCA Timer/Counter

/12 f

OSC

/4 f

OSC

External clock at ECI pin

OSC

/8)

16 Bits Each

Module 0

Module 1

Module 2

Module 3

Module 4

(maximum rate = f

OSC OSC

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

1255 F23.0

/6 /2

OSC

/4)

T8-1.0 1255

FIGURE 8-1: PCA T

IMER/COUNTER AND COMPARE/CAPTURE MODULES

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Preliminary Specifications The table below summarizes various clock inputs at two common frequencies.

FlashFlex51 MCU

TABLE 8-2: PCA T

PCA Timer/Counter Mode

Mode 0: f Mode 1: 330 nsec 250 nsec Mode 2: Timer 0 Overflows Timer 0 programmed in:

8-bit mode 256 µsec 192 µsec 16-bit mode 65 msec 49 µsec 8-bit auto-reload 1 to 255 µsec 0.75 to 191 µsec

Mode 3: External Input MAX 0.66 µsec 0.50 µsec

1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.

/12 1 µsec 0.75 µsec

OSC

IMER/COUNTER INPUTS

Clock Increments

12 MHz 16 MHz

T8-2.0 1255

The four possible CMOD timer modes w ith and without the overflow interrupt enabled are shown below. This list assumes that PCA will be left running during idle mode.

TABLE 8-3: CMOD VALUES

CMOD Value

PCA Count Pulse Selected

Internal clock, f Internal clock, f Timer 0 overflow 04H 05H External clock at P1.2 06H 07H

/12 00H 01H

OSC

/4 02H 03H

OSC

Without Interrupt Enabled With Interrupt Enabled

T8-3.0 1255

The CCON register is associated with all PCA timer functions. It contains run cont rol bits and flags for the PCA timer (CF) and all modules. To run the PCA the CR bit (CCON.6) must be set by software. Clearing the bit, will turn off PCA. When the PC A counter overflows, the CF (CCON.7) will be set, and a n interru pt will be generate d if the ECF bit in the CMO D register is set. The CF bit can only be c leared by software. Eac h module h as its own timer interrupt or capture interrupt flag (CCF0 for module 0, CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can only be cleared by software. (See “PCA Timer/Counter Control Register (CCON)” on page 27.)

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

8.3 Compare/Capture Modules

Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. Refer to “PCA Compare/Capture Module Mode Register (CCAPMn)” on page 29 for details. The registers each contain 7 bits which are used to control the mode each module will operate in. The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on module) will enable the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set, causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. When there is a match between the PCA counter and the mod-

Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine whether the cap ture input will be ac tive on a pos itive edge or negative edge. The CAPN bit enables the negative edge that a capture in put will be active on, and th e CAPP bit enables the positive edge. When both bits are set , bot h edges will be ena bled and a capture will occur for either transition. The last bit in th e register ECOM (CCAPMn. 6) when set, enables the comparator function. Table 8-5 shows the CCAPMn settings for the various PCA functions.

There are two additio nal register associated with each of the PCA modu les: CCAP nH a nd CCAPn L. Th e y a re regi sters that hol d the 16-bi t coun t v al ue wh en a ca ptur e occu rs or a compare occurs. When a module is used in PWM mode, these registers are used to control the duty cycle of

the output. See Figure 8-1. ule’s capture/compare register, the MATn (CCAPMn.3) and the CCFn bit in the CCON register to be set.

TABLE 8-4: PCA H

Symbol Description

CCAP0H PCA Module 0 CCAP0L EAH CCAP0L[7:0] 00H

CCAP1H PCA Module 1 CCAP1L EBH CCAP1L[7:0] 00H

CCAP2H PCA Module 2 CCAP2L ECH CCAP2L[7:0] 00H

CCAP3H PCA Module 3 CCAP3L EDH CCAP3L[7:0] 00H

CCAP4H PCA Module 4 CCAP4L EEH CCAP4L[7:0] 00H

Compare/Capture Registers

IGH AND LOW REG IST ER COMPARE/CAPTURE MODULES

Direct

Address

FAH CCAP0H[7:0] 00H

FBH CCAP1H[7:0] 00H

FCH CCAP2H[7:0] 00H

FDH CCAP3H[7:0] 00H

FEH CCAP4H[7:0] 00H

Bit Address, Symbol, or Alternative Port Function

RESET

ValueMSB LSB

T8-4.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 8-5: PCA MODULE MODES

Without Interrupt enabled

ECOMy2CAPPy2CAPNy2MATy2TOGy2PWMy2ECCFy2Module Code

- 0 0 0 0 0 0 0 No Operation

- 0 1 0 0 0 0 0 16-bit capture on positive-edge trigger at CEX[4:0]

- 0 0 1 0 0 0 0 16-bit capture on negative-edge trigger a t CEX[4:0]

- 0 1 1 0 0 0 0 16-bit capture on positive/negative-edge trigger at CEX[4:0]

- 1 0 0 1 0 0 0 Compare: software timer

- 1 0 0 1 1 0 0 Compare: high-speed output

- 1 0 0 0 0 1 0 Compare: 8-bit PWM

-1 0 0 10 or 1

1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

2. y = 0, 1, 2, 3, 4

3. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.

4. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.

0 0 Compare: PCA WDT (CCAPM4 only)

T8-5.0 1255

TABLE 8-6: PCA MODULE MODES

With Interrupt enabled

ECOMy

- 0 1 0 0 0 0 1 16-bit capture on positive-edge trigger at CEX[4:0]

- 0 0 1 0 0 0 1 16-bit capture on negative-edge trigger a t CEX[4:0]

- 0 1 1 0 0 0 1 16-bit capture on positive/negative-edge

- 1 0 0 1 0 0 1 Compare: software timer

- 1 0 0 1 1 0 1 Compare: high-speed output

-1 0 0 0 0 1 X

-1 0 0 10 or 1

1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

2. y = 0, 1, 2, 3, 4

3. No PCA interrupt is needed to generate the PWM.

4. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.

5. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer.

6. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.

CAPPy2CAPNy2MATy2TOGy2PWMy2ECCFy2Module Code

trigger at CEX[4:0]

Compare: 8-bit PWM

Compare: PCA WDT (CCAPM4 only)

T8-6.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

8.3.1 Capture Mode

Capture mode is used to capture the PCA timer/counter value into a module’s capture registers (CCAPnH and CCAPnL). The capture will occur on a positive edge, negative edge, or both on the corr esponding module’s pin. To use one of the PCA modu les in the capture mo de, either one or both the CCAPM bits CAPN and CAPP for that module must be set. When a valid transition occurs on the CEX pin corresponding to the module used, the PCA hardware loads the 16-bit value of the PCA counter register (CH

and CL) into the module’s capture regis ters (C CAPn L and CCAPnH). If the CCFn bit for the module in the CCON SFR and th e ECC Fn bi t i n th e CCAP Mn SF R a re se t, th en an interrupt will b e generated. In th e interru pt servi ce routine, the 16-bit capture value must be saved in RAM before the next event capture occurs. If a subsequent capture occurred, the o riginal capture values would be lost. After flag event flag has been set by hardware, the u ser must clear the flag in software. (See Figure 8-2)

Preliminary Specifications

CCON

CEXn

CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CCAPMn

n=0 to 4

FIGURE 8-2: PCA C

Capture

ECOMn

APTURE MODE

CAPPn

0000

CAPNn MATn TOGn PWMn ECCFn

PCA Interrupt

PCA Timer/Counter

CH CL

CCAPnH CCAPnL

1255 F24.0

Page 56

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

8.3.2 16-Bit Software Timer Mode

The 16-bit software timer mode is used to trigger interrupt routines, which must occur at pe rio dic inte rvals. It is setup by setting both the ECO M and MAT bits in the module’s CCAPMn register. The PCA timer wi ll be comp ared to the module’s capture registers (CCAPnL and CCAPnH) and when a match occurs, an interr upt will occur, if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

Write to

CCAPnL

Write to CCAPnH

Reset

CCAPnH CCAPnL

Enable Match

CF CR CCF4 CCF3 CCF2 CCF1 CCF0

16-bit Comparator

CH CL

If necessar y, a new 16-bit co mpare value can be loaded into CCAPnH and CCAPnL during the interrupt routine. The user should be aware that the hardware temporarily disables the comparat or functi on whil e these r egisters are being updated so that an invalid match will not occur. Thus, it is recommended that the us er write to the low byte first (CCAPnL) to disable the comparator, then write to the high byte (CCAPnH) to re-enable it. If a ny upd ate s to th e r eg isters are done, the user m ay want to hold o ff a ny in ter r u pts from occurring by clearing the EA bit. (See Figure 8-3)

CCON

PCA Interrupt

FIGURE 8-3: PCA C

PCA Timer/Counter

ECOMn

OMPARE MODE (SOFTWARE TIMER)

CAPPn

CAPNn MATn TOGn PWMn ECCFn

0000

1255 F25.0

CCAPMn

n=0 to 4

Page 57

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

8.3.3 High Speed Output Mode

The high speed ou tput mode is used to toggle a por t pin when a match occurs between the PCA timer and the preloaded value in the compare registers. In this mode, the CEX output pin (on por t 1) asso ciated with the PCA module will toggle every time there is a match between the PCA counter (CH and CL) and the captu re registers ( CCAPnH and CCAPnL). To activate this mode, the user must set TOG, MAT , and ECOM bits in the module’s CCAPMn SFR.

Write to

CCAPnL

Write to CCAPnH

Reset

CCAPnH CCAPnL

Enable Match

CF CR CCF4 CCF3 CCF2 CCF1 CCF0

16-bit Comparator

CH CL

High speed output mo de is muc h m ore a cc u rate tha n to ggling pins since the toggle occurs before branchi ng to an interrupt. In this case, interrupt latency wi ll not affect the accuracy of the output. When using high speed output, using an interr upt is optional. Only if the user wishes to change the time for the next toggle is it necessary to update the compare regi sters. Otherwise, the next toggle will occur when th e PCA ti mer rolls over and matche s the last compare value. (See Figure 8-4)

CCON

PCA Interrupt

Toggle

CEXn

FIGURE 8-4: PCA H

PCA Timer/Counter

ECOMn

IGH SPEED OUTPUT MODE

CAPPn

CAPNn MATn TOGn PWMn ECCFn

000

CCAPMn

n=0 to 4

1255 F26.0

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

8.3.4 Pulse Width Modulator

The Pulse Width Modulator (PWM) mode is used to generate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL ≥ CCAPnL the output is high. T o activate this mode, the user must set the PWM an d ECOM bits in the module’s CCAPMn SFR. (See Figure 8-5 and Table 8-7)

In PWM mode, the frequency of the output depends on the source for the PCA timer. Since there is only one set of CH and CL registers, all modules share the PCA timer and frequency. Duty cycle of the outpu t is co ntrolled by the value

CCAPnH

FlashFlex51 MCU

loaded into the high byte (CCAPnH) . Since writes to the CCAPnH register are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for comparison until the n ext period of the outp ut (when CL rolls over from 255 to 00).

To calculate values for CCAPnH for any duty cycle, use the following equation:

CCAPnH = 256(1 - Duty Cycle)

where CCAPnH is an 8-bit integer and Duty Cycle is a fraction.

CCAPnL

Enable

ECOMn

FIGURE 8-5: PCA P

8-bit Comparator

Overflow

CAPPn

ULSE WIDTH MODULATOR MODE

CAPNn MATn TOGn PWMn ECCFn

PCA Timer/Counter

00000

CL < CCAPnL

CL >= CCAPnL

CCAPMn

n=0 to 4

1255 F27.0

TABLE 8-7: PULSE WIDTH M ODULATOR FRE QUENCIES

PWM Frequency

PCA Timer Mode

1/12 Oscillator Frequency 3.9 KHz 5.2 KHz 1/4 Oscillator Frequency 11.8 KHz 15.6 KHz Timer 0 Overflow:

8-bit 15.5 Hz 20.3 Hz 16-bit 0.06 Hz 0.08 Hz 8-bit Auto-Reload 3.9 KHz to 15.3 Hz 5.2 KHz to 20.3 Hz

External Input (Max) 5.9 KHz 7.8 KHz

12 MHz 16 MHz

CEXn

T8-7.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

8.3.5 Watchdog Timer

The Watchdog Timer mode is used to impro v e reliability in the system without increasing chip count (See Figure 8-6). Watchdog Timers are useful f or systems that are susceptible to noise, power glitches, or electrostatic discharge. It can also be used to prev ent a softw a re deadlock. If during the execution of the user’s code, there is a deadlock, the Watchdog Timer will time out and an internal reset will occur. Only module 4 can be pr ogra mmed as a W atchd og Timer (but still can be programmed to other modes if the Watchdog T imer is not used ).

To use the Watchdog Timer, the user pre-loads a 16-bit value in the compare register. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur , an internal reset will be generated. This will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog timer by clearing the WDTE bit before a match occurs and then re-enable it.

The first two options are more reliable because the Watchdog Timer is never disabled as in option #3. If the program counter ever goes astray , a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the tim e base for other modul es would not be a good idea. Thus, in most application the first solution is the best option.

Use the code below to initialize the Watchdog Timer. Module 4 can be configure d in either comp are mode, and the WDTE bit in CMOD must also be set. The user’s software then must periodically change (CCAP4H, CCAP4L) to keep a match from occurring with the PCA timer (CH, CL). This code is given in the Watchdog routine below.

;============================================== Init_Watchdog:

MOVCCAPM4, #4CH; Module 4 in compare mode MOVCCAP4L, #0FFH; Write to low byte first MOVCCAP4H, #0FFH; Before PCA timer counts up

; to FFFF Hex, these compare ; values must be changed.

ORLCMOD, #40H; Set the WDTE bit to enable the

; watchdog timer without ; changing the other bits in

; CMOD ;============================================== ;Main program goes here, but call WATCHDOG periodically. ;============================================== WATCHDOG:

CLR EA; Hold off interrupts MOVCCAP4L, #00; Next compare value is within MOVCCAP4H, CH; 65,535 counts of the

; current PCA

SETBEA; timer value RET

;==============================================

This routine should not be part of an interrupt ser vice routine. If the program counter goes astra y and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program of the PCA timer .

Write to

Reset

CCAP4L

Write to CCAP4H

Enable

FIGURE 8-6: PCA W

ATCHDOG TIMER (MODULE 4 ONLY)

CIDL WDTE CPS1 CPS0 ECF

CCAP4H CCAP4L

16-bit Comparator

CH CL

PCA Timer/Counter

ECOMn

Module 4

Match

CAPPn

CAPNn MATn TOGn PWMn ECCFn

00X0

CMOD

Reset

CCAPM4

1255 F28.0

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

9.0 SECURITY LOCK

FlashFlex51 MCU

The security lock protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from acc idental erasing and pro gramming to the internal flash memory. There are two different types of security locks in the device security lock system: hard lock and SoftLock.

9.1 Hard Lock

When hard lock is activated, MOVC or IAP instructions executed from an unlocked or soft locked program address space, are disabled from reading code bytes in hard locked memory blocks (See Table 9-2). Hard lock can eithe r lock both flash memo ry blocks or just lock the 8 K Byte flash memory block (Block 1 ). All external host and IAP co mmands except for Chip-Erase are ignored for memory blocks that are hard locked.

9.2 SoftLock

SoftLoc k allow s flash cont ents to be alt ered unde r a secure environment. This lock option allows the user to update program code in the so ft locked memor y block through i napplication programming mode under a predetermined secure environmen t. For example, if Bl ock 1 (8K) mem or y block is locked (hard locked or sof t locked), and Block 0 memory block is soft locked, code residing in Block 1 can program Block 0. The following IAP mode commands

issued throu gh the comman d mail bo x regi ster, SFCM, exe cuted from a Locked (hard locked or soft locked) block, can be operated on a sof t locked block: Block-Erase, SectorErase, By te-Pr ogr am and By te-Verify.

In external host mode, Sof tLock behaves the same as a hard lock.

9.3 Security Lock Status

The three bits that indicate the device security lock status are located in S FST [7: 5]. A s shown in Fig ure 91 and Table 9-1, the thr ee se curity lock bits control th e lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the secur ity lock bits are programmed and both blocks are unlo cked. In the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via Byte-Verify. In t he third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2, Block 1 except read operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/program of internal memory or boot from external memor y. For details on how to program the security lock bits refer to the external hos t mode and in-application programming sections.

UPU/SS

UUU/NN

PUU/SS

UUP/LS

Level 1

Level 2

Level 3

UPP/LL PPU/LS

FIGURE 9-1: S

Note: P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked, S = Soft locked

ECURITY LOCK LEVELS

PUP/LL UPP/LL

PPP/LL

Level 4

1255 F29.0

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 9-1: S

Level

1 000 U U U Unlock Unlock No Security Features are Enabled. 2 100 P U U SoftLock SoftLock MOVC instructions executed from

3 011

4 111 P P P Hard Lock Hard Lock Same as Level 3 hard lock/hard lock,

1. P = Programmed (B it logic state = 0), U = Unprogrammed (Bit logic state = 1).

2. SF ST [7:5] = Secur ity Lock Status Bits (SB1_i, SB2_i, SB3_i)

ECURITY LOCK OPTIONS

Security Lock Bits

101 010 U P U SoftLock SoftLock Level 2 plus Verify disabled. Code in

110 001

P U

1,2 1

P U

SB3

P P

U P

Security Status of:

Block 1 Block 0

Hard Lock Hard Lock Level 2 plus Verify disabled, both

Hard Lock SoftLock Level 2 plus Verify disabled. Code in

Security TypeSFST[7:5] SB1 SB2

external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled.

blocks locked.

Block 1 ma y prog ram Blo ck 0 an d vice versa.

Block 1 may program Block 0.

but MCU will start code execution from the internal memory regardless of EA#.

T9-1.0 1255

9.4 Read Operation Under Lock Condition

The status of secu rity bits SB1, SB2, and SB 3 can be r ead when the read command is disabled by security lock. There are three ways to read the status.

1. External host mode: Read-back = 00H (locked)

2. IAP command: Read-back = previous SFDT data

3. MOVC: Read-back = FFH (blank)

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SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 9-2: SECURITY LOCK ACCESS TABLE

Source

Level SFST[7:5]

Address

Block 0/1

(hard lock on both blocks)

111b

External

Block 0/1

011b/101b

(hard lock on both blocks)

External

Block 0

001b/110b (Block 0 = SoftLock, Block 1 = hard lock)

Block 1

External

Block 0

010b

(SoftLock on both blocks)

Block 1

External

Block 0

(SoftLock on both blocks)

100b

Block 1

External

Block 0

000b

(unlock)

Block 1

External

1. Locat ion of MOVC or IAP instruction

2. Target address is the location of the byte being read

3. Ext ernal host Byte-Verify access does not depend on a source address.

FlashFlex51 MCU

Target

Address

Block 0/1 N N Y Y

External N/A N/A N Y

Block 0/1 N N N N

External N/A N/A N Y

Block 0/1 N N Y Y

External N/A N/A N Y

Block 0/1 N N N N

External N/A N/A Y Y

Block 0 N N Y Y Block 1 N N N N

External N/A N/A N Y

Block 0 N Y Y Y Block 1 N N Y Y

External N/A N/A N Y

Block 0/1 N N N N

External N/A N/A Y Y

Block 0 N N Y Y Block 1 N Y Y Y

External N/A N/A N Y

Block 0 N Y Y Y Block 1 N N Y Y

External N/A N/A N Y

Block 0/1 N N N N

External N/A N/A Y Y

Block 0 Y N Y Y Block 1 Y Y Y Y

External N/A N/A N Y

Block 0 Y Y Y Y Block 1 Y N Y Y

External N/A N/A N Y

Block 0/1 Y N N N

External N/A N/A Y Y

Block 0 Y N Y Y Block 1 Y Y Y Y

External N/A N/A N Y

Block 0 Y Y Y Y Block 1 Y N Y Y

External N/A N/A N Y

Block 0/1 Y Y N Y

External N/A N/A Y Y

Byte-Verify Allowed MOVC Allowed

External Host

IAP 516RD2 5xRD2

T9-2.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

10.0 RESET

A system reset initializes the MCU and begins program execution at program memor y location 0000H. The r eset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycle s (24 clo cks), after the oscil lator becomes stable. ALE, PSE N# are weakly pulled hi gh dur ing reset. During reset, ALE and PSEN# output a high level in order to perform a prop er reset. This level must not be affected by external element. A system reset will not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-7 to 3-11.

10.1 Power-on Reset

At initial power up, the port pins will be in a random state until the oscill ator has star ted and the internal reset algorithm has weakly pulled all pins high. Powering up the

device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash.

When power is applied to the device, the RST pin must be held high long enoug h for the oscilla tor to st art up (usual ly sev eral milliseco nds f or a lo w freq uency crystal), i n addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to V µF capacitor and to V

through an 8.2KΩ resistor as

shown in Figure 10- 1. Note that if an RC circui t is being used, provisions shou ld be made to ensure the V time does not exceed 1 millisecond and the oscillator startup time does not exceed 10 milliseconds.

For a low frequency oscillator wit h slow start-up tim e the reset signal must be extended in order to a ccount for the slow start-up ti me. This method maintains the necessar y relationship between V

and RST to avoid programming

at an indeterm inate locati on, which may cause corr uption in the code of the flash. The power-on detection is designed to wor k as power up initia lly, before the voltage reaches the brown-out detection level. The POF flag in the PCON register i s set to in dicate an i nitial power up condition. The POF flag w ill remain act ive until cleared by software. Please refer to Section 3.5, PCON register definition for detail information.

For more information on system level design techniques, please review the

FlashFle x51 Family Microcontrolle r

Design Considerations for the SST

application note.

through a 10

rise

10µF

8.2K

FIGURE 10-1: P

OWER-ON RESET CIRCUIT

10.2 Software Reset

The software reset is executed by changing SFCF[1] (SWR) from “0” to “1”. A software reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.

10.3 Brown-out Detection Reset

The device includes a brown-out detection circuit to protect the system fr om s e v ered sup plied v olt age V SST89E5xxRD2 internal brown-out detection threshold is

3.85V, SST89V5xxRD2 brown-out detection threshold is

2.35V. For brown -out voltage parameters, please r efer to Tables 14-6 and 14-7.

When V out detector triggers the circuit to generate a brown-out interrupt but the CPU still runs until the supplied voltage returns to the brown-out detection voltage V default operation for a brown-out detection is to cause a processor reset.

ods before the brown-out detection circuit will respond. Brown-out interr upt ca n be ena bled by setting th e EBO bi t

in IEA register (address E8H, bit 3). If EBO bit is set and a brown-out condition occurs, a brown-out int errupt will be generated to execute the program at location 0 04BH. It is required that the EB O bit be cleare d by software after the brown-out interrupt is serviced. Clearing EBO bit when the brown-out condition i s active will pr oper ly res et the d evice. If brown-out interru pt is not enabled, a br own-o ut c ond it io n will reset the program to resume execution at location 0000H.

drops below this voltage t hreshold, th e brown-

must sta y below V

at least four oscillator clock peri-

BOD

Preliminary Specifications

RST

SST89E/V5xxRD2

XTAL2

XTAL1

1255 F30.0

fluctuations.

. The

BOD

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

11.0 INTERRUPTS

11.1 Interrupt Priority and Polling Sequence

The device support s eight int errupt s ources un der a four level priority sch eme. Table 11-1 summarizes the p olling sequence of the supported interrupts. Note that th e SPI serial in terface and the UART share the same interrup t vector. (See Figure 11-1)

TABL E 11-1: I

Description Interrupt Flag

Ext. Int0 IE0 0003H EX0 PX0/H 1(highest) yes Brown-out - 004BH EBO PBO/H 2 no T0 TF0 000BH ET0 PT0/H 3 no Ext. Int1 IE1 0013H EX1 PX1/H 4 yes T1 TF1 001BH ET1 PT1/H 5 no PCA CF/CCFn 0033H EC PPCH 6 no Ext. Int. 2 IE2 003BH EX2 PX2/H 7 no Ext. Int. 3 IE3 0043H EX3 PX3/H 8 no UART/SPI TI/RI/SPIF 0023H ES PS/H 9 no T2 TF2, EXF2 002BH ET2 PT2/H 10 no

NTERRUPT POLLING SEQUENCE

Vector

Address

Interrupt

Enable

Interrupt

Priority

Service Priority

Wake-Up

Power-down

T11-1.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

IP/IPH/IPA/IPAH

REGISTERS

INT0#

IE & IEA

REGISTERS

IT0

IE0

Preliminary Specifications

HIGHEST PRIORITY INTERRUPT

CCFn

ECF

ECCFn

BOF

TF0

INT1#

TF1

INT2#

INTERRUPT POLLING SEQUENCE

IT1

0 1

IE1

IE2IT2

TF2

EXF2

0 1

RI TI

IE3IT3

INDIVIDUAL

ENABLES

GLOBAL DISABLE

LOWEST PRIORITY INTERRUPT

1255 F31.0

INT3#

SPIF

SPIE

FIGURE 11-1: INTERRUPT STRUCTURE

Page 66

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

12.0 POWER-SAVING MODES

The device provides two power saving modes of operation for applications where power consumption is crit ical. The two modes are idle and power-down, see Tabl e 12-1.

12.1 Idle Mode

Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode.

The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits idle mode . After e x it th e Inte rrupt Se rvice Routin e , the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. A hardware reset sta r ts th e device similar to a power-on reset.

TABL E 12-1: P

Mode Initiated by State of MCU Exited by

Idle Mode Software

Power-down

Mode

OWER S AVING MODES

(Set IDL bit in PCON)

MOV PCON, #01H;

Software

(Set PD bit in PCON)

MOV PCON, #02H;

CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged.

CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during power -down. External Interrupts are only active for level sensitive interrupts , if enabled.

12.2 Power-down Mode

The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during powerdown, the minimu m V

The device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The star t of the int errup t clears the PD bi t and exits power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hol d low at least 1024 c lock cycles before bringing back high to complete the exit. Upon interrupt si gnal b eing re st ored t o logic V tion of the interrupt service routine will execute. A hardware reset starts the device similar to power-on reset.

To exit properly out of power-down, the reset or external interrupt should not be executed before the V restored to its normal operating voltage. Be sure to hold V

voltage long enough at its normal operating level for

the oscillator to restart and stabilize (normally less than 10 ms).

level is 2.0V.

the first instruc-

IH,

line is

Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle mode, after the ISR RETI instruc tion, program r esumes execution beginning at the instruction following the one that invoked idle m ode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts t he device similar t o a power-on rese t.

Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits powerdown mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. A user could consider placing two or three NOP instructions after th e instruction that invokes power -down mode to eliminate any problems. A hardware reset restarts the de vice s imilar to a power-on reset.

T12-1.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

13.0 SYSTEM CLOCK AND CLOCK OPTIONS

Preliminary Specifications

13.1 Clock Input Options and Recommended Capacitor Values for Oscillator

Shown in Figure 13 -1 are the i nput a nd out put of an internal inverting am plifier ( XTAL1, XTAL2), which can be configured for use as an on-chip oscillator.

When driving the device from an external clock source, XTAL2 should be l eft disconne cted and XTAL1 should be driven.

At star t-up, the external oscillat or may encoun ter a high er capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the V

Crystal manufacturer, supply voltage, and other factors may cause circuit perfor mance to differ from one application to another. C1 and C2 shou ld be adjusted appropr iately fo r each design. Table 13-1, shows the typical values for C1 and C2 vs. crystal type for various frequencies

TABL E 13-1:RECOMMENDED VALUES FOR C1 AND

and VIH specifications.

BY CRYSTAL TYPE

Crystal C1 = C2

Quartz 20-30pF

Ceramic 40-50pF

T13-1.0 1255

More specific information about on-chip oscillator design can be found in the

Considera tions

FlashFlex51 Oscill ator Circuit Des ign

application note.

13.2 Clock Doubling Option

By default, the device runs at 12 clo cks pe r mac h in e c ycl e (x1 mode). The device has a clock doubling option to speed up to 6 clocks per ma chine cycle. Please refer to Table 13-2 for detail.

Clock double mode can be e nabled eit her vi a the external host mode or the IAP mode. Please refer to Table 4-1 for the ext e rnal ho st mo de en a bling command an d t o Table 46 and Table 4-7 for the IAP mode enabling commands (When set, the EDC# bit in SFST register will indicate 6 clock mode.).

The clock double mode is only for doubling the internal system clock and the internal flash memory, i.e. EA#=1. To access the external memory and the peripheral

devices, careful consideration must be taken. Also note that the crystal output (XTAL2) will not be doubled.

Using the On-Chip Oscillator

FIGURE 13-1: O

SCILLATOR CHARACTERISTICS

XTAL2

XTAL1

External

Oscillator

Signal

External Clock Drive

XTAL2

XTAL1

1255 F32.0

TABL E 13-2: CLO CK DOUBLING FEATURES

Device Standard Mode (x1) Clock Double Mode (x2)

Clocks per

Machine Cycle

SST89E5xxRD2 12 40 6 20 SST89V5xxRD2 12 33 6 16

Max. External Clock Frequency

(MHz)

Clocks per

Machine Cycle

Max. External Clock Frequency

(MHz)

T13-2.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

14.0 ELECTRICAL SPECIFICATION

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on EA# Pin to V

D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20ns) on Any Other Pin to V Maximum I Maximum I

per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

Package Power Dissipation Capability (T

Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240° C

Output Short Circ uit Curr ent

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD+1.0V

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

+0.5V

1. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption.

Note: This specification contains preliminary information on new products in production.

The specifications are subject to change without notice.

TABL E 14-1: OPERATING RANGE

Symbol Description Min. Max Unit

Ambient Temperature Under Bias

Standard 0 +70 Industrial -40 +85 °C

Supply Voltage

SST89E5xxRD2 4.5 5.5 V SST89V5xxRD2 2.7 3.6 V

OSC

Oscillator Frequency

SST89E5xxRD2 0 40 MHz SST89V5xxRD2 0 33 MHz

Oscillator Frequency for IAP

SST89E5xxRD2 .25 40 MHz SST89V5xxRD2 .25 33 MHz

TABL E 14-2: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

END

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

mA JEDEC Standard 78

°C

T14-1.0 1255

T14-2.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABL E 14-3: AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF

See Figures 14-8 and 14-10

T14-3.0 1255

TABL E 14-4: RECOMME NDED SYSTEM POWER-UP TIMIN GS

Symbol Parameter Minimum Units

PU-READ

PU-WRITE

Power-up to Read Operation 100 µs

Power-up to Write Operation 100 µs

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter

T14-4.0 1255

TABL E 14-5: PIN IMPEDANCE (V

=3.3V, Ta=25 °C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. Refer to PCI spec.

I/O Pin Capacitance V Input Capacitance V

= 0V 15 pF

I/O

= 0V 12 pF

Pin Inductance 20 nH

T14-5.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

14.1 DC Electrical Characteristic s

TABLE 14-6: DC ELECTRICAL CHARACTERISTICS FOR SST89E 5XX RD2

= -40°C TO +85°C; V

Symbol Parameter Test Conditions Min Max Units

V V V V

V I I I R C I

IL IH IH1 OL

OL1

OH1

BOD IL TL LI

RST

IO DD

Input Low Voltage 4.5 < VDD < 5.5 -0.5 0.2VDD - 0.1 V Input High Voltage 4.5 < VDD < 5.5 0.2VDD + 0.9 VDD + 0.5 V Input High Voltage (X TAL1, RST) 4.5 < VDD < 5.5 0.7V Output Low Voltage (Ports 1.5, 1.6, 1.7) VDD = 4.5V

Output Low Voltage (Ports 1, 2, 3)

Output Low Voltage (Port 0, ALE, PSEN#)

Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)

Output Hi gh Voltage (Port 0 in External Bus Mode)

Brown-out Detection Voltage 3.85 4.15 V Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.4V -75 µA Logical 1-to-0 Transition Current (Ports 1, 2, 3) Input Leakage Current (Port 0) 0.45 < VIN < VDD-0.3 ±10 µA RST Pull-down Resistor 40 225 KΩ Pin Capacitance

Power Supply Current IAP Mode @ 12 MHz 70 mA @ 40 MHz 88 mA Active Mode @ 12 MHz 23 mA @ 40 MHz 50 mA Idle Mode @ 12 MHz 20 mA @ 40 MHz 42 mA Power-down Mode (min. V

= 4.5-5.5V; V

1,3

= 0V

= 16mA 1.0 V

VDD + 0.5 V

VDD = 4.5V

IOL = 100µA

= 1.6mA

IOL = 3.5mA

2 2 2

0.3 V

0.45 V

1.0 V

VDD = 4.5V

= 200µA

IOL = 3.2mA

VDD = 4.5V

= -10µA VDD - 0.3 V

2 2

0.3 V

0.45 V

IOH = -30µA VDD - 0.7 V IOH = -60µA VDD - 1.5 V

VDD = 4.5V IOH = -200µA VDD - 0.3 V IOH = -3.2mA VDD - 0.7 V

VIN = 2V -650 µA

@ 1 MHz, 25°C 15 pF

= 2V) Ta = 0°C to +70°C 80 µA

Ta = -40°C to +85°C 90 µA

T14-6.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum I Maximum I Maximum I If I

Pins are not guaranteed to sink current greater than the listed test conditions.

2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.

4. Capacitive loading on Ports 0 & 2 may cause the V the address bits are stabilizing.

5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

6. Pin capacitance is characterized but not tested. EA# is 25pF (max).

per port pin: 15mA

per 8-bit port:26mA

total for all outputs:71mA

exceeds the test condition, VOL may exceed the related specification.

on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when

is approximately 2V.

s of ALE and Ports 1 & 3. The noise due

Page 72

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABLE 14-7: DC ELECTRICAL CHARACTERISTICS FOR SST89V 5XX RD2

= -40°C TO +85°C; V

Symbol Parameter Test Conditions Min Max Units

V V V V

V I I I R C I

IL IH IH1 OL

OL1

OH1

BOD IL TL LI

RST

IO DD

Input Low Voltage 2.7 < VDD < 3.6 -0.5 0.7 V Input High Voltage 2.7 < VDD < 3.6 0.2VDD + 0.9 VDD + 0.5 V Input High Voltage (XTAL1, RST) 2.7 < VDD < 3.6 0.7V Output Low Voltage (Ports 1.5, 1.6, 1.7) VDD = 2.7V

Output Low Voltage (Ports 1, 2, 3)

Output Low Voltage (Port 0, ALE, PSEN#)

Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)

Output High Voltage (Port 0 in External Bus Mode)

Brown-out Detection Voltage 2.35 2.55 V Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.4V -75 µA Logical 1-to-0 Transition Current (Ports 1, 2, 3) Input Leakage Current (Port 0) 0.45 < VIN < VDD-0.3 ±10 µA RST Pull-down Resistor 225 KΩ Pin Capacitance

Power Supply Current IAP Mode @ 12 MHz 40 mA @ 33 MHz 47 mA Active Mode @ 12 MHz 11.5 mA @ 33 MHz 30 mA Idle Mode @ 12 MHz 8.5 mA @ 33 MHz 21 mA Power-down Mode (min. V

1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum I Maximum I Maximum I If I

listed test conditions.

per port pin: 15mA

per 8-bit port: 26mA

total for all outputs:71mA

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the

= 2.7-3.6V; V

= 0V

VDD + 0.5 V

IOL = 16mA 1.0 V

1,3

VDD = 2.7V IOL = 100µA IOL = 1.6mA

= 3.5mA

VDD = 2.7V IOL = 200µA

= 3.2mA

VDD = 2.7V

2 2 2

2 2

0.3 V

0.45 V

1.0 V

0.3 V

0.45 V

IOH = -10µA VDD - 0.3 V

= -30µA VDD - 0.7 V

IOH = -60µA VDD - 1.5 V

VDD = 2.7V

= -200µA VDD - 0.3 V

IOH = -3.2mA VDD - 0.7 V

VIN = 2V -650 µA

@ 1 MHz, 25°C 15 pF

= 2V) Ta = 0°C to +70°C 45 µA

Ta = -40°C to +85°C 55 µA

T14-7.0 1255

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FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.

4. Capacitive loading on Ports 0 & 2 may cause the V the address bits are stabilizing.

5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

6. Pin capacitance is characterized but not tested. EA# is 25pF (max).

is approximately 2V.

on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when

Page 74

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Maximum Active I

Typical Active I

(mA)

5101520253035

Internal Clock Frequency (MHz)

FIGURE 14-1: IDD VS. FREQUENCY FOR 3V SST89V5XXRD2

Maximum Idle I

Typical Idle I

1255 F33.0

Maximum Active I

(mA)

510152025303540

Internal Clock Frequency (MHz)

FIGURE 14-2: I

VS. FREQUENCY FOR 5V SST89E5XXRD2

Typical Active I

Maximum Idle I

Typical Idle I

1255 F34.0

Page 75

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

14.2 AC Electrical Characteristics

AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF;

Load Capacitance for All Other Outputs = 80pF)

TABL E 14-8: AC E

= -40°C TO +85°C, VDD = 2.7-3.6V@33MHZ, 4.5-5.5V@40MHZ, VSS = 0V

Symbol Parameter

1/T 1/2T T

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

PLAZ

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

CLCL

x1 Mode Oscillator Frequency x2 Mode Oscillator Frequency

CLCL

ALE Pulse Width Address Valid to ALE Low

Address Hold After ALE Low

ALE Low to Valid Instr In

ALE Low to PSEN# Low

PSEN# Pulse Width PSEN# Low to Valid Instr In

Input Instr Hold After PSEN# Input Instr Float After PSEN#

PSEN# to Address valid Address to Valid Instr In

PSEN# Low to Address Float RD# Pulse Width

Write Pulse Width (WE#) RD# Low to Valid Data In

Data Hold After RD# Data Float After RD#

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD# or WR# Low Address to RD# or WR# Low

LECTRICAL CHARACTERISTICS (1 OF 2)

33 MHz (x1 Mode)

16 MHz (x2 Mode)

Min Max Min Max Min Max

033040 0 40 MHz 016020 0 20 MHz

46 35 2T

56 4T

35 3T

25 T

22 17 T

72 5T

10 10 10 ns

142

62 5T

00 0 ns

36 2T

152 8T

183 9T

66 116

46 4T

Oscillator

40 MHz (x1 Mode)

20 MHz (x2 Mode)

10 T

55 4T

10 T

25 3T

10 T

65 5T

120

75 5T

38 2T

150 8T

150 9T

60 90

70 4T

Variable

Units

- 15 ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 65 (3V) ns

CLCL

- 45 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 15 (5V) ns

CLCL

3T 3T

CLCL CLCL

- 25 (3V)

- 15 (5V)

- 55 (3V) ns

CLCL

- 50 (5V) ns

CLCL

0ns

- 5 (3V) ns

CLCL

- 15 (5V) ns

CLCL

- 8 ns

CLCL

- 80 (3V) ns

CLCL

- 60 (5V) ns

CLCL

- 40 (3V)

CLCL

- 30 (5V)

CLCL

- 40 (3V)

CLCL

- 30 (5V)

CLCL

- 90 (3V) ns

CLCL

- 50 (5V) ns

CLCL

- 25 (3V) ns

CLCL

- 12 (5V) ns

CLCL

- 90 (3V) ns

CLCL

- 50 (5V) ns

CLCL

- 90 (3V) ns

CLCL

- 75 (5V) ns

CLCL

- 25 (3V)

CLCL

- 15 (5V)

CLCL

- 75 (3V) ns

CLCL

- 30 (5V) ns

CLCL

3T 3T

CLCL CLCL

+ 25 (3V) + 15 (5V)

Page 76

Preliminary Specifications

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

TABL E 14-8: AC E

Symbol Parameter

WHQX

QVWH

QVWX

Data Hold After WR#

Data Valid to WR# High

Data Valid to WR# High to Low

LECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2)

= -40°C TO +85°C, VDD = 2.7-3.6V@33MHZ, 4.5-5.5V@40MHZ, VSS = 0V

Oscillator

33 MHz (x1 Mode)

16 MHz (x2 Mode)

Min Max Min Max Min Max

142 7T

10 5 T

40 MHz (x1 Mode)

20 MHz (x2 Mode)

125 7T

CLCL CLCL

CLCL

- 27 (3V) ns

- 20 (5V) ns

- 70 (3V) ns

- 50 (5V) ns

- 20 ns

Variable

Units

Transition

RLAZ

WHLH

1. Calculated values are for x1 Mode only

RD# Low to Address Float 0 0 0 ns RD# to WR# High to ALE High 5 55 T

10 40 T

- 25 (3V) T

CLCL

- 15 (5V) T

CLCL

+ 25 (3V) ns

CLCL

+ 15 (5V) ns

CLCL

T14-8.0 1255

Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.

A: Address Q: Output data C: Clock R: RD# signal D: Input data T: Time H: Logic level HIGH V: Valid I: Instruction (program memory contents) W: WR# signal L: Logic level LOW or ALE X: No longer a valid logic level P: PSEN# Z: High Impedance (Float)

For example:

= Time from Address Valid to ALE Low

AVLL

= Time from ALE Low to PSEN# Low

LLPL

Page 77

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

LHLL

ALE

PLPH

PXAV

A0 - A7

A8 - A15

PSEN#

PORT 0

PORT 2

AVLL

LLAX

A0 - A7

LLPL

AVIV

A8 - A15

PLAZ

LLIV

PLIV

PXIZ

PXIX

INSTR IN

Preliminary Specifications

FIGURE 14-3: EXTERNAL PROGRAM MEMORY READ CYCLE

LHLL

ALE

PSEN#

RD#

PORT 0

PORT 2

AVLL

A0-A7 FROM RI or DPL

AVWL

P2[7:0] or A8-A15 FROM DPH

AVDV

LLWL

LLAX

RLAZ

LLDV

RLRH

RLDV

DATA IN

WHLH

RHDZ

RHDX A0-A7 FROM PCL

A8-A15 FROM PCH

1255 F35.0

INSTR IN

1255 F36.0

FIGURE 14-4: EXTERNAL DATA MEMORY READ CYCLE

Page 78

Preliminary Specifications

ALE

PSEN#

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

LHLL

WHLH

LLWL

WR#

PORT 0

PORT 2

AVLL

A0-A7 FROM RI or DPL

LLAX

QVWX

AVWL

P2[7:0] or A8-A15 FROM DPH

FIGURE 14-5: EXTERNAL DATA MEMORY WRITE CYCLE

TABL E 14-9: EXTERNAL CLOCK DRIVE

12MHz 40MHz Variable

Symbol Parameter

1/T T

CLCL

CHCX

CLCX

CLCH

CHCL

CLCL

Oscillator F requency 0 40 MHz

High Time 8.75 0.35T Low Time 8.75 0.35T Rise Time 20 10 ns Fall Time 20 10 ns

MinMaxMinMax Min Max

83 25 ns

WLWH

QVWH DATA OUT

WHQX

A0-A7 FROM PCL

Oscillator

INSTR IN

A8-A15 FROM PCH

CLCL CLCL

0.65T

1255 F37.0

CLCL CLCL

Units

ns ns

T14-9.0 1255

DD - 0.5

0.45 V

0.7V

0.2 VDD - 0.1

CHCL

CLCX

CLCL

CHCX

CLCH

1255 F38.0

FIGURE 14-6: EXTERNAL CLOCK DRIVE WAVEFORM

Page 79

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

TABL E 14-10: SERIAL PORT TIMING

Oscillator

12MHz 40MHz Variable

Symbol Parameter

XLXL

QVXH

XHQX

XHDX

XHDV

Serial Port Clock Cycle Time 1.0 0.3 12T Output Data Setup to Clock Rising Edge 700 117 10T Output Data Hold After Clock Rising Edge 50 2 T

Input Data Hold After Clock Rising Edge 0 0 0 ns Clock Rising Edge to Input Data Valid 700 117 10T

Min Max Min Max Min Max

CLCL

- 133 ns

CLCL

- 117 ns

CLCL

02T

- 50 ns

CLCL

Preliminary Specifications

Units

µs

- 133 ns

CLCL

T14-10.0 1255

INSTRUCTION

ALE

1 2 3 4 5 6 7 8

XLXL

CLOCK

XHQX

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHDX

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

QVXH

01 234 567

FIGURE 14-7: SHIFT REGISTER MODE TIM IN G WAVEFORMS

IHT

ILT

AC Inputs during testing are driven at V V

(0.45V) for a Logic "0". Measurement reference points for inputs and

ILT

outputs are at V

(VDD -0.5V) for Logic "1" and

IHT

(0.2VDD + 0.9) and VLT (0.2VDD - 0.1)

Note: VHT- V VLT- V V

IHT-VINPUT

ILT

1255 F40.0

HIGH LOW

- V

INPUT

Test

HIGH Test

LOW Test

SET TI

SET R I

1255 F39.0

+0.1V

LOAD

-0.1V

LOAD

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/I

Timing Reference

Points

1255 F41.0

= ± 20mA.

-0.1V

+0.1V

FIGURE 14-8: AC TESTING INPUT/OUTPUT TEST

FIGURE 14-9: FLOAT WAVEFORM

WAVEFORM

Page 80

SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TO DUT

1255 F42.0

FIGURE 14-10: A TEST LOAD EXAMPLE

TO TESTER

FlashFlex51 MCU

SST89x5xxRD2

CLOCK SIGNAL

All other pins disconnected

(NC)

XTAL2 XTAL1

EA#RST

FIGURE 14-11: IDD TEST CONDITION,

CTIVE MODE

EA#RST

1255 F43.0

VDD = 2V

SST89x5xxRD2

(NC)

All other pins disconnected

XTAL2 XTAL1

EA#RST

FIGURE 14-13: IDD TEST CONDITION,

OWER-DOWN MODE

1255 F44.0

SST89x5xxRD2

CLOCK SIGNAL

All other pins disconnected

(NC)

XTAL2 XTAL1

1255 F45.0

FIGURE 14-12: IDD TEST CONDITION,

DLE MODE

Page 81

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

TABL E 14-11: EXTERNAL MODE FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS

Parameter

Reset Setup Time T Read-ID Command Width T PSEN# Setup Time T Address, Command, Data Setu p Time T Chip-Erase Time T Block-Erase Time T Sector-Erase Time T Program Setup Time T Address, Command, Data Hold T Byte-Program Time Select-Block Program Time T Re-map or Security bit Program Time T Verify Command Delay Time T Verify High Order Address Delay Time T V eri fy Lo w Ord er Addres s Delay Time T

1. For IAP operations, the program execution overhead must be added to the above timing parameters.

2. Program and Erase times will scale inversely proportional to programming clock frequency.

3. All timing measurements are from the 50% of the input to 50% of the output.

4. Each byte must be erased before programming.

2,3

Symbol Min Max Units

SU RD ES

ADS

CE BE SE

PROG

PSB

AHA

ALA

DH PB

PS OA

3µs 1 µs

40 µs

0ns

150 ms

100 ms

30 ms

1.2 µs 0ns

50 µs

500 ns

80 µs 50 ns 50 ns 50 ns

T14-11.0 1255

Page 82

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

14.3 Flash Memory Programming Timing Diagrams with External Host Mode

RST

PSEN#

ALE/PROG#

EA#

P2[7:6] ,P3[7:6]

P3[5:4] ,P2[5:0] ,P1

Device ID = See Table 4-3, "Product Identification"

0000b

0030H

BFH

FIGURE 14-14: READ-ID

Reads chip signature and identification registers at the addressed location.

RST

ADS

PROG

PSEN#

ALE/PROG#

0000b

0031H

Device ID

1255 F46.0

EA#

P3[3]

PSB

P3[5:4], P2[5:0] A5H/55H

P3[7:6], P2[7:6]

FIGURE 14-15: S

ELECT-BLOCK1 / SELECT-BLOCK0 (FOR SST89E516RD2/SST89V516RD2 ONLY)

1001b

1255 F47.0

Enables the selection o f either of the flash memor y blocks prior to issuing a Byte-Verify, Block-Erase, SectorErase, or Byte-Program.

Page 83

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

RST

PSEN#

ADS

ALE/PROG#

EA#

P3[3]

PROG

Preliminary Specifications

P3[7:6], P2[7:6]

0001b

FIGURE 14-16: CHIP-ERASE

Erases both flash memory blocks. Security lock is ignored and the security bits are erased too.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

1255 F48.0

P3[7:6], P2[7:6] 1101b

1255 F49.0

FIGURE 14-17: B

LOCK-ERASE FOR SST89E51 6RD2/SST89 V516RD2

Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.

Page 84

Preliminary Specifications

RST

PSEN#

ALE/PROG#

EA#

P3[3]

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

ADS

PROG

P3[7:6], P2[7:6]

P3[5:4], P2[5:0]

1101b

FIGURE 14-18: BLOCK-ERASE FOR SST89E5XRD2/SST89V5XRD2

Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

1255 F50.0

P3[7:6], P2[7:6]

P3[5:4], P2[5:0]

FIGURE 14-19: S

ECTOR-ERASE

1011b

1255 F51.0

Erases the addressed sector if the security lock is not activated on that flash memory block.

Page 85

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

Preliminary Specifications

P3[5:4], P2[5:0]

P3[7:6], P2[7:6]

1110b

1255 F52.0

FIGURE 14-20: BYTE-PROGRAM

Programs the addressed cod e byte if the byte location has be en successfully erased and not yet programmed . Byte-Program operation is only allowed when the security lock is not activated on that flash memory block.

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

P3[7:6], P2[7:6]

FIGURE 14-21: P

ROG-SB1 / PROG-SB2 / PROG-SB3

1111b / 0011b / 0101b

1255 F53.0

Programs the Security bits SB1, SB2 and SB3 respectively . Only a Chip-Erase will erase a programmed security bit.

Page 86

SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

RST

ADS

PROG

PSEN#

ALE/PROG#

EA#

P3[3]

P3[5:4], P2[5:0] 5AH / AAH

FlashFlex51 MCU

P3[7:6], P2[7:6]

1001b

1255 F54.0

FIGURE 14-22: PROG-SC0 / PROG-SC1

Programs the star t-up configuration bit SC0/SC1. O nly a Chip-Erase will erase a programmed SC0/SC1 bit. Prog-SC1 applies to SST89E5 xRD 2/S ST89V5xRD2 only.

RST

PSEN#

ALE/PROG#

EA#

P3[7:6], P2[7:6]

1100b

AHA

ALA

P3[5:4], P2[5:0]

FIGURE 14-23: B

YTE-VERIFY

1255 F55.0

Reads the code byte from the addres sed flas h memory location if the secur ity lock is not act ivated on that flas h memory block.

Page 87

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

15.0 PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

Preliminary Specifications

SST89

x5xxRD2- XX -X-X X

Package Modifier

I = 40 pins J = 44 pins

Package Type

P = PDIP N = PLCC TQ = TQFP

Operation Temperature

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Operating Frequency

33 = 0-33MHz 40 = 0-40MHz

Feature Set and Flash Memory Size

52RD2 = C52 feature set + 8(16) KByte 54RD2 = C52 feature set + 16(32) KByte 58RD2 = C52 feature set + 32(40) KByte 516RD2 = C52 feature set + 64(72) KByte

Note: Number in parenthesis includes an additional 8 KByte flash which can be enabled.

Voltage Range

E = 4.5-5.5V V = 2.7-3.6V

Product Series

89 = C51 Core

15.1 Valid Combinations

Valid combinations for SST89E52RD2

SST89E52RD2-40-C-PI SST89E52RD2-40-C-NJ SST89E52RD2-40-C-TQJ SST89E52RD2-40-C-PIE SST89E52RD2-40-C-NJE SST89E52RD2-40-C-TQJE

SST89E52RD2-40-I-PI SST89E52RD2-40-I-NJ SST89E52RD2-40-I-TQJ SST89E52RD2-40-I-PIE SST89E52RD2-40-I-NJE SST89E52RD2-40-I-TQJE

Valid combinations for SST89V52RD2

SST89V52RD2-33-C-PI SST89V52RD2-33-C-NJ SST89V52RD2-33-C-TQJ SST89V52RD2-33-C-PIE SST89V52RD2-33-C-NJE SST89V52RD2-33-C-TQJE

SST89V52RD2-33-I-PI SST89V52RD2-33-I-NJ SST89V52RD2-33-I-TQJ SST89V52RD2-33-I-PIE SST89V52RD2-33-I-NJE SST89V52RD2-33-I-TQJE

Page 88

SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Valid combinations for SST89E54RD2

SST89E54RD2-40-C-PI SST89E54RD2-40-C-NJ SST89E54RD2-40-C-TQJ SST89E54RD2-40-C-PIE SST89E54RD2-40-C-NJE SST89E54RD2-40-C-TQJE

SST89E54RD2-40-I-PI SST89E54RD2-40-I-NJ SST89E54RD2-40-I-TQJ SST89E54RD2-40-I-PIE SST89E54RD2-40-I-NJE SST89E54RD2-40-I-TQJE

Valid combinations for SST89V54RD2

SST89V54RD2-33-C-PI SST89V54RD2-33-C-NJ SST89V54RD2-33-C-TQJ SST89V54RD2-33-C-PIE SST89V54RD2-33-C-NJE SST89V54RD2-33-C-TQJE

SST89V54RD2-33-I-PI SST89V54RD2-33-I-NJ SST89V54RD2-33-I-TQJ SST89V54RD2-33-I-PIE SST89V54RD2-33-I-NJE SST89V54RD2-33-I-TQJE

Valid combinations for SST89E58RD2

SST89E58RD2-40-C-PI SST89E58RD2-40-C-NJ SST89E58RD2-40-C-TQJ SST89E58RD2-40-C-PIE SST89E58RD2-40-C-NJE SST89E58RD2-40-C-TQJE

SST89E58RD2-40-I-PI SST89E58RD2-40-I-NJ SST89E58RD2-40-I-TQJ SST89E58RD2-40-I-PIE SST89E58RD2-40-I-NJE SST89E58RD2-40-I-TQJE

FlashFlex51 MCU

Valid combinations for SST89V58RD2

SST89V58RD2-33-C-PI SST89V58RD2-33-C-NJ SST89V58RD2-33-C-TQJ SST89V58RD2-33-C-PIE SST89V58RD2-33-C-NJE SST89V58RD2-33-C-TQJE

SST89V58RD2-33-I-PI SST89V58RD2-33-I-NJ SST89V58RD2-33-I-TQJ SST89V58RD2-33-I-PIE SST89V58RD2-33-I-NJE SST89V58RD2-33-I-TQJE

Valid combinations for SST89E516RD2

SST89E516RD2-40-C-PI SST89E516RD2-40-C-NJ SST89E516RD2-40-C-TQJ SST89E516RD2-40-C-PIE SST89E516RD2-40-C-NJE SST89E516RD2-40-C-TQJE

SST89E516RD2-40-I-PI SST89E516RD2-40-I-NJ SST89E516RD2-40-I-TQJ SST89E516RD2-40-I-PIE SST89E516RD2-40-I-NJE SST89E516RD2-40-I-TQJE

Valid combinations for SST89V516RD2

SST89V516RD2-33-C-PI SST89V516RD2-33-C-NJ SST89V516RD2-33-C-TQJ SST89V516RD2-33-C-PIE SST89V516RD2-33-C-NJE SST89V516RD2-33-C-TQJE

SST89V516RD2-33-I-PI SST89V516RD2-33-I-NJ SST89V516RD2-33-I-TQJ SST89V516RD2-33-I-PIE SST89V516RD2-33-I-NJE SST89V516RD2-33-I-TQJE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Page 89

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

16.0 PACKAGING DIAGRAMS

Pin #1 Identifier

.065 .075

2.020

2.070

12˚

4 places

Preliminary Specifications

.600 .625

.530 .557

Base Plane

Seating Plane

.015 Min.

.063 .090

Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.045 .055

less

40-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST P

ACKAGE CODE: PI

.015 .022

stringent

.100 BSC

.100 † .200

.220 Max.

.008 .012

.600 BSC

40-pdip-PI-7

15˚

0˚

Page 90

Preliminary Specifications

TOP VIEW SIDE VIEW BOTTOM VIEW

Optional

Pin #1 Identifier

.042 .048

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

.685 .695 .646 .656

144

†

.020 R. MAX.

.042 .056

x45˚

.147 .158

.025 .045

.042 .048

.685 .695

†

.646 .656

.050 BSC.

Note: 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .650; SST min is

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.026 .032

.050 BSC.

less

44-LEAD PLASTI C LEAD CHIP CARRIER (PLCC) SST P

ACKAGE CODE: NJ

stringent

.165 .180

.100 .112

.013 .021

.500 REF.

.020 Min.

.590 .630

.026 .032

44-plcc-NJ-7

Page 91

FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2

Preliminary Specifications

Pin #1 Identifier

1.2

max.

Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±0.05) mm.

4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.

10.00 ± 0.10

12.00 ± 0.25

10.00 ± 0.10

12.00 ± 0.25

.30 .45

.80 BSC

.09 .20

.95

1.05 .05

.15

44-LEAD THIN QUAD FLAT PACK (TQFP) SST P

ACKAGE CODE: TQJ

.45 .75

1.00 ref

0˚- 7˚

44-tqfp-TQJ-7

1mm

TABL E 16-1: R

EVISION HISTORY

Number Description Date

• Initial Release

Mar 2004

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 940 86 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

Datasheet FSST89E52RD2, SST89E54RD2, SST89E58RD2, SST89E516RD2, SST89V52RD2 Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual