Datasheet SST49LF002A, SST49LF003A, SST49LF004A, SST49LF008A Datasheet (SST)

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

SST49LF002A / 003A / 004A / 008A2Mb / 3Mb / 4Mb / 8Mb Firmware Hub for Intel 8xx Chipsets

FEATURES:

Advance Information

• Firmware Hub for Intel 8xx Chipsets

• 2 Mbit, 3 Mbit, 4 Mbit, or 8 Mbit SuperFlash memory array for code/data storage

– SST49LF002A: 256K x8 (2 Mbit) – SST49LF003A: 384K x8 (3 Mbit) – SST49LF004A: 512K x8 (4 Mbit) – SST49LF008A: 1024K x8 (8 Mbit)

• Flexible Erase Capability

– Uniform 4 KByte Sectors – Uniform 16 KByte overlay blocks for

SST49LF002A

– Uniform 64 KByte overlay blocks for

SST49LF003A/004A/008A

– Top Boot Block protection

- 16 KByte for SST49LF002A

- 64 KByte for SST49LF003A/004A/008A

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance:100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical) – Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time:

SST49LF002A: 4 seconds (typical) SST49LF003A: 6 seconds (typical) SST49LF004A: 8 seconds (typical)

SST49LF008A: 15 seconds (typical) – Single-pulse Program or Erase – Internal timing generation

• Two Operational Modes

– Firmware Hub Interface (FWH) Mode for

in-system operation

– Parallel Programming (PP) Mode for fast

production programming

• Firmware Hub Hardware Interface Mode

– 5-signal communication interface supporting

byte Read and Write – 33 MHz clock frequency operation – WP# and TBL# pins provide hardware write

protect for entire chip and/or top Boot Block – Block Locking Register for all blocks – Standard SDP Command Set – Data# Polling and Toggle Bit for End-of-Write

detection – 5 GPI pins for system design flexibility – 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and

8-pin data I/O interface – Supports fast In-System or PROM programming

for manufacturing

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC – 32-lead TSOP (8mm x 14mm)

PRODUCT DESCRIPTION

The SST49LF00xA flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF00xA: Firmware Hub (FWH) Interface Mode for In-System programming and Parallel Programming (PP) Mode for fast factory programming of PC-BIOS applications.

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The SST49LF00xA flash memory devices are manufactured with SST’s proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF00xA devices significantly improve performance and reliability, while lowering power consumption. The SST49LF00xA devices write (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Intel is a registered trademark of Intel Corporation.

These specifications are subject to change without notice.

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF00xA products provide a maximum ByteProgram time of 20 µsec. The entire memory can be erased and programmed byte-by-byte typically in 15 seconds for an 8-Mbit device, when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles.

To protect against inadvertent write, the SST49LF00xA devices employ hardware and software data (SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

To meet high density, surface mount requirements, the SST49LF00xA device is offered in 32-lead TSOP and 32lead PLCC packages. See Figures 7 and 8 for pin assignments and Table 8 for pin descriptions.

Mode Selection and Description

The SST49LF00xA flash memory devices can operate in two distinct interface modes: the Firmware Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be configured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In FWH mode, the device is configured to interface with its host using Intel’s Firmware Hub proprietary protocol. Commu-

nication between Host and the SST49LF00xA occurs via the 4-bit I/O communication signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. See the Device Memory Maps in Figures 3 through 6 for address assignments.

FIRMWARE HUB (FWH) MODE

Device Operation

The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations of the SST49LF00xA. Operations such as Memory Read and Memory Write uses Intel FWH propriety protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only available in PP Mode.

The device enters standby mode when FWH4 is high and no internal operation is in progress. The device is in ready mode when FWH4 is low and no activity is on the FWH bus.

Firmware Hub Interface Cycles

Addresses and data are transferred to and from the SST49LF00xA by a series of “fields,” where each field contains 4 bits of data. ST49LF00xA supports only single-byte read and writes, and all fields are one clock cycle in length. Field sequences and contents are strictly defined for Read and Write operations. Addresses in this section refer to addresses as seen from the SST49LF00xA’s “point of view,” some calculation will be required to translate these to the actual locations in the memory map (and vice versa) if multiple memory device is used on the bus. Tables 1 and 2 list the field sequences for Read and Write cycles.

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

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TABLE 1: FWH READ CYCLE

Clock Cycle

1 START 1101 IN FWH4 must be active (low) for the part to respond. Only the

2 IDSEL 0000 to 1111 IN Indicates which FWH device should respond. If the to IDSEL (ID

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

10 IMSIZE 0000 (1 byte) IN A field of this size indicates how many bytes will be or trans-

11 TAR0 1111 IN

12 TAR1 1111 (float) Float

13 RSYNC 0000 (READY) OUT During this clock cycle, the FWH will generate a “ready-

14 DATA YYYY OUT YYYY is the least-significant nibble of the least-significant

15 DATA YYYY OUT YYYY is the most-significant nibble of the least-significant

16 TAR0 1111 OUT

17 TAR1 1111 (float) Float thenINThe master (Intel ICH) resumes control of the bus during

1. Field contents are valid on the rising edge of the present clock cycle.

Field

Name

Field Contents

FWH[3:0]

1

FWH[3:0] Direction Comments

last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate a FWH memory Read cycle.

select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle.

address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first.

ferred during multi-byte operations. The SST49LF00xA will only support single-byte operation. IMSIZE=0000b

In this clock cycle, the master (Intel ICH) has driven the bus

then Float

then float to all ‘1’s and then floats the bus, prior to the next clock cycle. This is the first part of the bus “turnaround cycle.”

The SST49LF00xA takes control of the bus during this

then OUT

cycle. During the next clock cycle, it will be driving “sync data.”

sync” (RSYNC) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle.

data byte.

In this clock cycle, the SST49LF00xA has driven the bus to

then Float

all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.”

this cycle.

T1.3 504

CLK

FWH4

FWH[3:0]

STR TAR RSYNCIMSIMADDRIDS DATA TAR

504 ILL F59.1

FIGURE 1: SINGLE-BYTE READ WAVEFORMS

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

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TABLE 2: FWH WRITE CYCLE

Clock Cycle

1 START 1110 IN FWH4 must be active (low) for the part to respond.

2 IDSEL 0000 to 1111 IN Indicates which SST49LF00xA device should

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

10 IMSIZE 0000 (1 byte) IN This size field indicates how many bytes will be

11 DATA YYYY IN This field is the least-significant nibble of the data byte.

12 DATA YYYY IN This field is the most-significant nibble of the data byte.

13 TAR0 1111 IN then Float In this clock cycle, the master (Intel ICH) has driven the

14 TAR1 1111 (float) Float then OUT The SST49LF00xA takes control of the bus during this

15 RSYNC 0000 OUT The SST49LF00xA outputs the values 0000, indicat-

16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF00xA has driven the

17 TAR1 1111 (float) Float then IN The master (Intel ICH) resumes control of the bus during

1. Field contents are valid on the rising edge of the present clock cycle.

Field

Name

Field Contents

FWH[3:0]

1

FWH[3:0] Direction Comments

Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate a FWH memory Read cycle.

respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle.

address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first.

transferred during multi-byte operations. The FWH only supports single-byte writes. IMSIZE=0000b

This data is either the data to be programmed into the flash memory or any valid flash command.

then float bus to all ‘1’s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.”

cycle. During the next clock cycle it will be driving the “sync” data.

ing that it has received data or a flash command.

bus to all then float ‘1’s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.”

this cycle.

T2.4 504

CLK

FWH4

FWH[3:0]

STR DATA TA RTA R

IMSIMADDRIDS

RSYNC

504 ILL F60.1

FIGURE 2: WRITE WAVEFORMS

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

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Abort Mechanism

If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’ (ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the data may be incorrectly altered.

Response To Invalid Fields

During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows:

Address out of range: The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by SST49LF00xA.

Address A writes to the flash core (A

=0).

(A

22

has the special function of directing reads and

22

=1) or to the register space

22

The SST49LF003A features are equivalent to the SST49LF004A with 128 KByte less memory. For the SST49LF003A, operations beyond the 3-Mbit boundary (below 20000H) are not valid (see Device Memory Map).

Invalid IMSIZE field: If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no operation will be attempted. The SST49LF00xA will not generate any kind of response in this situation. Invalidsize fields for a Read/Write cycle are anything but 0000b.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF00xA. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest flash memory address range for the SST49LF003A/ 004A/008A and 4 boot sectors (16 KByte) for SST49LF002A. WP# pin write protects the remaining sectors in the flash memory.

WP# pin during a Program or Erase operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.

TBL# is internally ORed with the top Boot Block Locking register. When TBL# is low, the top Boot Block is hardware write protected regardless of the state of the WriteLock bit for the Boot Block Locking register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional effect, even though the register may indicate that the block is no longer locked.

WP# is internally ORed with the Block Locking register. When WP# is low, the blocks are hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking registers. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even though the register may indicate that the block is no longer locked.

Reset

A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization.

During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time T reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 18, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation.

RSTP.

A

An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot Block Locking register. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another.

Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or

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SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Write Operation Status Detection

The SST49LF00xA device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling

) and Toggle Bit (DQ6). The End-of-Write detection

(DQ

7

mode is incorporated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either

or DQ6. In order to prevent spurious rejection, if an

DQ

7

erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF00xA device is in the internal Program operation, any attempt to read DQ

will produce the com-

7

plement of the true data. Once the Program operation is completed, DQ though DQ

will produce true data. Note that even

7

may have valid data immediately following the

7

completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ internal Erase operation is completed, DQ

will produce a ‘0’. Once the

7

will produce a

7

‘1’. Proper status will not be given using Data# Polling if the address is in the invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ

will produce alternating

6

‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop.

Multiple Device Selection

The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the SST49LF00xA is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). The SST49LF00xA will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. For further information regarding FWH device mapping and paging, please refer to the Intel 82801(ICH) I/O

Controller Hub documentation. Since there is no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recommended.

REGISTERS

There are three types of registers available on the SST49LF00xA, the General Purpose Inputs Register, Block Locking Registers, and the JEDEC ID Registers. These registers appear at their respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt to read or write any register during an internal Write operation will be ignored.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on the SST49LF00xA. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register for the boot device appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. See Table 3 for the GPI_REG bits and function.

TABLE 3: G

Bit Function

7:5 Reserved - -

4 FGPI[4]

Reads status of general purpose input pin

3 FGPI[3]

Reads status of general purpose input pin

2 FGPI[2]

Reads status of general purpose input pin

1 FGPI[1]

Reads status of general purpose input pin

0 FGPI[0]

Reads status of general purpose input pin

ENERAL PURPOSE INPUTS REGISTER

Pin #

32-PLCC 32-TSOP

30 6

311

412

513

614

T3.2 504

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

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Block Locking Registers

SST49LF00xA provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 4 and Table 5. Unused register locations will read as 00H.

TABLE 4: B

Register Block Size

T_BLOCK_LK 16K 3FFFFH - 3C000H FFBF8002H

T_MINUS01_LK 16K

T_MINUS02_LK 16K

T_MINUS03_LK 16K

T_MINUS04_LK 16K

T_MINUS05_LK 16K

T_MINUS06_LK 16K

T_MINUS07_LK 16K

1. Default value at power up is 01H

LOCK LOCKING REGISTERS FOR SST49LF002A

16K 16K

16K

TABLE 5: BLOCK LOCKING REGISTERS FOR SST49LF003A/004A/008A

Block

Register

T_BLOCK_LK 64K 07FFFFH - 070000H 07FFFFH - 070000H 0FFFFFH - 0F0000H FFBF0002H

T_MINUS01_LK 64K 06FFFFH - 060000H 06FFFFH - 060000H 0EFFFFH - 0E0000H FFBE0002H

T_MINUS02_LK 64K 05FFFFH - 050000H 05FFFFH - 050000H 0DFFFFH - 0D0000H FFBD0002H

T_MINUS03_LK 64K 04FFFFH - 040000H 04FFFFH - 040000H 0CFFFFH - 0C0000H FFBC0002H

T_MINUS04_LK 64K 03FFFFH - 030000H 03FFFFH - 030000H 0BFFFFH - 0B0000H FFBB0002H

T_MINUS05_LK 64K 02FFFFH - 020000H 02FFFFH - 020000H 0AFFFFH - 0A0000H FFBA0002H

T_MINUS06_LK 64K

T_MINUS07_LK 64K 00FFFFH - 000000H 08FFFFH - 080000H FFB80002H

T_MINUS08_LK 64K

T_MINUS09_LK 64K 06FFFFH - 060000H FFB60002H

T_MINUS10_LK 64K 05FFFFH - 050000H FFB50002H

T_MINUS11_LK 64K 04FFFFH - 040000H FFB40002H

T_MINUS12_LK 64K 03FFFFH - 030000H FFB30002H

T_MINUS13_LK 64K 02FFFFH - 020000H FFB20002H

T_MINUS14_LK 64K 01FFFFH -010000H FFB10002H

T_MINUS15_LK 64K 00FFFFH - 000000H FFB00002H

1. Default value at power up is 01H

Size

Protected Memory Address Range

01FFFFH - 010000H 09FFFFH - 090000H FFB90002H

1

Protected Memory

Address Package

3BFFFH - 38000H

37FFFH - 34000H 33FFFH - 30000H

2FFFFH - 2C000H 2BFFFH - 28000H

27FFFH - 24000H 23FFFH - 20000H

1FFFFH - 1C000H 1BFFFH - 18000H

17FFFH - 14000H 13FFFH - 10000H

0FFFFH - 0C000H 0BFFFH - 08000H

07FFFH - 04000H 03FFFH - 00000H

1

07FFFFH - 070000H FFB70002H

Memory Map

Register Address

FFBF0002H

FFBE8002H

FFBE0002H

FFBD8002H

FFBD0002H

FFBC8002H

FFBC0002H

Memory Map

Register AddressSST49LF003A SST49LF004A SST49LF008A

T4.1 504

T5.2 504

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TABLE 6: B

Reserved Bit [7..2] Lock-Down Bit [1] Write-Lock Bit [0] Lock Status

Write Lock

The Write-Lock bit, bit 0, controls the lock state described in Table 6. The default Write status of all blocks after powerup is write locked. When bit 0 of the Block Locking register is set, Program and Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is sampled at the beginning of the operation.

The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking register does not indicate the state of the TBL# pin.

The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is low, it overrides the software locking scheme. The Block Locking register does not indicate the state of the WP# pin.

LOCK LOCKING REGISTER BITS

000000 0 0 Full Access 000000 0 1 Write Locked (Default State at Power-Up) 000000 1 0 Locked Open (Full Access Locked Down) 000000 1 1 Write Locked Down

PARALLEL PROGRAMMING MODE

Device Operation

Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#.

Read

The Read operation of the SST49LF00xA device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 14, for further details.

Reset

A VIL on RST# pin initiates a device reset.

T6.3 504

Lock Down

The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 6. When in the FWH interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock Down status of a particular block can be determined by reading the corresponding Lock-Down bit. Once a block’s Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and the block is locked down in its current state of write accessibility.

JEDEC ID Registers

The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. Unused register location will read as 00H. Refer to the relevant application note for details. See Table 7 for the device ID code.

Byte-Program Operation

The SST49LF00xA device is programmed on a byte-bybyte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A and the column Address (A edge of R/C#. The data bus is latched in the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 µs. See Figure 15 for Program operation timing diagram, Figure 18 for timing waveforms, and Figure 26 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.

) is latched on the falling edge of R/C#

10-A0

) is latched on the rising

21-A11

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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

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Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 19 for Sector-Erase timing waveforms. Any commands written during the Sector-Erase operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the SST49LF003A/SST49LF004A/SST49LF008A and 16 KByte uniform block size for the SST49LF002A. The BlockErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 20 for timing waveforms. Any commands written during the BlockErase operation will be ignored.

Chip-Erase

The SST49LF00xA device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with ChipErase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 10 for the command sequence, Figure 21 for timing diagram, and Figure 29 for the flowchart. Any commands written during the Chip-Erase operation will be ignored.

Write Operation Status Detection

The SST49LF00xA device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling

) and Toggle Bit (DQ6). The End-of-Write detection

(DQ

7

mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ

or DQ6. In order to prevent spurious rejection, if an

7

erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF00xA device is in the internal Program operation, any attempt to read DQ

will produce the com-

7

plement of the true data. Once the Program operation is completed, DQ though DQ

will produce true data. Note that even

7

may have valid data immediately following the

7

completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ Erase operation is completed, DQ

will produce a ‘0’. Once the internal

7

will produce a ‘1’. The

7

Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figure 16 for Data# Polling timing diagram and Figure 27 for a flowchart. Proper status will not be given using Data# Polling if the address is in the invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 17 for Toggle Bit timing diagram and Figure 27 for a flowchart.

will produce alternating

6

9

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Data Protection

The SST49LF00xA device provides both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V

Write Inhibit Mode:

is less than 1.5V.

DD

Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST49LF00xA provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequences. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF00xA device is shipped with the Software Data Protection permanently enabled. See Table 10 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within T

RC.

Electrical Specifications

The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 11 for the DC voltage and current specifications. Refer to the tables on pages 19 through 23 for the AC timing specifications for Clock, Read/Write, and Reset operations.

Product Identification

The product identification mode identifies the device as the SST49LF00xA and manufacturer as SST.

TABLE 7: P

Manufacturer’s ID 0000H BFH FFBC0000H

Device ID

SST49LF002A 0001H 57H FFBC0001H

SST49LF003A 0001H 1BH FFBC0001H

SST49LF004A 0001H 60H FFBC0001H

SST49LF008A 0001H 5AH FFBC0001H

RODUCT IDENTIFICATION

Byte Data

JEDEC ID

Address

Location

T7.5 504

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between V than 1 cm away from the V

pin of the device. Additionally, a

DD

low frequency 4.7 µF electrolytic capacitor from V should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket.

The RST# pin must remain stable at V

IH

tion of an Erase operation. WP# must remain stable at V the entire duration of the Erase and Program operations for non-Boot Block sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at V entire duration of the Erase and Program operations.

and VSS less

DD

to V

DD

SS

for the entire dura-

for

IH

for the

IH

10

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

System Memory

(Top 4 MByte)

FFFFFFFFH

SST49LF002A

(2 Mbit)

FFFC0000H

FFFA0000H

FFF80000H

FFF00000H

SST49LF003A

(3 Mbit)

SST49LF004A

(4 Mbit)

SST49LF008A

(8 Mbit)

Advance Information

FFC00000H

BOOT-CONFIGURATION SYSTEM MEMORY MAP

FUNCTIONAL BLOCK DIAGRAM

TBL#

WP#

INIT#

FWH[3:0]

CLK

FWH4

ID[3:0]

FGPI[4:0]

R/C#

A[10:0]

DQ[7:0]

OE#

WE#

FWH

Interface

Programmer

Interface

Address Buffers & Latches

Range for

Additional FWH Devices

X-Decoder

Control Logic

RST#

IC

504 ILL B1A.3

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

504 ILL B1.2

11

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

TBL#

Block 15

3C000H

3BFFFH

Block 14

38000H

37FFFH

Block 13

34000H

33FFFH

Block 12

30000H

2FFFFH

Block 11

2C000H

3FFFFH

Block 10

2BFFFH

28000H

Block 9

27FFFH

24000H

23FFFH

Block 8

WP# for

Block 0~14

20000H

1FFFFH

Block 7

1C000H

1BFFFH

Block 6

18000H

17FFFH

Block 5

14000H

13FFFH

Block 4

10000H

0FFFFH

Block 3

0C000H

0BFFFH

Block 2

08000H

07FFFH

Block 1

04000H

03FFFH

300000

Block 0 (16 KByte)

02FFFH

02000H

01FFFH

01000H

00FFFH

00000H

FIGURE 3: DEVICE MEMORY MAP FOR SST49LF002A

Boot Block

4 KByte Sector 3

4 KByte Sector 2

4 KByte Sector 1

4 KByte Sector 0

504 ILL F52.7

12

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

7FFFFH

TBL#

Block 7

70000H

6FFFFH

Block 6

60000H

5FFFFH

Block 5

50000H

WP# for

Block 2~6

Block 4

4FFFFH

40000H

3FFFFH

Block 3

30000H 2F000H

Block 2

22000H 21000H 20000H

*Block 1

1FFFFH

10000H

*Block 0

(64 KByte)

* operations to shaded area are not valid.

0FFFFH

00000H

FIGURE 4: DEVICE MEMORY MAP FOR SST49LF003A

Boot Block

4 KByte Sector 47

4 KByte Sector 34

4 KByte Sector 33

4 KByte Sector 32

Invalid Range

504 ILL F56.1

WP# for

Block 0~6

FIGURE 5: D

TBL#

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

(64 KByte)

EVICE MEMORY MAP FOR SST49LF004A

7FFFFH

70000H

6FFFFH

60000H

5FFFFH

50000H

4FFFFH

40000H

3FFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H 0F000H

02000H 01000H 00000H

Boot Block

4 KByte Sector 2

4 KByte Sector 1 4 KByte Sector 0

504 ILL F45.5

13

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

TBL#

WP# for

Block 0~14

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

Boot Block

4 KByte Sector 15

Block 0 (64 KByte)

002000H

001000H

000000H

4 KByte Sector 2

4 KByte Sector 1

4 KByte Sector 0

504 ILL F57.0

FIGURE 6: DEVICE MEMORY MAP FOR SST49LF008A

14

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

NC NC NC

V

(VSS)

SS

IC (IC)

A10 (FGPI4)

R/C# (CLK) V

(VDD)

DD

NC

RST# (RST#)

A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Standard Pinout

Top View

Die Up

( ) Designates FWH Mode

FIGURE 7: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

)

DD

(V

DD

A7(FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

A3 (ID3)

A2 (ID2)

A1 (ID1)

A0 (ID0)

DQ0 (FWH0)

A8 (FGPI2)

A9 (FGPI3)

RST# (RST#)NCV

4 3 2 1 32 31 30

5

6

7

8

32-lead PLCC

9

10

Top View

11

12

13

14 15 16 17 18 19 20

504 ILL F01.4

R/C# (CLK)

A10 (FGPI4)

29

28

27

26

25

24

23

22

21

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

IC (IC)

VSS (VSS)

NC

V

DD (VDD

OE# (INIT#)

WE# (FWH4) NC

DQ7 (RES)

OE# (INIT#) WE# (FWH4) V

(VDD)

DD

DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (FWH3) V

(VSS)

SS

DQ2 (FWH2) DQ1 (FWH1) DQ0 (FWH0) A0 (ID0) A1 (ID1) A2 (ID2) A3 (ID3)

)

SS

(V

SS

V

DQ4 (RES)

( ) Designates FWH Mode

FIGURE 8: P

IN ASSIGNMENTS FOR 32-LEAD PLCC

DQ1 (FWH1)

DQ2 (FWH2)

DQ5 (RES)

DQ3 (FWH3)

504 ILL F02.3

DQ6 (RES)

15

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

TABLE 8: PIN DESCRIPTION

Interface

Symbol Pin Name Type

A

10-A0

DQ

7

Address I X Inputs for low-order addresses during Read and Write operations.

-DQ0Data I/O X To output data during Read cycles and receive input data during

OE# Output Enable I X To gate the data output buffers

WE# Write Enable I X To control the Write operations

IC Interface

Configuration Pin

INIT# Initialize I X This is the second reset pin for in-system use. This pin is internally

ID[3:0] Identification Inputs I X These four pins are part of the mechanism that allows multiple parts

FGPI[4:0] General Purpose Inputs I X These individual inputs can be used for additional board flexibility.

TBL# Top Block Lock I X When low, prevents programming to the Boot Block sectors at top of

FWH[3:0] FWH I/Os I/O X I/O Communications

CLK Clock I X To provide a clock input to the control unit

FWH4 FWH Input I X Input Communications

RST# Reset I X X To reset the operation of the device

WP# Write Protect I X When low, prevents programming to all but the highest addressable

R/C# Row/Column Select I X Select For the Programming interface, this pin determines whether

RES Reserved X These pins must be left unconnected.

V

DD

V

SS

Power Supply PWR X X To provide power supply (3.0-3.6V)

Ground PWR X X Circuit ground (OV reference) All VSS pins must be grounded.

NC No Connection I X X Unconnected pins

1. I = Input, O = Output

1

FunctionsPP FWH

Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs.

Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high.

I X X This pin determines which interface is operational. When held high,

programmer mode is enabled and when held low, FWH mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled- down with a resistor between 20-100 KΩ.

combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited.

to be attached to the same bus. The strapping of these pins is used to identify the component.The boot device must have ID[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 KΩ.

The state of these pins can be read through GPI_REG register. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated.

memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected.

blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected.

the address pins are pointing to the row addresses, or to the column addresses.

T8.4 504

16

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

TABLE 9: OPERATION MODES SELECTION (PP MODE)

Mode RST# OE# WE# DQ Address

Read Program V Erase V

Reset V

Write Inhibit

V

IH

IL

V

IH

XX

Product Identification

1. X can be VIL or VIH, but no other value.

2. Device ID 57H for SST49LF002A, 1BH for SST49LF003A, 60H for SST49LF004A, and 5AH for SST49LF008A

V

IH

TABLE 10: SOFTWARE COMMAND SEQUENCE

1

1st

Command Sequence

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA

Chip-Erase

Software ID Entry

Software ID Exit

1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to complete a

2. Address format A14-A0 (Hex), Addresses A21-A15 can be VIL or VIH, but no other value, for the Command sequence in PP Mode.

3. BA = Program Byte address

4. SAX for Sector-Erase Address

5. BAX for Block-Erase Address

6. Chip-Erase is supported in PP Mode only

7. SST Manufacturer’s ID = BFH, is read with A0=0,

8. The device does not remain in Software Product ID mode if powered down.

9. Both Software ID Exit operations are equivalent

6

7,8

9

command sequence.

With A With A With A With A

= 0; 49LF002A Device ID = 57H, is read with A0 = 1.

17-A1

= 0; 49LF003A Device ID = 1BH, is read with A0 = 1.

18-A1

= 0; 49LF004A Device ID = 60H, is read with A0 = 1.

18-A1

= 0; 49LF008A Device ID = 5AH, is read with A0 = 1.

19-A1

Write Cycle

2

Addr

Data Addr2Data Addr2Data Addr2Data Addr2Data Addr2Data

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

5555H AAH 2AAAH 55H 5555H 90H

XXH F0H

5555H AAH 2AAAH 55H 5555H F0H

V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

D

OUT

D

IN

1

X

A

IN

A

IN

Sector or Block address, XXH for Chip-Erase

XXHigh Z X

V

IL

V

IL

1

2nd

Write Cycle

XHigh Z/D

V

IH

V

IH

High Z/D

Manufacturer’s ID (BFH) Device ID

1

3rd

Write Cycle

OUT

2

4th

Write Cycle

3

1

Data

X

A18-A1=VIL, A0=V A18-A1=VIL, A0=VIH

1

5th

Write Cycle

IL

X

6th

4

5

T9.5 504

1

30H

50H

T10.5 504

17

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to

1

Transient Voltage (<20 ns) on Any Pin to Ground Potential

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

2

Output Short Circuit Current

1. Do not violate processor or chipset limitations on the INIT# pin.

2. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI outputs.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

V

+0.5V

DD

OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +85°C 3.0-3.6V

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

See Figures 24 and 25

1. FWH interface signals use PCI load test conditions

TABLE 11: DC OPERATING CHARACTERISTICS (ALL INTERFACES)

Limits

Symbol Parameter

I

DD

Active VDD Current Address input=VIL/VIH, at F=1/TRC Min,

Read 12 mA OE#=

2

Write

I

SB

Standby VDD Current (FWH Interface)

3

I

RY

Ready Mode VDD Current (FWH Interface)

I

Input Current for IC, ID [3:0] pins

I

LI

I

LO

4

V

IHI

4

V

ILI

V

IL

V

IH

V

OL

V

OH

1. Test conditions apply to PP mode.

2. IDD active while Erase or Program is in progress.

3. The device is in Ready Mode when no activity is on the FWH bus.

4. Do not violate processor or chipset specification regarding INIT# voltage.

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

Output Leakage Current 1 µA V

INIT# Input High Voltage 1.0 VDD+0.5 V VDD=VDD Max

INIT# Input Low Voltage -0.5 0.4 V VDD=VDD Min

Input Low Voltage -0.5 0.3 V

Input High Voltage 0.5 V

Output Low Voltage 0.1 V

Output High Voltage 0.9 V

Min Max Units

24 mA OE#=VIH, VDD=VDD Max (PP Mode)

100 µA FWH4=0.9VDD, f=33 MHz VDD=VDD Max, All

10 mA FWH4=VIL, f=33 MHz VDD=VDD Max

200 µA VIN=GND to VDD, VDD=VDD Max

DD

VDD+0.5 V VDD=VDD Max

DD

VVDD=VDD Min

VIOL=1500µA, VDD=VDD Min

VIOH=-500 µA, VDD=VDD Min

1

Test Conditions

V

DD=VDD

Max (PP Mode)

V

, WE#=V

IH

other inputs ≥ 0.9 V

1

IH

DD

All other inputs ≥ 0.9 V

=GND to VDD, VDD=VDD Max

OUT

or ≤ 0.1 V

DD

= 30 pF

L

DD

T11.9 504

18

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

1

T

PU-READ

T

PU-WRITE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter

Power-up to Read Operation 100 µs

1

Power-up to Write Operation 100 µs

T12.2 504

TABLE 13: PIN IMPEDANCE (V

=3.3V, Ta=25 °C, f=1 Mhz, other pins open)

DD

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

2

L

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. Refer to PCI spec.

I/O Pin Capacitance V

Input Capacitance V

= 0V 12 pF

I/O

= 0V 12 pF

IN

Pin Inductance 20 nH

T13.4 504

TABLE 14: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LT H

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

DD

mA JEDEC Standard 78

T14.3 504

TABLE 15: CLOCK TIMING PARAMETERS

Symbol Parameter Min Max Units

T

CYC

T

HIGH

T

LOW

- CLK Slew Rate (peak-to-peak) 1 4 V/ns

- RST# or INIT# Slew Rate 50 mV/ns

CLK Cycle Time 30 ns

CLK High Time 11 ns

CLK Low Time 11 ns

T15.1 504

T

cyc

T

high

0.6 V

0.4 V

0.3 V

0.5 V

DD

T

low

0.2 V

DD

0.4 V

DD

(minimum)

504 ILL F27.0

p-to-p

FIGURE 9: CLK WAVEFORM

19

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

AC CHARACTERISTICS (FWH MODE)

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

TABLE 16: READ/WRITE CYCLE TIMING PARAMETERS (FWH MODE), V

=3.0-3.6V

DD

Symbol Parameter Min Max Units

T

CYC

T

SU

T

DH

1

T

VAL

T

BP

T

SE

T

BE

T

SCE

T

ON

T

OFF

1. Minimum and maximum times have different loads. See PCI spec.

Clock Cycle Time 30 ns

Data Set Up Time to Clock Rising 7 ns

Clock Rising to Data Hold Time 0 ns

Clock Rising to Data Valid 2 11 ns

Byte Programming Time 20 µs

Sector-Erase Time 25 ms

Block-Erase Time 25 ms

Chip-Erase Time 100 ms

Clock Rising to Active (Float to Active Delay) 2 ns

Clock Rising to Inactive (Active to Float Delay) 28 ns

TABLE 17: AC INPUT/OUTPUT SPECIFICATIONS (FWH MODE)

Symbol Parameter Min Max Units Conditions

IOH(AC) Switching Current High -12 V

-17.1(VDD-V

(Test Point) -32 V

IOL(AC) Switching Current Low 16 V

26.7 V

(Test Point) 38 V

I

CL

I

CH

2

slewr

2

slewf

1. See PCI spec.

2. PCI specification output load is used.

Low Clamp Current -25+(VIN+1)/0.015 mA -3 < VIN ≤ -1

High Clamp Current 25+(VIN-VDD-1)/0.015 mA VDD+4 > VIN ≤ VDD+1

Output Rise Slew Rate 1 4 V/ns 0.2VDD-0.6VDD load

Output Fall Slew Rate 1 4 V/ns 0.6VDD-0.2VDD load

DD

OUT

)

Equation C

DD

Equation D

DD

mAmA0 < V

1

mA V

1

mAmAVDD >V

mA V

≤ 0.3V

OUT

0.3VDD < V

0.7VDD < V

=0.7V

OUT

0.6VDD > V

0.18VDD > V

=0.18V

OUT

< 0.9V

OUT

<V

OUT

DD

≥0.6V

> 0.1V

OUT

DD

> 0

T16.3 504

DD

T17.3 504

TABLE 18: RESET TIMING PARAMETERS, V

=3.0-3.6V (FWH MODE)

DD

Symbol Parameter Min Max Units

T

PRST

T

KRST

T

RSTP

T

RSTF

1

T

RST

T

RSTE

1. There will be a latency of T

VDD stable to Reset Low 1 ms

Clock Stable to Reset Low 100 µs

RST# Pulse Width 100 ns

RST# Low to Output Float 48 ns

RST# High to FWH4 Low 1 µs

RST# Low to reset during Sector-/Block-Erase or Program 10 µs

if a reset procedure is performed during a Program or Erase operation.

RSTE

T18.5 504

20

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

V

DD

CLK

RST#/INIT#

FWH[3:0]

FWH4

FIGURE 10: RESET TIMING DIAGRAM

T

PRST

T

KRST

T

RSTF

T

RSTP

T

RSTE

T

RST

Sector-/Block-Erase

or Program operation

aborted

504 ILL F51.1

CLK

FWH [3:0]

(Valid Output Data)

FWH [3:0]

(Float Output Data)

FIGURE 11: OUTPUT TIMING PARAMETERS

V

TEST

V

TH

V

TL

T

VAL

T

ON

T

OFF

504 ILL F49.1

21

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

V

TH

CLK

T

SU

V

TEST

V

TL

T

DH

FWH [3:0]

(Valid Input Data)

Inputs

Valid

V

MAX

504 ILL F50.1

FIGURE 12: INPUT TIMING PARAMETERS

TABLE 19: INTERFACE MEASUREMENT CONDITION PARAMETERS

Symbol Value Units

1

V

TH

1

V

TL

V

TEST

1

V

MAX

Input Signal Edge Rate 1 V/ns

1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. V may use different voltage values, but must correlate results back to these parameters.

specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing

MAX

0.6 V

0.2 V

0.4 V

DD

V

T19.3 504

22

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

AC CHARACTERISTICS (PP MODE)

Advance Information

TABLE 20: READ CYCLE TIMING PARAMETERS V

=3.0-3.6V (PP MODE)

DD

Symbol Parameter Min Max Units

T

RC

T

RST

T

AS

T

AH

T

AA

T

OE

T

OLZ

T

OHZ

T

OH

TABLE 21: PROGRAM/ERASE CYCLE TIMING PARAMETERS V

Read Cycle Time 270 ns

RST# High to Row Address Setup 1 µs

R/C# Address Set-up Time 45 ns

R/C# Address Hold Time 45 ns

Address Access Time 120 ns

Output Enable Access Time 60 ns

OE# Low to Active Output 0 ns

OE# High to High-Z Output 35 ns

Output Hold from Address Change 0 ns

=3.0-3.6V (PP MODE)

DD

Symbol Parameter Min Max Units

T

RST

AS

AH

CWH

OES

OEH

OEP

OET

WP

WPH

DS

DH

IDA

BP

SE

BE

SCE

RST# High to Row Address Setup 1 µs

R/C# Address Setup Time 50 ns

R/C# Address Hold Time 50 ns

R/C# to Write Enable High Time 50 ns

OE# High Setup Time 20 ns

OE# High Hold Time 20 ns

OE# to Data# Polling Delay 40 ns

OE# to Toggle Bit Delay 40 ns

WE# Pulse Width 100 ns

WE# Pulse Width High 100 ns

Data Setup Time 50 ns

Data Hold Time 5 ns

Software ID Access and Exit Time 150 ns

Byte Programming Time 20 µs

Sector-Erase Time 25 ms

Block-Erase Time 25 ms

Chip-Erase Time 100 ms

T20.2 504

T21.2 504

TABLE 22: RESET TIMING PARAMETERS, V

=3.0-3.6V (PP MODE)

DD

Symbol Parameter Min Max Units

T

PRST

T

RSTP

T

RSTF

1

T

RST

T

RSTE

T

RSTC

1. There will be a reset latency of T

VDD stable to Reset Low 1 ms

RST# Pulse Width 100 ns

RST# Low to Output Float 48 ns

RST# High to Row Address Setup 1 µs

RST# Low to reset during Sector-/Block-Erase or Program 10 µs

RST# Low to reset during Chip-Erase 50 µs

RSTE

or T

if a reset procedure is performed during a Program or Erase operation.

RSTC

T22.1 504

23

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

V

DD

Addresses

R/C#

RST#

DQ

7-0

FIGURE 13: RESET TIMING DIAGRAM

T

PRST

T

RSTF

T

RSTP

T

RSTC

RSTE

T

RST

Row Address

Sector-/Block-Erase

or Program operation

aborted

Chip-Erase

aborted

504 ILL F58.0

T

RST#

Addresses

RSTP

T

RST

T

ASTAH

T

RC

Row AddressColumn AddressRow Address

T

AS

AH

Column Address

R/C#

V

IH

High-Z

T

OLZ

T

AA

T

OH

T

OE

T

OHZ

Data Valid

High-Z

504 ILL F28.2

DQ

WE#

OE#

7-0

FIGURE 14: READ CYCLE TIMING DIAGRAM (PP MODE)

24

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

T

RSTP

T

RST#

RST

Advance Information

Addresses

T

AS

T

AH

Column AddressRow Address

T

AS

R/C#

OE#

T

OES

WE#

DQ

7-0

FIGURE 15: WRITE CYCLE TIMING DIAGRAM (PP MODE)

T

AH

T

CWH

T

WP

T

DS

Data Valid

T

OEH

T

WPH

T

DH

504 ILL F29.2

Addresses

Row Column

R/C#

WE#

OE#

T

OEP

DQ

7

FIGURE 16: D

ATA# POLLING TIMING DIAGRAM (PP MODE)

D#D D# D

504 ILL F54.2

25

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

6

Row Column

T

OET

D D

Addresses

R/C#

WE#

OE#

DQ

FIGURE 17: TOGGLE BIT TIMING DIAGRAM (PP MODE)

504 ILL F55.0

Addresses

DQ

FIGURE 18: B

Four-Byte Code for Byte-Program

5555 2AAA 5555 BA

R/C#

OE#

T

WP

WE#

SB0

T

WPH

SB1 SB2 SB3

7-0

BA = Byte-Program Address

YTE-PROGRAM TIMING DIAGRAM (PP MODE)

Internal Program Starts

Data55AA A0

T

BP

504 ILL F53.0

26

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Six-Byte code for

Sector-Erase Operation

Addresses

DQ

R/C#

OE#

WE#

7-0

5555 2AAA 5555 5555 2AAA SA

T

WP

T

WPH

SB0

SAx = Sector Address

SB1 SB2 SB3 SB4 SB5

55AA55AA 80 30

x

Internal Erasure Starts

Advance Information

T

SE

504 ILL F32.1

FIGURE 19: SECTOR-ERASE TIMING DIAGRAM (PP MODE)

Six-Byte code for

Block-Erase Operation

Addresses

5555 2AAA 5555 5555 2AAA BA

R/C#

OE#

T

WP

T

WPH

SB0

BAx = Block Address

SB1 SB2 SB3 SB4 SB5

DQ

WE#

7-0

x

55AA55AA 80 50

T

BE

Internal Erasure Starts

504 ILL F48.1

FIGURE 20: B

LOCK-ERASE TIMING DIAGRAM (PP MODE)

27

Advance Information

Addresses

R/C#

OE#

WE#

DQ

7-0

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Six-Byte code for Chip-Erase Operation

5555 2AAA 5555 5555 2AAA 5555

T

WP

T

WPH

SB0 SB1 SB2 SB3 SB4 SB5

55AA55AA 80 10

T

SCE

Internal Erasure Starts

504 ILL F33.1

FIGURE 21: CHIP-ERASE TIMING DIAGRAM (PP MODE)

Three-byte sequence for

Software ID Entry

Addresses

5555 2AAA 5555 0000 0001

R/C#

OE#

T

IDA

DQ

WE#

7-0

T

WP

T

WPH

55AA 90

SW0

SW1 SW2

Device ID = 57H for SST49LF002A, 1BH for SST49LF003A,

60H for SST49LF004A, 5AH for SST49LF008A

T

BF

AA

Device ID

504 ILL F34.5

FIGURE 22: S

OFTWARE ID ENTRY AND READ (PP MODE)

28

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Three-Byte Sequence for

Software ID Exit and Reset

Addresses

2AAA 5555

T

WP

T

WPH

SW0 SW1 SW2

AA 55 F0

T

IDA

DQ

5555

R/C#

OE#

WE#

7-0

Advance Information

504 ILL F35.2

FIGURE 23: SOFTWARE ID EXIT AND RESET (PP MODE)

V

IHT

V

ILT

AC test inputs are driven at V for inputs and outputs are V

FIGURE 24: AC I

NPUT/OUTPUT REFERENCE WAVEFORMS (PP MODE)

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

V

OT

504 ILL F06.1

(0.1 VDD) for a logic “0”. Measurement reference points

ILT

Note: V

- V

INPUT

OUTPUT

INPUT

Tes t

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

TO DUT

C

L

504 ILL F07.0

FIGURE 25: A T

EST LOAD EXAMPLE (PP MODE)

29

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Start

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: A0H

Address: 5555H

FIGURE 26: BYTE-PROGRAM ALGORITHM

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

504 ILL F36.1

30

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

Internal Timer

Byte-

Program/Erase

Initiated

Wait TBP,

T

SCE, TBE

or TSE

Program/Erase

Completed

Program/Erase

No

Toggle Bit

Byte-

Initiated

Read byte

Read same

byte

Does DQ

match?

Ye s

Data# Polling

Byte-

Program/Erase

Initiated

No

Read DQ

Is DQ7 =

7

true data?

Ye s

6

Program/Erase

Completed

FIGURE 27: WAIT OPTIONS

Program/Erase

Completed

504 ILL F37.0

31

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Software Product ID Entry

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 90H

Address: 5555H

Wait T

IDA

Read Software ID

Software Product ID Exit &

Reset Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: F0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Write data: F0H

Address: XXH

Wait T

IDA

Return to normal

operation

504 ILL F38.1

FIGURE 28: SOFTWARE PRODUCT COMMAND FLOWCHARTS

32

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

Chip-Erase

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Block-Erase

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Sector-Erase

Command Sequence

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

Wait Options

Chip erased

to FFH

Write data: 50H

Address: BA

X

Wait Options

Block erased

to FFH

Write data: 30H

Address: SA

X

Wait Options

Sector erased

to FFH

504 ILL F39.1

FIGURE 29: ERASE COMMAND SEQUENCE

33

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Advance Information

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49L

F00xA -XXX -XX -XX

Package Modifier

H = 32 leads

Package Type

N = PLCC W = TSOP (type 1, die up, 8mm x 14mm)

Operating Temperature

C = Commercial = 0°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Serial Access Clock Frequency

33 = 33 MHz

Version

Device Density

008 = 8 Mbit 004 = 4 Mbit 003 = 3 Mbit 002 = 2 Mbit

Voltage Range

L = 3.0-3.6V

Valid combinations for SST49LF002A

SST49LF002A-33-4C-WH SST49LF002A-33-4C-NH

Valid combinations for SST49LF003A

SST49LF003A-33-4C-WH SST49LF003A-33-4C-NH

Valid combinations for SST49LF004A

SST49LF004A-33-4C-WH SST49LF004A-33-4C-NH

Valid combinations for SST49LF008A

SST49LF008A-33-4C-WH SST49LF008A-33-4C-NH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

34

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTTOM VIEW

.495

Optional

Pin #1

Identifier

.048 .042

.485 .453 .447

1232

.020 R. MAX.

.029 .023

x 30˚

.112 .106

.040 .030

R.

Advance Information

.042 .048

.553

.595

.547

.585

.050 BSC

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.032 .026

.050 BSC

.140 .125

.095 .075

.021 .013

.400 BSC

.015 Min.

.530 .490

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

ACKAGE CODE: NH

SST P

.032 .026

32-plcc-NH-3

35

Advance Information

Pin # 1 Identifier

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

1.05

0.95

0.50

BSC

8.10

7.90

12.50

12.30

1.20

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

14.20

13.80

max.

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH

DETAIL

1mm

0.27

0.17

0.15

0.05

0˚- 5˚

0.70

0.50

32-tsop-WH-7

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

36