D Anti Latchup Capability
D Monolithic Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 1 pA
D Low Noise
D High CMRR: 90 dB
(V)V
GS(off)
-1 to -6-254.5-120
(BR)GSS
Min (V)gfs Min (mS)IG Typ (pA) |V
GS1
- V
D External Substrate Bias—Avoids Latchup
D Tight Differential Match vs. Current
D Improved Op Amp Speed, Settling Time
Accuracy
D High-Speed Performance
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signal
|Max (mV)
GS2
D Wideband Differential Amps
D High-Speed,
Temp-Compensated,
Single-Ended Input Amps
D High Speed Comparators
D Impedance Converters
DESCRIPTION
The SST441NL is a monolithic high-speed dual JFET
mounted in a single SO-8 package. This JFET is an excellent
choice for use as wideband differential amplifiers in
demanding test and measurement applications.
Pins 4 and 8 on the SST441NL and pin 4 on the U441NL part
numbers enable the substrate to be connected to a positive,
external bias (V
/16” from case for 10 sec.)300_C. . . . . . . . . . . . . . . . . . .
The U441NL in the hermetically sealed TO-78 package is
available with full military processing.
The SO-8 package provides ease of manufacturing. The
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods.
TO-78
S
1
1
D
1
2
3
G
1
Power Dissipation :Per Side
Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
Gate-Source Breakdown VoltageV
Gate-Source Cutoff VoltageV
Saturation Drain Current
Gate Reverse CurrentI
Gate Operating CurrentI
Gate-Source Forward VoltageV
b
(BR)GSS
GS(off)
I
DSS
GSS
G
GS(F)
IG = -1 mA, VDS = 0 V
VDS = 10 V, ID = 1 nA-1-3.5-6
VDS = 10 V, VGS = 0 V61530mA
VGS = -15 V, VDS = 0 V-1-500pA
TA = 125_C
VDG = 10 V, ID = 5 mA-1-500pA
TA = 125_C
IG = 1 mA , VDS = 0 V0.7V
-25-35
Dynamic
Common-Source
Forward Transconductance
Common-Source
Output Conductance
Common-Source
Forward Transconductance
Common-Source
Output Conductance
Common-Source
Input Capacitance
Common-Source
Reverse Transfer Capacitance
Equivalent Input Noise Voltagee
g
fs
g
os
g
fs
g
os
C
iss
C
rss
n
V
= 10 V, I
D
V
= 10 V, ID = 5 mA
D
V
= 10 V, ID = 5 mA
D
VDS = 10 V, ID = 5 mA
= 5 mA
D
f = 1 kHz
f = 100 MHz
f = 1 MHz
f = 10 kHz
4.569mS
Matching
Differential Gate-Source Voltage
Gate-Source Voltage Differential
Change with Temperature
Saturation Drain Current Ratio
Transconductance Ratio
Common Mode Rejection RatioCMRRVDG = 10 to 15 V, ID = 5 mA90dB
Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.NNZ
b. Pulse test: PW v300 ms duty cycle v3%.
c. Assumes smaller value in the numerator.