Datasheet SST39VF6401B, SST39VF6402B Datasheet (Silicon Storage Technology)

FEATURES:

64 Mbit (x16) Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

SST39VF640xB2.7V 64Mb (x16) MPF+ memories

Data Sheet

• Organized as 4M x16

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord)

for SST39VF6402B

– Bottom Block-Protection (bottom 32 KWord)

for SST39VF6401B

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

– 70 ns – 90 ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bits – Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pin Assignments – Software command sequence compatibility

- Address format is 11 bits, A

10-A0

- Block-Erase 6th Bus Write Cycle is 30H

- Sector-Erase 6th Bus Write Cycle is 50H

• Packages Available

– 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (8mm x 10mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39VF640xB devices are 4M x16 CMOS MultiPurpose Flash Plus (MPF+) manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF640xB write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories.

Featuring high performance Word-Program, the SST39VF640xB devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF640xB devices are suited for applications that require convenient and economical updating of program,

configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high-density, surface mount requirements, the SST39VF640xB devices are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 1 and 2 for pin assignments.

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF640xB also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the I typically 3 µA. The Auto Low Power mode reduces the typical I

active read current to the range of 2 mA/MHz of

DD

Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

active read current from typically 9 mA to

DD

Read

The Read operation of the SST39VF640xB is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).

Word-Program Operation

The SST39VF640xB are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.

Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF640xB offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms and Figure 23 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ

toggling and DQ6 at “1”. While in Erase-Suspend

2

mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence.

2

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Data Sheet

Chip-Erase Operation

The SST39VF640xB provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 9 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low.

Write Operation Status Detection

The SST39VF640xB provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ Tog gl e B i t ( D Q

). The End-of-Write detection mode is

6

) and

7

enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ

or DQ6. In order to pre-

7

vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39VF640xB are in the internal Program operation, any attempt to read DQ plement of the true data. Once the Program operation is completed, DQ though DQ

will produce true data. Note that even

7

may have valid data immediately following the

7

completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ internal Erase operation is completed, DQ

will produce the com-

7

will produce a ‘0’. Once the

7

will produce a

7

‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 20 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ is valid after the rising edge of sixth WE# (or CE#) pulse. DQ

will be set to “1” if a Read operation is attempted on an

6

Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ

will toggle.

6

An additional Toggle Bit is available on DQ used in conjunction with DQ sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ

) is valid after the rising edge of the last WE# (or CE#)

2

pulse of Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart.

TABLE 1: WRITE OPERATION STATUS

Status DQ7DQ

Normal Operation

EraseSuspend Mode

Note: DQ7 and DQ2 require a valid address when reading

Standard Program

Standard Erase

Read from Erase-Suspended Sector/Block

Read from Non- Erase-Suspended Sector/Block

Program DQ

status information.

will produce alternating “1”s

6

bit will

6

, which can be

2

to check whether a particular

6

DQ

6

DQ7# Toggle No Toggle

0 Toggle Toggle

1 1 Toggle

Data Data Data

# Toggle N/A

7

2

T1.0 1288

)

6

3

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Data Protection

The SST39VF640xB provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

V

Power Up/Down Detection: The Write operation is

DD

inhibited when V

Write Inhibit Mode:

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39VF6402B support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF6401B support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block.

TABLE 2: B

Product Address Range

Bottom Boot Block

SST39VF6401B 000000H-007FFFH

Top Boot Block

SST39VF6402B 3F8000H-3FFFFFH

OOT BLOCK ADDRESS RANGES

T2.0 1288

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T

any in-progress operation will terminate and

RP,

return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of T

RHR

is required after RST# is driven high before a valid Read can take place (see Figure 15).

The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF640xB provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within T

The contents of DQ15-DQ

RC.

can be VIL or VIH, but no other value, during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39VF640xB also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

8

4

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Data Sheet

Product Identification

The Product Identification mode identifies the devices as the SST39VF6401B and SST39VF6402B, and the manufacturer as SST. This mode may be accessed through software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart.

TABLE 3: P

Manufacturer’s ID 0000H BFH

Device ID

SST39VF6401B 0001H 236DH

SST39VF6402B 0001H 236CH

RODUCT IDENTIFICATION

Address Data

T3.0 1288

Product Identification Mode Exit/ CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 13 for timing waveform, and Figures 21 and 22 for flowcharts.

Security ID

The SST39VF640xB devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased.

The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details.

5

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Memory Address

RESET#

WE#

RST#

WP#

Address Buffer & Latches

CE#

OE# WE# WP#

A15 A14 A13 A12 A11 A10

A9

A8 A19 A20

A21

NC A18 A17

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

X-Decoder

Control Logic

Standard Pinout

Top View

Die Up

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ15 - DQ

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

1288 48-tsop P1.0

A16 NC V

SS

DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DD

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V

SS

CE# A0

0

1288 B1.0

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

6

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

TOP VIEW (balls facing down)

Data Sheet

6

5

4

3

2

1

A13

A12

A14

A15

A16

NC

DQ15

A9

A8

A10

A11

DQ7

DQ14

DQ13

WE#

RST#

A21

A19

DQ5

DQ12

V

NC

WP#

A18

A20

DQ2

DQ10

DQ11

A7

A17

A6

A5

DQ0

DQ8

DQ9

A3

A4

A2

A1

A0

CE#

OE#

A B C D E F G H

DD

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

1288 4-tfbga B1K P2.0

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

TABLE 4: P

Symbol Pin Name Functions

1

A

-A

MS

DQ15-DQ

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address A

MS

IN DESCRIPTION

Address Inputs To provide memory addresses.

0

During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block.

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 2.7-3.6V

Ground

= A21 for SST39VF640xB

T4.0 1288

7

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Data Sheet

TABLE 5: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

Program V

Erase V

Standby V

IL

IH

Write Inhibit X V

XXV

Product Identification

Software Mode V

1. X can be VIL or VIH, but no other value.

IL

V

IL

V

IH

V

IH

V

D

IH

IL

OUT

D

IN 1

X

X X High Z X

IL

V

IL

X High Z/ D

High Z/ D

IH

V

IH

OUT

A

IN

A

IN

Sector or block address, XXH for Chip-Erase

X

See Table 6

T5.0 1288

8

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Data Sheet

TABLE 6: SOFTWARE COMMAND SEQUENCE

Command Sequence

Word-Program

Sector-Erase

Block-Erase

Chip-Erase

Erase-Suspend

Erase-Resume

Query Sec ID

User Security ID Word-Program

User Security ID Program Lock-Out

Software ID Entry

CFI Query Entry

Software ID Exit /CFI Exit/Sec ID Exit

1. Address format A10-A0 (Hex).

2. DQ

3. WA = Program Word address

4. SA

5. With A

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With A

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

5

7,8

9,10

Addresses A

15

for Sector-Erase; uses AMS-A11 address lines

X

BA

, for Block-Erase; uses AMS-A15 address lines

X

A

= Most significant address

MS

A

= A21 for SST39VF640xB

MS

11

-DQ8 can be VIL or VIH, but no other value, for Command sequence

= 0; Sec ID is read with A3-A0,

MS-A4

Lock Status is read with A

=0; SST Manufacturer ID = 00BFH, is read with A0 = 0,

MS-A1

A

= Most significant address

MS

A

= A21 for SST39VF640xB

MS

mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

1st Bus

Write Cycle

1

Addr

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data

555H AAH 2AAH 55H 555H A0H WA

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BA

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

3

Data

5th Bus

Write Cycle

6th Bus

Write Cycle

4

X

4

X

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

XXXXH B0H

XXXXH 30H

555H AAH 2AAH 55H 555H 88H

555H AAH 2AAH 55H 555H A5H WA

6

Data

555H AAH 2AAH 55H 555H 85H XXH60000H

555H AAH 2AAH 55H 555H 90H

555H AAH 2AAH 55H 555H 98H

555H AAH 2AAH 55H 555H F0H

XXH F0H

- A21 can be VIL or V

SST ID is read with A User ID is read with A

7-A0

SST39VF6401B Device ID = 236DH, is read with A SST39VF6402B Device ID = 236CH, is read with A

but no other value, for Command sequence for SST39VF640xB.

IH,

= 0 (Address range = 000000H to 000007H),

3

= 1 (Address range = 000010H to 000017H).

3

= 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

= 1,

0

= 1.

0

2

50H

30H

T6.0 1288

9

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Data Sheet

TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF640XB

Address Data Data

10H 0051H Query Unique ASCII string “QRY” 11H 0052H 12H 0059H 13H 0002H Primary OEM command set 14H 0000H 15H 0000H Address for Primary Extended Table 16H 0000H 17H 0000H Alternate OEM command set (00H = none exists) 18H 0000H 19H 0000H Address for Alternate OEM extended Table (00H = none exits) 1AH 0000H

1. Refer to CFI publication 100 for more details.

TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF640XB

Address Data Data

1BH 0027H V

1CH 0036H V

1DH 0000H V

1EH 0000H V

1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)

20H 0000H Typical time out for min. size buffer program 2

21H 0004H Typical time out for individual Sector/Block-Erase 2

22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)

23H 0001H Maximum time out for Word-Program 2

24H 0000H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2

26H 0001H Maximum time out for Chip-Erase 2

Min (Program/Erase)

DD

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

Max (Program/Erase)

DD

-DQ4: Volts, DQ3-DQ0: 100 millivolts

DQ

7

min. (00H = no VPP pin)

PP

max. (00H = no VPP pin)

PP

N

µs (00H = not supported)

N

times typical (21 x 23 = 16 µs)

N

times typical (21 x 25 = 64 ms)

ms (24 = 16 ms)

N

times typical (21 x 24 = 32 ms)

T7.0 1288

T8.0 1288

TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF640XB

Address Data Data

27H 0017H Device size = 2 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H Maximum number of bytes in multi-byte write = 2 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0007H y = 2047 + 1 = 2048 sectors (07FFH = 2047) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) 31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y =127 + 1 = 128 blocks (007FH = 127) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

N

Bytes (17H = 23; 223 = 8 MByte)

10

N

(00H = not supported)

T9.0 1288

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

Voltage on A Package Power Dissipation Capability (T Surface Mount Solder Reflow Temperature Output Short Circuit Current

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

A

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

°C for 10 seconds; please consult the factory for the latest information.

OPERATING RANGE

Range Ambient Temp V

Commercial Industrial

0°C to +70°C

-40°C to +85°C

DD

2.7-3.6V

DD

+0.5V +2.0V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

See Figures 17 and 18

= 30 pF

L

11

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Data Sheet

TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V

Limits

Symbol Parameter

I

DD

I

SB

I

ALP

I

LI

I

LIW

I

LO

V

IL

V

ILC

V

IH

V

IHC

V

OL

V

OH

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

2. See Figure 17

3. The I

Power Supply Current Address input=V

3

Read

Program and Erase 35 mA CE#=WE#=V

Standby VDD Current 20 µA CE#=V

Auto Low Power 20 µA CE#=V

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

Input Leakage Current on WP# pin and RST#

Output Leakage Current 10 µA V

Input Low Voltage 0.8 V VDD=VDD Min

Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

Input High Voltage 0.7V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

(room temperature), and V

current listed is typically less than 2mA/MHz, with OE# at V

DD

= 3V. Not 100% tested.

DD

1

Test ConditionsMin Max Units

VDD=VDD Max

18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

IHC

ILC

All inputs=V

10 µA WP#=GND to VDD or RST#=GND to V

=GND to VDD, VDD=VDD Max

OUT

VVDD=VDD Max

Ty p i ca l VDD is 3V.

IH.

ILT/VIHT

, OE#=V

IL

, VDD=VDD Max

SS

or V

WE#=V

DD,

2

, at f=5 MHz,

IH

IHC

T10.0 1288

DD

TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

TABLE 12: CAPACITANCE (T

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

Power-up to Program/Erase Operation 100 µs

= 25°C, f=1 Mhz, other pins open)

A

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 13: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1,2

N

END

1

T

DR

1

I

LT H

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

2. N

END

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

DD

mA JEDEC Standard 78

T11.0 1288

T12.0 1288

T13.0 1288

12

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

AC CHARACTERISTICS

TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

SST39VF640xB-70 SST39VF640xB-90

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

T

CLZ

T

OLZ

T

CHZ

T

OHZ

1

T

OH

1

T

RP

T

RHR

1,2

T

RY

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

Read Cycle Time 70 90 ns

Chip Enable Access Time 70 90 ns

Address Access Time 70 90 ns

Output Enable Access Time 35 45 ns

1

CE# Low to Active Output 0 0 ns

1

OE# Low to Active Output 0 0 ns

1

CE# High to High-Z Output 20 30 ns

1

OE# High to High-Z Output 20 30 ns

Output Hold from Address Change 0 0 ns

RST# Pulse Width 500 500 ns

1

RST# High before Read 50 50 ns

RST# Pin Low to Read Mode 20 20 µs

This parameter does not apply to Chip-Erase operations.

Data Sheet

UnitsMin Max Min Max

T14.0 1288

TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

BE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Word-Program Time 10 µs

Address Setup Time 0 ns

Address Hold Time 30 ns

WE# and CE# Setup Time 0 ns

WE# and CE# Hold Time 0 ns

OE# High Setup Time 0 ns

OE# High Hold Time 10 ns

CE# Pulse Width 40 ns

WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns

Data Setup Time 30 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns

Sector-Erase 25 ms

Block-Erase 25 ms

Chip-Erase 50 ms

T15.0 1288

13

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

ADDRESS A

DQ

MS-0

CE#

OE#

WE#

15-0

IH

HIGH-Z

Note: AMS = Most significant address

A

= A21 for SST39VF640xB

MS

FIGURE 3: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

DATA VALIDDATA VALID

CHZ

HIGH-Z

1288 F03.0

ADDRESS A

DQ

MS-0

WE#

OE#

CE#

15-0

T

AS

Note: AMS = Most significant address

555 2AA 555 ADDR

T

AH

T

WP

T

WPH

T

CH

T

CS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

A

= A21 for SST39VF640xB

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

(ADDR/DATA)

T

DS

WORD

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

1288 F04.0

14

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

ADDRESS A

DQ

MS-0

CE#

OE#

WE#

15-0

T

AS

555 2AA 555 ADDR T

AH

T

CP

T

CPH

T

CS

XXAA XX55 XXA0 DATA

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

T

DS

T

CH

SW0 SW1 SW2

Note: AMS = Most significant address

A

= A21 for SST39VF640xB

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

WORD

(ADDR/DATA)

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

T

OEH

T

CE

T

OE

1288 F05.0

T

OES

DQ

7

Note: AMS = Most significant address

DATA DATA# DATA# DATA

A

= A21 for SST39VF640xB

MS

1288 F06.0

FIGURE 6: DATA# POLLING TIMING DIAGRAM

15

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

ADDRESS A

MS-0

CE#

OEH

OE#

WE#

DQ

and DQ

6

2

Note: AMS = Most significant address

A

= A21 for SST39VF640xB

MS

FIGURE 7: TOGGLE BITS TIMING DIAGRAM

T

CE

T

OET

TWO READ CYCLES

WITH SAME OUTPUTS

OES

1288 F07.0

SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS A

MS-0

555 2AA 2AA555 555

CE#

OE#

T

WP

WE#

DQ

15-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 15) A

= Most significant address

MS

= A21 for SST39VF640xB

A

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

T

SCE

555

XX55 XX10XX55XXAA XX80 XXAA

1288 F08.0

16

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

SIX-BYTE CODE FOR BLOCK-ERASE

Data Sheet

T

BE

ADDRESS A

DQ

MS-0

CE#

OE#

WE#

15-0

555 2AA 2AA555 555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 15) BA

= Block Address

X

A

= Most significant address

MS

A

= A21 for SST39VF640xB

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

BA

X

XX55 XX30XX55XXAA XX80 XXAA

1288 F09.0

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESS A

MS-0

555 2AA 2AA555 555

SA

X

CE#

OE#

T

WP

WE#

DQ

15-0

XX55 XX50XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 15) SA

= Sector Address

X

A

= Most significant address

MS

A

= A21 for SST39VF640xB

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

T

SE

1288 F10.0

17

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Three-Byte Sequence for Software ID Entry

ADDRESS A

DQ

14-0

CE#

OE#

WE#

15-0

Note: Device ID = 236DH for SST39VF6401B and 236CH for SST39VF6402B

555 2AA 555 0000 0001

T

WP

T

WPH

XX55XXAA XX90

SW0 SW1 SW2

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

00BF

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

Device ID

1288 F11.0

Three-Byte Sequence for CFI Query Entry

ADDRESS A

DQ

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

14-0

CE#

OE#

WE#

15-0

X can be V

555 2AA 555

T

WP

T

WPH

XX55XXAA XX98

SW0 SW1 SW2

or V

but no other value.

IL

IH,

FIGURE 12: CFI QUERY ENTRY AND READ

T

IDA

T

AA

1288 F12.0

18

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

Data Sheet

ADDRESS A

DQ

14-0

15-0

555 2AA 555

XXAA XX55 XXF0

CE#

OE#

T

WP

WE#

T

SW0 SW1 SW2

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be V

or V

but no other value.

IL

IH,

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

WHP

T

IDA

1288 F13.0

ADDRESS A

MS-0

555 2AA 555

CE#

OE#

WE#

DQ

15-0

Note: AMS = Most significant address

A

= A21 for SST39VF640xB

MS

WP# must be held in proper logic state (V X can be V

IL

or V

FIGURE 14: SEC ID ENTRY

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

T

WP

T

WPH

XX55XXAA XX88

SW0 SW1 SW2

but no other value.

IH,

T

IDA

T

AA

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

1288 F14.0

19

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Data Sheet

T

RP

RST#

T

CE#/OE#

FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

T

RP

RHR

1288 F15.0

RST#

T

RY

CE#/OE#

End-of-Write Detection

(Toggle-Bit)

FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

1288 F16.0

20

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

V

IHT

Data Sheet

V

ILT

AC test inputs are driven at V for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

1288 F17.0

(0.1 VDD) for a logic “0”. Measurement reference points

ILT

Note: V

- V

INPUT

OUTPUT

INPUT

Tes t

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

1288 F18.0

FIGURE 18: A TEST LOAD EXAMPLE

C

L

21

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

FIGURE 19: WORD-PROGRAM ALGORITHM

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1288 F19.0

X can be VIL or VIH, but no other value

22

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Data Sheet

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE, TSE

or T

BE

Program/Erase

Completed

Program/Erase

No

Toggle Bit

Initiated

Read word

Read same

word

Does DQ

6

match?

Ye s

No

Data# Polling

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Ye s

Program/Erase

Completed

Program/Erase

Completed

1288 F20.0

FIGURE 20: WAIT OPTIONS

23

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

CFI Query Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait T

IDA

Sec ID Query Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait T

IDA

Software Product ID Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait T

IDA

Read CFI data

X can be VIL or VIH, but no other value

Read Sec ID

FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS

Read Software ID

1288 F21.0

24

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Data Sheet

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Wait T

IDA

Return to normal

operation

X can be VIL or VIH, but no other value

Load data: XXF0H

Address: XXH

Wait T

IDA

Return to normal

operation

1288 F22.0

FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS

25

Data Sheet

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Chip-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Block-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Wait T

SCE

Chip erased

to FFFFH

Load data: XX50H

Address: SA

Wait T

X

SE

Sector erased

to FFFFH

X can be VIL or VIH, but no other value

Load data: XX30H

Address: BA

Wait T

X

BE

Block erased

to FFFFH

1288 F23.0

FIGURE 23: ERASE COMMAND SEQUENCE

26

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

PRODUCT ORDERING INFORMATION

SST 39 VF 6402B - 70 - 4C - EK E

XX

XX XXXXB - XXX -XX -XXX X

Data Sheet

Environmental Attribute

1

E

= non-Pb

Package Modifier

K = 48 balls or leads

Package Type

E = TSOP (type1, die up, 12mm x 20mm) B1 = TFBGA (8mm x 10mm, 0.8mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns 90 = 90 ns

Hardware Block Protection

1 = Bottom Boot-Block 2 = Top Boot-Block

Device Density

640 = 64 Mbit

Volt ag e

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash Plus

1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

27

Data Sheet

Valid Combinations for SST39VF6401B

SST39VF6401B-70-4C-EK SST39VF6401B-70-4C-B1K SST39VF6401B-70-4C-EKE SST39VF6401B-70-4C-B1KE SST39VF6401B-90-4C-EK SST39VF6401B-90-4C-B1K SST39VF6401B-90-4C-EKE SST39VF6401B-90-4C-B1KE

SST39VF6401B-70-4I-EK SST39VF6401B-70-4I-B1K SST39VF6401B-70-4I-EKE SST39VF6401B-70-4I-B1KE SST39VF6401B-90-4I-EK SST39VF6401B-90-4I-B1K SST39VF6401B-90-4I-EKE SST39VF6401B-90-4I-B1KE

Valid Combinations for SST39VF6402B

SST39VF6402B-70-4C-EK SST39VF6402B-70-4C-B1K SST39VF6402B-70-4C-EKE SST39VF6402B-70-4C-B1KE SST39VF6402B-90-4C-EK SST39VF6402B-90-4C-B1K SST39VF6402B-90-4C-EKE SST39VF6402B-90-4C-B1KE

SST39VF6402B-70-4I-EK SST39VF6402B-70-4I-B1K SST39VF6402B-70-4I-EKE SST39VF6402B-70-4I-B1KE SST39VF6402B-90-4I-EK SST39VF6402B-90-4I-B1K SST39VF6402B-90-4I-EKE SST39VF6402B-90-4I-B1KE

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

28

64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B

PACKAGING DIAGRAMS

Pin # 1 Identifier

12.20

11.80

Data Sheet

1.05

0.95

0.50

BSC

0.27

0.17

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

20.20

19.80

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK

0.15

0.05

DETAIL

1.20 max.

0˚- 5˚

0.70

0.50

1mm

48-tsop-EK-8

29

Data Sheet

10.00 ± 0.20

64 Mbit Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B

BOTTOM VIEWTOP VIEW

5.60

0.80

6

5

4

3

2

1

A B C D E F G H

A1 CORNER

SIDE VIEW

SEATING PLANE

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

8.00 ± 0.20

1.10 ± 0.10

0.12

0.35 ± 0.05

4.00

0.80

H G F E D C B A

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM SST PACKAGE CODE: B1K

6

5

4

3

2

1

0.45 ± 0.05 (48X)

A1 CORNER

1mm

48-tfbga-B1K-8x10-450mic-4

TABLE 16: R

EVISION HISTORY

Number Description Date

00

01

02

• Initial release

• Clarified JEDEC software command compatibility on page 1

• Changed document phase from Preliminary Information to Data Sheet

Mar 2005

May 2005

Jul 2006

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

30

Datasheet SST39VF6401B, SST39VF6402B Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual