Datasheet SST39VF1681, SST39VF1682 Datasheet (Silicon Storage Technology)

FEATURES:

16 Mbit (x8) Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

SST39VF1681 / 16822.7V 16Mb (x8) MPF+ memories

Preliminary Specifications

• Organized as 2M x8

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low P ower Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 64 KByte)

for SST39VF1682

– Bottom Block-Protection (bottom 64 KByte)

for SST39VF1681

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

– 70 ns – 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Byte-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bits – Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and Command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm) – 48-lead TSOP (12mm x 20mm)

PRODUCT DESCRIPTION

The SST39VF168x devices are 2M x8 C MOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program time of 7 µsec. These devices use T oggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protec tion schem es. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a g ua rant eed ty pic al en dur ance of 100,00 0 cycles. Data retention is ra ted at greater than 100 y ears .

The SST39VF168x devices are suited for applications that require convenient and economi cal updating of program, configuration, or da ta memory. For all system a ppl i ca tio ns,

they significantly i mp r ove performa nc e an d re li ab il it y, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The tota l energy consumed is a function of the applied voltage, curre nt, and time of ap plic ation . Sinc e for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also impr ove flexibility while lowering the c ost for program, data, and configuration storage applications.

The SuperFlash technology prov ides fixed Erase and Program times, independent of the n umbe r of Er ase/Prog r am cycles that have occurred. Therefore the system software or hardware does not hav e to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA and 48-lead TSOP packages. See Figures 1 and 2 for pin assignments.

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocess or write sequences. A command is written by asse r ting WE# low whil e keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. T he data bus is latc hed o n the rising edge of WE# or CE#, whichever occurs first.

The SST39VF168x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the I typically 3 µA. The Auto Low Pow er mode reduces the typical I

active read current to the range of 2 mA/MHz of

DD

Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate ano ther Read cycle, with no access t ime penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

active read current from typically 9 mA to

DD

Read

The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).

Byte-Program Operation

The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The s econd step is to load byte address and byte data. During the ByteProgram opera tion, th e addr esses ar e latche d on the fa lling edge of either CE# or WE#, whichever occurs last. The data is latched on th e rising edge of ei ther CE# or WE#, whichever occurs first. The third step is the in ternal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figure s 4 a nd 5 for WE # and CE # co nt ro ll ed P r og ram operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the in tern al Program operation, the host is fre e to perform ad ditiona l tasks. Any

commands issu ed during the inter nal Program operation are ignored. Dur ing the c omman d seq uence, WP # sho uld be statically held high or lo w .

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39V F168x offer both Sector-Erase and Block-Erase mode. The sec tor architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on unifor m block size of 64 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the comm and (30H or 50H) is latched on th e rising edge of the sixth WE# pulse. The internal Erase operation begins a fter the sixth WE# pulse. The End -ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms and Figure 23 for the flowchart. Any commands issued during the Sec tor- or B lock-Era se op erat io n are ignored. When WP# is low, any attempt to Sector(Block-) Erase the prote cted block will be ignor ed. During the command sequence, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memor y loca tion, or program data into any sector/block that is not sus pended for an Erase operation . The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Era se-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at addr ess location withi n erase-suspende d sectors/blocks will output DQ

toggling and DQ6 at “1”. While in Erase-Suspend

2

mode, a Byte-Program operation is allowed except for the sector or block selected for Erase-Suspend.

T o resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in th e last Byte sequence .

2

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

Chip-Erase Operation

The SST39VF168x provide a Chip-Erase o peration, w hich allows the user to erase the entire memory arra y to the “1” state. This is useful when the entire de vice must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only v alid read is Toggle Bit or Data# P olling. See Table 6 for the command sequence, Figure 9 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or lo w.

Write Operation Status Detection

The SST39VF16 8x provide two softwar e means to det ect the completion of a Write (Program or Erase) cycle, in order to optimize the syst em write cycl e time . The s oftw are detection includes two status bits: Data# Polling (DQ Toggle Bit (DQ

). The End-of-Write detection mode is

6

) and

7

enabled after the rising edge of WE#, which initiate s the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict w it h ei th er D Q

or DQ6. In order to pre-

7

vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the reje ction is valid.

Data# Polling (DQ7)

When the SST39VF168x are in the internal Program ope ration, any attempt to read DQ ment of the true data. Once the Program operation is completed, DQ though DQ

will produce true data. Note that even

7

may have valid data immediately following the

7

completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after a n in te rva l of 1 µ s . Du ring internal Erase operation, any attempt t o rea d DQ internal Erase operation is completed, DQ

will produce the comple-

7

will produce a ‘0’. Once the

7

will produce a

7

‘1’. The Data# P olling is v alid after the rising edge o f f ourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# P olling timing diagram an d Figure 20 f or a flowchart.

Toggle Bits (DQ6 and DQ2)

During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ and “0”s, i.e., toggling between 1 and 0. Wh en the i nte rnal Program or Erase operat ion is complete d, the DQ stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ is valid after the ris ing edge of six th WE# (or CE#) p ulse. DQ

will be set to “1” if a Read operation is attempted on an

6

Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ

will toggle .

6

An additional Toggle Bit is available on DQ used in conjunction with DQ sector is being actively erased or erase-suspended. T able 1 shows detailed status bits information. The Toggle Bit (DQ

) is valid after the rising edge of the last WE# (or CE#)

2

pulse of Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart.

TABLE 1: WRITE OPERATION STATUS

Status DQ7DQ

Normal Operation

EraseSuspend Mode

Note: DQ7 and DQ2 require a valid address when reading

Standard Program

Standard Erase

Read from Erase Suspended Sector/Block

Read from Non- Erase Suspended Sector/Block

Program DQ

status information.

will produc e a lt ernat in g “1 ” s

6

bit will

6

, which can be

2

to check w h ethe r a pa rticular

6

DQ

6

DQ7# Toggle No Toggle

0 Toggle Toggle

1 1 Toggle

Data Data Data

# Toggle N/A

7

2

T1.0 1243

)

6

3

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Protection

The SST39VF168x provide both hardware and software feature s to pr otect n onv ol atile data f rom inad vertent writ es.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5 ns will not init iate a write cycle .

V

Power Up/Down Detection: The Write operation is

DD

inhibited when V Write Inhibit Mode:

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE# high will inhibit the W r ite operation. This prevents inadvertent writes during p ow er-up o r po wer- down.

Hardware Block Protection

The SST39VF168 2 supports top har dware block protection, which protects the top 64 KByte block of the device. The SST39VF1681 su pports bottom hardware block protection, which pr otects the bottom 64 KByte block of the device. The Boot Block addre ss ranges are describ ed in Table 2. Program and Erase operation s are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block.

TABLE 2: B

Product Address Range Bottom Boot Block

SST39VF1681 000000H-00FFFFH

Top Boot Block

SST39VF1682 1F0000H-1FFFFFH

OOT BLOCK ADDRESS RANGES

T2.1 1243

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T

any in-progress operation will terminate and

RP,

return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of T

RHR

is required after RST# is driven high before a valid Read can take place (see Figure 15).

The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity .

Software Data Protection (SDP)

The SST39VF 168x pr ovide t he JEDEC appro ved S oftw are Data Protection schem e for all data alteration operations, i.e., Program and Erase. Any Program operation requi res the inclusion of the th ree-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal pr otection from inad vertent W rite operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices a re shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within T

RC.

Common Flash Memory Interface (CFI)

The SST39VF168x also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address AAAH in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tab les 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

4

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

Product Identification

The Product Identificatio n mode id entifies th e devices as the SST39VF1681 and SST39VF1682, and manufacturer as SST. Users may use the s oftware Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same s ocket. For details, see Table 6 for software operation, Figure 11 for the software ID Entry and Read timing diagram, and Figure 21 for the software ID Entry c ommand sequence flowchart.

TABLE 3: P

Manufacture r’s ID 0000H BFH Device ID

SST39VF1681 0001H C8H SST39VF1682 0001H C9H

RODUCT IDENTIFICATION

Address Data

T3.1 1243

Product Identification Mode Exit/ CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identific ation mode must be exited. Exit is acco mplished by issuing the software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that

apparently caus es the device to behave abnor mally, e.g., not read correctly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 13 for timing waveform, and Figures 21 and 22 for flowcharts.

Security ID

The SST39VF168x devices offer a 256-bit Security ID space which is divided into two 128-bit segments. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programme d for the customer to prog ram a s desir ed.

To program the user segm ent of the Security ID, the user must use the Security ID Byte-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complet e, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corr up ti on of this sp ac e. Note tha t regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased.

The Security ID space can be queried by executing a three-byte command sequence with Enter-Sec-ID command (88H) at addr ess AAAH in the last byte s equence. Execute the Exit-Sec-ID command to exit this mode. Refer to Table 6 for more details.

FUNCTIONAL BLOCK DIAGRAM

X-Decoder

Memory Address

RESET#

Address Buffer & Latches

CE#

OE# WE# WP#

Control Logic

I/O Buffers and Data Latches

5

SuperFlash

Memory

Y-Decoder

DQ7 - DQ

0

1243 B1.0

Preliminary Specifications

TOP VIEW (balls facing down)

6

A14

A13

5

A10

A9

4

WE#

RST#

3

NC

WP#

2

A8

A4

A18

A5

1

A B C D E F G H

FIGURE 1: PIN ASSIGNMENTS FOR 48-LE A D TFBGA

A15

A11

NC

A19

A7

A3

A16

A12

A20

NC

A6

A2

A17

DQ7

DQ5

DQ2

DQ0

A1

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

NC

A0

V

SS

NC

DQ6

NC

V

DQ4

DD

NC

DQ3

NC

DQ1

CE#

OE#

V

SS

1243 48-tfbga B3K P1.0

FIGURE 2: P

A16 A15 A14 A13 A12 A11 A10

A9

A20

NC

WE#

RST#

NC

WP#

NC A19 A18

A8 A7 A6 A5 A4 A3 A2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard Pinout

To p Vi ew

IN ASSIGNMENTS FOR 48-LEAD TSOP

Die Up

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

1243 48-tsop P2.0

A17 NC V

SS

A0 DQ7 NC DQ6 NC DQ5 NC DQ4 V

DD

NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# V

SS

CE# A1

6

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

TABLE 4: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ

DQ

7

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RST# Reset To reset and return the device to Read mod e . CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address A

MS

Address Inputs To provide memory addresses.

0

During Sector-Erase A During Block-Erase A

Data Input/output T o outpu t d ata during Read cycles and rece ive input data during Write cycles.

0

MS-A16

address lines will select the sector.

MS-A12

address lines will select the block.

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 2.7-3.6V Ground

= A20 for SST39VF1681/1682

T4.1 1243

TABLE 5: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V Program V Erase V

Standby V

IL IL IL

IH

Write Inhibit X V

XXV Product Identification Software Mode V

1. X can be VIL or VIH, but no other value.

IL

V

IL

V

IH

V

IH

X X High Z X

IL

V

IL

V V V

D

IH IL IL

D X

OUT IN

1

X High Z/ D

High Z/ D

IH

V

IH

OUT OUT

A

IN

A

IN

Sector or block ad dress, XXH for Chip-Erase

X X

See Table 6

T5.0 1243

7

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Preliminary Specifications

TABLE 6: SOFTWARE COMMAND SEQUENCE

Command Sequence

Byte-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID User Security ID

Byte-Program User Security ID

Program Lock-Out Software ID En try

CFI Query Entry Software ID Exit

/CFI Exit/Sec ID Exit Software ID Ex i t

/CFI Exit/Sec ID Exit

1. Address format A11-A0 (Hex).

2. BA = Program Byte Address

3. SA

4. With A

5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH.

6. The device does not remain in Software Product ID Mode if powered down.

7. With A

8. Both Software ID Exit operations are equivalent

9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

4

6,7

8,9

Addresses A

for Sector-Erase; uses AMS-A12 address lines

X

BA

, for Block-Erase; uses AMS-A16 address lines

X

A

= Most significant address

MS

A

= A20 for SST39VF1681/1682

MS

Lock Status is read with A

A

= Most significant address

MS

A

= A20 for SST39VF1681/1682

MS

mode again (the programmed “0” bits cannot be reversed to “1”).

20-A12

= 0; Sec ID is read with A4-A0,

MS-A5

=0; SST Manufacturer ID = 00BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

1

Addr

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

AAAH AAH 555H 55H AAAH A0H BA

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

2

Data

5th Bus

Write Cycle

6th Bus

Write Cycle

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BA

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H XXXXH B0H XXXXH 30H

AAAH AAH 555H 55H AAAH 88H

AAAH AAH 555H 55H AAAH A5H BA

AAAH AAH 555H 55H AAAH 85H XXH

5

Data

5

00H

AAAH AAH 555H 55H AAAH 90H

AAAH AAH 555H 55H AAAH 98H

AAAH AAH 555H 55H AAAH F0H

XXH F0H

can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682.

SST ID is read with A User ID is read with A

SST39VF1681 Device ID = C8H, is read with A SST39VF1682 Device ID = C9H, is read with A

= 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

7-A0

= 0 (Address range = 00000H to 0000FH),

4

= 1 (Address range = 00010H to 0001FH).

4

= 1,

0

= 1,

0

3

50H

X

3

30H

X

T6.1 1243

8

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

TABLE 7: CFI QUERY IDENTIFICATION STRING

Address Data Data

10H 51H Query Unique ASCII string “QRY” 11H 52H 12H 59H 13H 01H Primary OEM command set 14H 07H 15H 00H Address for Primary Extended Table 16H 00H 17H 00H Alternate OEM command set (00H = none exists) 18H 00H 19H 00H Address for Alternate OEM extended Table (00H = none exits) 1AH 0 0H

1. Refer to CFI publication 100 for more details.

TABLE 8: SYSTEM INTERFACE INFORMATION

Address Data Data

1BH 2 7H V

1CH 36H VDD Max (Program/Erase)

1DH 00H VPP min. (00H = no VPP pin) 1EH 0 0H VPP max. (00H = no VPP pin) 1FH 03H Typical time out for Byte-Program 2 20H 00H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 04H Typical time out for individual Sector/Block-Er as e 2N ms (24 = 16 ms) 22H 05H Typical time out for Chip-Erase 2 23H 01H Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 µs) 24H 00H Maximum time out for buffer program 2N times typical 25H 01H Maximum time out for individual Sector/Block-Erase 2 26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)

Min (Program/Erase)

DD

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

1

N

ms (25 = 32 ms)

N

µs (23 = 8 µs)

N

times typica l (21 x 24 = 32 ms)

Preliminary Specifications

T7.1 1243

T8.1 1243

TABLE 9: DEVICE GEOMETRY INFORMATION

Address Data Data

27H 15H Device size = 2 28H 00H Flash Device Interface description; 00H = x8-only asynchronous interface 29H 00H 2AH 00H Maximum number of byte in multi-byte write = 2 2BH 0 0H 2CH 02H Number of Erase Sector/Block sizes supported by device 2DH FFH Sector Infor mation (y + 1 = Number of sectors; z x 256B = sector size) 2EH 01H y = 511 + 1 = 512 sectors (01FF = 511 2FH 10H 30H 00H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) 31H 1FH Block In formation (y + 1 = Number of blocks; z x 256B = block size) 32H 00H y = 31 + 1 = 32 blocks (1F = 31) 33H 00H 34H 01H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

N

Bytes (15H = 21; 221 = 2 MByte)

9

N

(00H = not supported)

T9.1 1243

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

OPERATING RANGE

Range Ambient Temp V

Commercial Industrial

0°C to +70°C

-40°C to +85°C

DD

2.7-3.6V

DD DD

+0.5V +2.0V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

See Figures 17 and 18

= 30 pF

L

10

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V

Limits

Symbol Parameter

I

DD

I

SB

I

ALP

I

LI

I

LIW

I

LO

V

IL

V

ILC

V

IH

V

IHC

V

OL

V

OH

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

2. See Figure 17

3. The I

Power Supply Current Address input=V

3

Read Program and Erase 35 mA CE#=WE#=VIL, OE#=V Standby VDD Current 20 µA CE#=V Auto Low Power 20 µA CE#=V

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Input Leakage Current

on WP# pin and RST# Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input Low Voltage (CMOS) 0.3 V VDD=VDD Max Input High Voltage 0.7V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

(room temperature), and V

current listed is typically less than 2mA/MHz, with OE# at V

DD

= 3V. Not 100% tested.

DD

1

Test ConditionsMin Max Units

V

DD=VDD

Max

18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

, VDD=VDD Max

IHC

, VDD=VDD Max

ILC

All inputs=V

10 µA WP#=GND to VDD or RST#=GND to V

=GND to VDD, VDD=VDD Max

OUT

VVDD=VDD Max

Typical VDD is 3V.

IH.

Preliminary Specifications

2

SS

IL T/VIHT

or V

WE#=V

DD,

IH

, at f=5 MHz,

IHC

T10.8 1243

DD

TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T T

1

PU-READ PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs

TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 13: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1,2

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. N

endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rat ing would result in a

END

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

DD

mA JEDEC Standard 78

T11.0 1243

T12.0 1243

T13.2 1243

11

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Preliminary Specifications

AC CHARACTERISTICS

TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

SST39VF168x-70 SST39VF168x-90

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

T

CLZ

T

OLZ

T

CHZ

T

OHZ

1

T

OH

1

T

RP

T

RHR

1,2

T

RY

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

Read Cycle Time 70 90 ns Chip Enable Access Time 70 90 ns Address Access Time 70 90 ns Output Enable Access Time 35 45 ns

1

CE# Low to Active Output 0 0 ns

1

OE# Low to Active Output 0 0 ns

1

CE# High to High-Z Output 20 30 ns

1

OE# High to High-Z Output 20 30 ns Output Hold from Address Change 0 0 ns RST# Pulse Width 500 500 ns

1

RST# High before Read 50 50 ns RST# Pin Low to Read Mode 20 20 µs

This parameter does not apply to Chip-Erase operations.

UnitsMin Max Min Max

T14.1 1243

TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

BE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Byte-Program Time 10 µs Address Setup Time 0 ns Address Hol d Time 30 ns WE# and CE# Setup Time 0 ns WE# and CE# Hold Time 0 ns OE# High Setup Time 0 ns OE# High Hold Time 10 ns CE# Pulse Width 40 ns WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns Data Setup Time 30 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns Sector-Erase 25 ms Block-Erase 25 ms Chip-Erase 50 ms

T15.0 1243

12

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

ADDRESS A

MS-0

CE#

OE#

IH

WE#

DQ

15-0

HIGH-Z

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

FIGURE 3: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

CHZ

HIGH-Z

DATA VALIDDATA VALID

1243 F02.0

ADDRESS A

MS-0

AAA AAA555 ADDR

T

AH

T

WP

WE#

T

AS

T

WPH

T

DS

OE#

T

CH

CE#

T

CS

DQ

7-0

AA 55 A0 DATA

SW0 SW1 SW2

BYTE

(ADDR/DATA)

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

1243 F03.0

13

Preliminary Specifications

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

INTERNAL PROGRAM OPERATION STARTS

T

BP

AAA AAA555 ADDR

T

AH

T

CP

T

AS

T

CPH

T

CS

T

CH

T

DS

AA 55 A0 DATA

T

DH

SW0 SW1 SW2

BYTE

(ADDR/DATA)

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

T

OEH

T

CE

T

OE

T

1243 F04.0

OES

DQ

7

DATA DATA# DATA# DATA

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

1243 F05.0

FIGURE 6: DATA# POLLING TIMING DIAGRAM

14

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

ADDRESS A

MS-0

CE#

OEH

OE#

WE#

and DQ

DQ

6

2

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

FIGURE 7: TOGGLE BIT S TIMING DIAGRAM

T

CE

T

OET

TWO READ CYCLES

WITH SAME OUTPUTS

OES

1243 F06.0

SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS A

MS-0

AAA AAA AAA555 AAA

CE#

OE#

T

WP

WE#

DQ

7-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) A

= Most Significant Address

MS

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

555

T

SCE

55 1055AA 80 AA

1243 F07.0

15

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SIX-BYTE CODE FOR BLOCK-ERASE

SST39VF1681 / SST39VF1682

T

BE

ADDRESS A

MS-0

AAA AAA555 AAA 555

CE#

OE#

T

WP

WE#

DQ

7-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) BA

= Block Address

X

A

= Most Significant Address

MS

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

or V

but no other value.

IL

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

BA

X

55 3055AA 80 AA

1243 F08.0

16

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

SIX-BYTE CODE FOR SECTOR-ERASE

Preliminary Specifications

T

SE

ADDRESS A

MS-0

AAA AAA555 AAA 555

CE#

OE#

T

WP

WE#

DQ

7-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.) SA

= Sector Address

X

A

= Most Significant Address

MS

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

SA

X

55 5055AA 80 AA

1243 F9.0

17

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

ADDRESS A

MS-0

AAA AAA555 0000 0001

CE#

OE#

T

WP

WE#

T

WPH

DQ

7-0

55AA 90

SW0 SW1 SW2

Note: Device ID - See Table 3 on page 5

A

= Most Significant Address

MS

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

BF

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

Device ID

1243 F10.1

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A

MS-0

555 AAAAAA

CE#

OE#

T

WP

WE#

T

WPH

DQ

7-0

55AA 98

SW0 SW1 SW2

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

FIGURE 12: CFI QUERY ENTRY AND REA D

T

IDA

T

AA

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

1243 F11.1

18

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

Preliminary Specifications

ADDRESS A

MS-0

DQ

7-0

AAA AAA555

AA 55 F0

CE#

OE#

T

WP

WE#

SW0 SW1 SW2

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

but no other value.

IH,

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

T

WHP

T

IDA

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

1243 F12.1

ADDRESS A

MS-0

AAA AAA555

CE#

OE#

WE#

DQ

7-0

Note: AMS = Most Significant Address

A

= A20 for SST39VF168x

MS

WP# must be held in proper logic state (V X can be V

IL

or V

FIGURE 14: SEC ID ENTRY

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

T

WP

T

WPH

55AA 88

SW0 SW1 SW2

but no other value.

IH,

T

IDA

T

AA

or VIH) 1 µs prior to and 1 µs after the command sequence.

IL

1243 F13.0

19

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Preliminary Specifications

T

RP

RST#

T

CE#/OE#

FIGURE 15: R ST# T IM IN G DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

T

RP

RHR

1243 F14.0

RST#

T

RY

CE#/OE#

End-of-Write Detection

(Toggle-Bit)

FIGURE 16: R ST# T IM IN G DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

1243 F15.0

20

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

V

IHT

Preliminary Specifications

V

ILT

AC test inputs are driven at V for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

1243 F16.0

(0.1 VDD) for a logic “0”. Measurement ref erence points

IL T

Note: V

- V

INPUT

OUTPUT

INPUT

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

1243 F17.0

FIGURE 18: A TEST LOAD EXAMPLE

C

L

21

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Start

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: A0H Address: AAAH

X can be VIL or VIH, but no other value

FIGURE 19: BYTE-PROGRAM ALGORITHM

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1243 F18.0

22

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Preliminary Specifications

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE, TSE

or T

BE

Program/Erase

Completed

No

Toggle Bit

Program/Erase

Initiated

Read word

Read same

word

Does DQ

6

match?

Ye s

No

Data# Polling

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Ye s

Program/Erase

Completed

Program/Erase

Completed

1243 F19.0

FIGURE 20: WAIT OPTIONS

23

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

CFI Query Entry

Command Sequence

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 98H

Address: AAAH

Wait T

IDA

Sec ID Query Entry

Command Sequence

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 88H Address: AAAH

Wait T

IDA

Software Product ID Entry

Command Sequence

Load data: AAH Address: AAAH

Load data: 55H

Address: 555H

Load data: 90H

Address: 5555H

Wait T

IDA

Read CFI data

X can be VIL or VIH, but no other value

Read Sec ID

FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS

Read Software ID

1243 F20.0

24

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

Software ID Exit/CFI Exit/Sec ID Exit

Preliminary Specifications

Command Sequence

Load data: AAH Address: AAAH

Load data: 55H

Address: 555H

Load data: F0H Address: AAAH

Wait T

IDA

Return to normal

operation

X can be VIL or V

Load data: F0H

Address: XXH

Wait T

Return to normal

operation

but no other value

IH,

IDA

1243 F21.0

FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS

25

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Chip-Erase

Command Sequence

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 80H Address: AAAH

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Sector-Erase

Command Sequence

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 80H Address: AAAH

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Block-Erase

Command Sequence

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 80H Address: AAAH

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: 10H Address: AAAH

Wait T

SCE

Chip erased

to FFFFH

Load data: 50H

Address: SA

Wait T

X

SE

Sector erased

to FFFFH

X can be VIL or VIH, but no other value

Load data: 30H

Address: BA

Wait T

X

BE

Block erased

to FFFFH

1243 F22.0

FIGURE 23: ERASE COMMAND SEQUENCE

26

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

PRODUCT ORDERING INFORMATION

SST 39 VF 1681 - 70 - 4C - B3K E

XX

XXXXXX -XXX -XX-XXX X

Preliminary Specifications

Environmental Attribute

E = non-Pb

Package Modifier

K = 48 leads

Package Type

B3 = TFBGA (6mm x 8mm, 0.8mm pitch) E = TSOP (type1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns 90 = 90 ns

Hardware Block Protection

1 = Bottom Boot-Block 2 = Top Boot-Block

Device Density

168 = 16 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

Valid Combinations for SST39VF1681

SST39VF1681-70-4C-EK SST39VF1681-70-4C-B3K SST39VF1681-70-4C-EKE SST39VF1681-70-4C-B3KE

SST39VF1681-70-4I-EK SST39VF1681-70-4I-B3K SST39VF1681-70-4I-EKE SST39VF1681-70-4I-B3KE SST39VF1681-90-4I-EK SST39VF1681-90-4I-EKE

Valid Combinations for SST39VF1682

SST39VF1682-70-4C-EK SST39VF1682-70-4C-B3K SST39VF1682-70-4C-EKE SST39VF1682-70-4C-B3KE

SST39VF1682-70-4I-EK SST39VF1682-70-4I-B3K SST39VF1682-70-4I-EKE SST39VF1682-70-4I-B3KE SST39VF1682-90-4I-EK SST39VF1682-90-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

27

Preliminary Specifications

PACKAGING DIAGRAMS

Pin # 1 Identifier

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

1.05

0.95

0.50

BSC

0.27

12.20

11.80

0.17

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

20.20

19.80

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK

0.15

0.05

DETAIL

1.20 max.

0˚- 5˚

0.70

0.50

1mm

48-tsop-EK-8

28

16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682

8.00 ± 0.20

6

5

4

3

2

1

A B C D E F G H

6.00 ± 0.20

4.00

0.80

BOTTOM VIEWTOP VIEW

5.60

0.80

H G F E D C B A

Preliminary Specifications

0.45 ± 0.05 (48X)

6

5

4

3

2

1

A1 CORNER

SIDE VIEW

SEATING PLANE

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1.10 ± 0.10

0.12

0.35 ± 0.05

A1 CORNER

1mm

48-tfbga-B3K-6x8-450mic-4

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE: B3K

TABLE 16: R

Number Description Date

00 01 02

EVISION HISTORY

• Initial release

• Change product number from 166x to 168x

• Added B3K package and associated MPNs (See page 27)

May 2003

Sep 2003

Oct 2003

• Removed 90 ns Commercial temperature for the EK and EKE packages

03

• 2004 Data Book

Nov 2003

• Updated B3K package diagram

Silicon Storage Technolog y, Inc. • 1171 Sonora Court • Sunnyval e , CA 940 86 • Telephone 408-73 5-91 10 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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Datasheet SST39VF1681, SST39VF1682 Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual