Datasheet SST39VF1601, SST39VF3201, SST39VF1602, SST39VF3202 Datasheet

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The SST39VF1601/1602 and SST39VF3201/3202 devices are 1M x16 and 2M x16, respectively, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF1601/1602/ 3201/3202 write (Program or Erase) with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pinouts for x16 memories.

Features

Not recommended for new designs. Please use SST39VF1601C and SST39VF3201B.

16 Mbit / 32 Mbit / (x16) Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

• Organized as 1M x16: SST39VF1601/1602 2M x16: SST39VF3201/3202

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord)

for SST39VF1602/3202

– Bottom Block-Protection (bottom 32 KWord)

for SST39VF1601/3201

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

–70ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPPGeneration

• End-of-Write Detection

– Toggle Bits – Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (6mm x 8mm)

• All devices are RoHS compliant

www.microchip.com

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Product Description

The SST39VF160x and SST39VF320x devices are 1M x16 and 2M x16, respectively, CMOS MultiPurpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF160x/320x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories.

Featuring high performance Word-Program, the SST39VF160x/320x devices provide a typical WordProgram time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF160x/320x devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF160x/320x are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pin assignments.

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Block Diagram

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Memory Address

WE# WP#

RESET#

Address Buffer Latches

CE# OE#

Control Logic

Figure 1: Functional Block Diagram

X-Decoder

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

-DQ

DQ

15

0

1223 B1.0

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Pin Assignment

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

SST39VF3201/3202

A15 A14 A13 A12 A11 A10

A9 A8

A19

A20

WE#

RST#

NC

WP#

NC A18 A17

A7 A6 A5 A4 A3 A2 A1

SST39VF1601/1602

A15 A14 A13 A12 A11 A10

A9 A8

A19

NC

WE#

RST#

NC

WP#

NC A18 A17

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard Pinout

Figure 2: Pin Assignments for 48-lead TSOP

Top View

Die Up

SST39VF160x/320x

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

1223 48-tsop P01.4

A16 NC V

SS

DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DD

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V

SS

CE# A0

TOP VIEW (balls facing down)

SST39VF1601/1602

6

A13

5

4

3

2

1

A9

WE#

NC

A7

A3

A12

A8

RST#

WP#

A17

A4

A14

A10

NC

A18

A6

A2

A15

A11

A19

NC

A5

A1

A16

DQ7

DQ5

DQ2

DQ0

A0

NC

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

V

DD

DQ11

DQ9

OE#

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

6

5

4

3

2

1

ABCDEFGH

1223 48-tfbga B3K P02.0

TOP VIEW (balls facing down)

SST39VF3201/3202

A13

A12

A14

A15

A16

NC

DQ15

A9

A8

A10

A11

DQ7

DQ14

DQ13

WE#

RST#

NC

A19

DQ5

DQ12

V

DD

NC

WP#

A18

A20

DQ2

DQ10

DQ11

A7

A17

A6

A5

DQ0

DQ8

DQ9

A3

A4

A2

A1

A0

CE#

OE#

ABCDEFGH

1223 48-tfbga B3K P02a.2

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

Figure 3: pin assignments for 48-ball TFBGA

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Table 1: Pin Description

Symbol Pin Name Functions

A

DQ

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

V

NC No Connection Unconnected pins.

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

1

-A0Address Inputs To provide memory addresses.

MS

-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

15

DD

SS

1. AMS= Most significant address

Power Supply To provide power supply voltage: 2.7-3.6V

Ground

AMS=A19for SST39VF1601/1602, and A20for SST39VF3201/3202

During Sector-Erase A During Block-Erase A

MS-A15

address lines will select the sector.

MS-A11

address lines will select the block.

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

grounded.

T1.2 25028

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Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF160x/320x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDDactive read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical I active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF160x/320x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

DD

Word-Program Operation

The SST39VF160x/320x are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39VF160x/320x offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11

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for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blocks will output DQ2toggling and DQ6at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence.

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Chip-Erase Operation

The SST39VF160x/320x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low.

Write Operation Status Detection

The SST39VF160x/320x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

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Data# Polling (DQ7)

When the SST39VF160x/320x are in the internal Program operation, any attempt to read DQ7will produce the complement of the true data. Once the Program operation is completed, DQ7will produce true data. Note that even though DQ7may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is completed, DQ7will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6will toggle.

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6to check whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.

Table 2: Write Operation Status

Status DQ

Normal Operation Standard Program DQ7# Toggle No Toggle

Standard Erase 0 Toggle Toggle

Erase-Suspend Mode Read from Erase-Suspended Sector/Block 1 1 Toggle

Read from Non- Erase-Suspended Sector/Block Data Data Data

Program DQ7# Toggle N/A

Note: DQ7and DQ2require a valid address when reading status information.

Data Protection

The SST39VF160x/320x provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

7

DQ

6

DQ

2

T2.0 25028

VDDPower Up/Down Detection: The Write operation is inhibited when VDDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

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Hardware Block Protection

The SST39VF1602/3202 support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF1601/3201 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table

3. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block.

Table 3: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

Top Boot Block

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

SST39VF1601/3201 000000H-007FFFH

SST39VF1602 0F8000H-0FFFFFH

SST39VF3202 1F8000H-1FFFFFH

T3.0 25028

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T no internal Program/Erase operation is in progress, a minimum period of T is driven high before a valid Read can take place (see Figure 16).

The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

any in-progress operation will terminate and return to Read mode. When

RP,

Software Data Protection (SDP)

The SST39VF160x/320x provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within T sequence.

The contents of DQ15-DQ8can be VILor VIH, but no other value, during any SDP command

RC.

Common Flash Memory Interface (CFI)

The SST39VF160x/320x also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

is required after RST#

RHR

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Product Identification

The Product Identification mode identifies the devices as the SST39VF1601, SST39VF1602, SST39VF3201, or SST39VF3202, and manufacturer as SST. This mode may be accessed software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 22 for the Software ID Entry command sequence flowchart.

Table 4: Product Identification

Manufacturer’s ID 0000H BFH

Device ID

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Address Data

SST39VF1601 0001H 234BH

SST39VF1602 0001H 234AH

SST39VF3201 0001H 235BH

SST39VF3202 0001H 235AH

T4.2 25028

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures 22 and 23 for flowcharts.

Security ID

The SST39VF160x/320x devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details.

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Operations

Table 5: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read V

Program V

Erase V

Standby V

Write Inhibit X V

Product Identification

Software Mode V

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

IL

IH

XXV

IL

1. X can be VILor VIH, but no other value.

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

V

IH

V

IH

X X High Z X

IL

V

IL

V

IL

D

IH

OUT

V

D

IL

IN

V

1

X

IL

X High Z/ D

High Z/ D

IH

V

IH

OUT

A

IN

A

IN

Sector or block address, XXH for Chip-Erase

X

See Table 6

T5.0 25028

Table 6: Software Command Sequence

Command Sequence

Word-Program

Sector-Erase

Block-Erase

Chip-Erase

Erase-Suspend

Erase-Resume

Query Sec ID

User Security ID Word-Program

User Security ID Program Lock-Out

Software ID Entry

CFI Query Entry

Software ID

9,10

Exit Sec ID Exit

Software ID

9,10

Exit /CFI Exit/Sec ID Exit

1. Address format A14-A0(Hex).

5

7,8

/CFI Exit/

Addresses A15-A19can be VILor VIH, but no other value, for Command sequence for SST39VF1601/1602, Addresses A15-A20can be VILor VIH, but no other value, for Command sequence for SST39VF3201/3202,

1st Bus

Write Cycle

1

Addr

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data

5555H AAH

XXXXHB0H

XXXXH30H

5555H AAH

XXH F0H

2nd Bus

Write Cycle

2AAAH

55H 5555H A0H WA3Data

55H 5555H 80H 5555HAAH

55H 5555H 88H

55H 5555H A5H WA6Data

55H 5555H 85H XXH60000

55H 5555H 90H

55H 5555H 98H

55H 5555H F0H

3rd Bus

Write Cycle

4th Bus

Write Cycle

H

5th Bus

Write Cycle

2AAAH

6th Bus

Write Cycle

55H SA

55H BA

4

30H

X

4

50H

X

55H 5555H10H

T6.6 25028

2

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16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

2. DQ15-DQ8can be VILor VIH, but no other value, for Command sequence

3. WA = Program Word address

4. SAXfor Sector-Erase; uses AMS-A11address lines BAX, for Block-Erase; uses AMS-A15address lines AMS= Most significant address AMS=A19for SST39VF1601/1602 and A20for SST39VF3201/3202

5. With AMS-A4= 0; Sec ID is read with A3-A0,

Lock Status is read with A7-A0= 0000FFH. Unlocked: DQ3= 1 / Locked: DQ3=0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With AMS-A1=0; SST Manufacturer ID = 00BFH, is read with A0=0,

AMS= Most significant address AMS=A19for SST39VF1601/1602 and A20for SST39VF3201/3202

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

SST ID is read with A3= 0 (Address range = 000000H to 000007H), User ID is read with A3= 1 (Address range = 000010H to 000017H).

SST39VF1601 Device ID = 234BH, is read with A0=1, SST39VF1602 Device ID = 234AH, is read with A0=1, SST39VF3201 Device ID = 235BH, is read with A SST39VF3202 Device ID = 235AH, is read with A

0

=1, =1,

Table 7: CFI Query Identification String1for SST39VF160x/320x

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

1. Refer to CFI publication 100 for more details.

T7.1 25028

12

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Microchip Technology Company

Table 8: System Interface Information for SST39VF160x/320x

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Address Data Data

1BH 0027H V

1CH 0036H V

1DH 0000H V

1EH 0000H V

1FH 0003H Typical time out for Word-Program 2

20H 0000H Typical time out for min. size buffer program 2

21H 0004H Typical time out for individual Sector/Block-Erase 2

22H 0005H Typical time out for Chip-Erase 2

23H 0001H Maximum time out for Word-Program 2

24H 0000H Maximum time out for buffer program 2

25H 0001H Maximum time out for individual Sector/Block-Erase 2

26H 0001H Maximum time out for Chip-Erase 2

Min (Program/Erase)

DD

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

Max (Program/Erase)

DD

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

min. (00H = no VPPpin)

PP

max. (00H = no VPPpin)

PP

ms)

N

µs (23= 8 µs)

N

ms (25=32ms)

N

times typical (21x23=16µs)

N

times typical

N

times typical (21x25=64ms)

µs (00H = not supported)

N

ms (24=16ms)

N

times typical (21x24=32

T8.3 25028

Table 9: Device Geometry Information for SST39VF1601/1602

Address Data Data

N

27H 0015H Device size = 2

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y+1=Number of sectors; z x 256B = sector size)

2EH 0001H y = 511+1=512sectors (01FF = 511

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 001FH Block Information (y+1=Number of blocks; z x 256B = block size)

32H 0000H y = 31+1=32blocks(001F = 31)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

Bytes (15H = 21; 221= 2 MByte)

N

(00H = not supported)

T9.0 25028

13

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Microchip Technology Company

Table 10:Device Geometry Information for SST39VF3201/3202

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Address Data Data

N

27H 0016H Device size = 2

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y+1=Number of sectors; z x 256B = sector size)

2EH 0003H y = 1023+1=1024 (03FFH = 1023)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H 003FH Block Information (y+1=Number of blocks; z x 256B = block size)

32H 0000H y = 63+1=64blocks(003FH = 63)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

Bytes (16H = 22; 222= 4 MByte)

N

(00H = not supported)

T10.2 25028

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Microchip Technology Company

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias ............................................. -55°C to +125°C

Storage Temperature ................................................ -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential .....................................-0.5V to 13.2V

Package Power Dissipation Capability (TA= 25°C) .................................. 1.0W

Surface Mount Solder Reflow Temperature1...........................260°C for 10 seconds

Output Short Circuit Current2.................................................. 50mA

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 11:Operating Range

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

Table 12:AC Conditions of Test

Input Rise/Fall Time Output Load

5ns C

1. See Figures 18 and 19

1

=30pF

L

DD

T11.1 25028

T12.1 25028

15

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Microchip Technology Company

Table 13:DC Operating Characteristics VDD= 2.7-3.6V

Symbol Parameter

I

DD

I

SB

I

ALP

I

LI

I

LIW

I

LO

V

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

1

Limits

Test ConditionsMin Max Units

Power Supply Current Address input=V

Read

V

3

18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

DD=VDD

Max

Program and Erase 35 mA CE#=WE#=VIL, OE#=V

Standby VDDCurrent 20 µA CE#=V

Auto Low Power 20 µA CE#=V

IHC,VDD=VDD

ILC,VDD=VDD

All inputs=V

SS

or V

Input Leakage Current 1 µA VIN=GND to VDD,VDD=VDDMax

Input Leakage Current on WP# pin and RST#

Output Leakage Current 10 µA V

IL

ILC

IH

IHC

OL

OH

Input Low Voltage 0.8 V VDD=VDDMin

Input Low Voltage (CMOS) 0.3 V VDD=VDDMax

Input High Voltage 0.7V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDDMax

Output Low Voltage 0.2 V IOL=100 µA, VDD=VDDMin

Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDDMin

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VDD= 3V. Not 100% tested.

2. See Figure 18

3. The IDDcurrent listed is typically less than 2mA/MHz, with OE# at V

10 µA WP#=GND to VDDor RST#=GND to

V

DD

=GND to VDD,VDD=VDDMax

OUT

VVDD=VDDMax

Typical VDDis 3V.

IH.

ILT/VIHT

DD,

2

, at f=5 MHz,

IH

Max

WE#=V

IHC

T13.8 25028

Table 14:Recommended System Power-up Timings

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

Table 15:Capacitance (T

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

Power-up to Program/Erase Operation 100 µs

= 25°C, f=1 MHz, other pins open)

A

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

=0V 12pF

I/O

Input Capacitance VIN=0V 6pF

Table 16:Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

1,2

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. N

END

result in a higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would

DD

mA JEDEC Standard 78

T14.0 25028

T15.0 25028

T16.2 25028

16

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Microchip Technology Company

AC Characteristics

Table 17:Read Cycle Timing Parameters VDD= 2.7-3.6V

Symbol Parameter Min Max Units

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1

T

RP

1

T

RHR

1,2

T

RY

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations.

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Read Cycle Time 70 ns

Chip Enable Access Time 70 ns

Address Access Time 70 ns

Output Enable Access Time 35 ns

CE# Low to Active Output 0 ns

OE# Low to Active Output 0 ns

CE# High to High-Z Output 20 ns

OE# High to High-Z Output 20 ns

Output Hold from Address Change 0 ns

RST# Pulse Width 500 ns

RST# High before Read 50 ns

RST# Pin Low to Read Mode 20 µs

T17.3 25028

Table 18:Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

1

T

WPH

1

T

CPH

T

DS

1

T

DH

1

T

IDA

T

SE

T

BE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Word-Program Time 10 µs

Address Setup Time 0 ns

Address Hold Time 30 ns

WE# and CE# Setup Time 0 ns

WE# and CE# Hold Time 0 ns

OE# High Setup Time 0 ns

OE# High Hold Time 10 ns

CE# Pulse Width 40 ns

WE# Pulse Width 40 ns

WE# Pulse Width High 30 ns

CE# Pulse Width High 30 ns

Data Setup Time 30 ns

Data Hold Time 0 ns

Software ID Access and Exit Time 150 ns

Sector-Erase 25 ms

Block-Erase 25 ms

Chip-Erase 50 ms

T18.1 25028

17

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

ADDRESS A

MS-0

CE#

OE#

T

V

IH

OLZ

WE#

T

CLZ

DQ

15-0

HIGH-Z

Note: AMS= Most significant address

A

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

Figure 4: Read Cycle Timing Diagram

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

CHZ

HIGH-Z

DATA VALI DDATA VALI D

1223 F03.3

INTERNAL PROGRAM OPERATION STARTS

T

BP

ADDRESS A

MS-0

5555 2AAA 5555 ADDR

T

AH

T

WP

T

DH

WE#

T

AS

T

WPH

T

DS

OE#

T

CH

CE#

T

CS

DQ

15-0

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

WORD

(ADDR/DATA)

Note: AMS= Most significant address

=A19for SST39VF1601/1602 and A20for SST39VF3201/3202

A

MS

WP# must be held in proper logic state (V X can be V

or V

IL

but no other value

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

Figure 5: WE# Controlled Program Cycle Timing Diagram

1223 F04.4

18

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Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

INTERNAL PROGRAM OPERATION STARTS

T

BP

ADDRESS A

DQ

MS-0

CE#

OE#

WE#

15-0

T

AS

5555 2AAA 5555 ADDR

T

AH

T

CP

T

CPH

T

CS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

Note: AMS= Most significant address

A WP# must be held in proper logic state (V X can be V

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

but no other value

or V

IL

IH,

T

DH

T

DS

T

CH

WORD

(ADDR/DATA)

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

Figure 6: CE# Controlled Program Cycle Timing Diagram

ADDRESS A

MS-0

CE#

OE#

WE#

T

OEH

T

CE

T

OE

1223 F05.4

T

OES

DQ

7

Note: AMS= Most significant address

DATA DATA# DATA # DATA

A

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

1223 F06.3

Figure 7: Data# Polling Timing Diagram

19

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

ADDRESS A

MS-0

CE#

OE#

WE#

DQ6and DQ

T

CE

T

OEH

2

Note: AMS= Most significant address

A

MS=A19

for SST39VF1601/1602 and A20for SST39VF3201/3202

Figure 8: Toggle Bits Timing Diagram

SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS A

MS-0

5555 2AAA 2AAA5555 5555

T

OES

1223 F07.4

SCE

T

OE

TWO READ CYCLES

WITH SAME OUTPUTS

5555

CE#

OE#

T

WP

WE#

DQ

15-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 17)

= Most significant address

A

MS

A WP# must be held in proper logic state (V X can be V

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

or V

IL

but no other value

IH,

) 1 µs prior to and 1 µs after the command sequence

IH

XX55 XX10XX55XXAA XX80 XXAA

Figure 9: WE# Controlled Chip-Erase Timing Diagram

1223 F08.5

20

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

SIX-BYTE CODE FOR BLOCK-ERASE

ADDRESS A

MS-0

5555 2AAA 2AAA5555 5555

CE#

OE#

T

WP

WE#

DQ

15-0

XX55 XX50XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 17)

= Block Address

BA

X

= Most significant address

A

MS

A WP# must be held in proper logic state (V X can be V

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

or V

IL

but no other value

IH,

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

Figure 10:WE# Controlled Block-Erase Timing Diagram

BA

T

BE

X

1223 F09.5

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESS A

MS-0

5555 2AAA 2AAA5555 5555

CE#

OE#

T

WP

WE#

DQ

15-0

XX55 XX30XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Sector-Erase operation.The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 17)

= Sector Address

SA

X

= Most significant address

A

MS

A WP# must be held in proper logic state (V X can be V

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

or VIH, but no other value

IL

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

Figure 11:WE# Controlled Sector-Erase Timing Diagram

SA

T

SE

X

1223 F10.5

21

A

Microchip Technology Company

1

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Three-Byte Sequence for Software ID Entry

ADDRESS A

14-0

5555 2AAA 5555 0000 0001

CE#

OE#

T

WP

WE#

T

WPH

DQ

15-0

SW0 SW1 SW2

Note: Device ID = 234BH for 39VF1601, 234AH for 39VF1602, 235BH for 39VF3201, and 235AH for 39VF3202,

WP# must be held in proper logic state (V X can be V

or V

IL

but no other value

IH,

Figure 12:Software ID Entry and Read

Three-Byte Sequence for CFI Query Entry

ADDRESS A

14-0

5555 2AAA 5555

T

IDA

T

AA

00BF

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

Device IDXX55XXAA XX90

CE#

OE#

T

IDA

T

AA

1223 F12.1

DQ

T

WP

WE#

T

WPH

15-0

SW0 SW1 SW2

Note: WP# must be held in proper logic state (VILor VIH) 1 µs prior to and 1 µs after the command sequence

X can be V

XX55XXAA XX98

or V

IL

IH

,

but no other value

Figure 13:CFI Query Entry and Read

22

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A

DQ

14-0

15-0

CE#

OE#

WE#

5555 2AAA 5555

XXAA XX55 XXF0

T

WP

T

WHP

SW0 SW1 SW2

Note: WP# must be held in proper logic state (VILor VIH) 1 µs prior to and 1 µs after the command sequence

X can be V

or V

IL

but no other value

IH,

Figure 14:Software ID Exit/CFI Exit

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A

MS-0

5555 2AAA 5555

T

IDA

1223 F13.0

CE#

OE#

T

IDA

T

AA

or VIH) 1 µs prior to and 1 µs after the command sequence

IL

1223 F20.2

DQ

T

WP

WE#

15-0

SW0 SW1 SW2

Note: AMS= Most significant address

A WP# must be held in proper logic state (V X can be V

for SST39VF1601/1602 and A20for SST39VF3201/3202

MS=A19

IL

XX55XXAA XX88

but no other value.

or V

IH,

T

WPH

Figure 15:SecIDEntry

23

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Microchip Technology Company

Figure 16:RST# Timing Diagram (When no internal operation is in progress)

RST#

CE#/OE#

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

T

RP

T

RHR

T

RP

1223 F22.1

RST#

CE#/OE#

T

RY

End-of-Write Detection

(Toggle-Bit)

Figure 17:RST# Timing Diagram (During Program or Erase operation)

V

IHT

V

OT

(0.1 VDD) for a

ILT

1223 F14.0

V

ILT

AC test inputs are driven at V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

REFERENCE POINTS OUTPUTINPUT

logic “0”. Measurement reference points for inputs and outputs are VIT(0.5 VDD) and VOT(0.5 VDD). Input rise and fall times (10%  90%) are <5 ns.

Note: VIT-V

INPUT

VOT-V V

IHT-VINPUT

V

ILT-VINPUT

OUTPUT

Figure 18:AC Input/Output Reference Waveforms

1223 F23.0

Test

Test HIGH Test LOW Test

TO TESTER

TO DUT

C

L

1223 F15.0

Figure 19:A Test Load Example

24

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16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

X can be VILor VIH, but no other value

Figure 20:Word-Program Algorithm

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1223 F16.0

25

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE,TSE

or T

BE

Program/Erase

Completed

No

Toggle Bit

Program/Erase

Initiated

Read word

Read same

word

Does DQ

match

6

Ye s

No

Data# Polling

Program/Erase

Initiated

Read DQ

Is DQ7=

true data

Program/Erase

Completed

7

Ye s

Figure 21:Wait Options

Program/Erase

Completed

1223 F17.0

26

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Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

CFI Query Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

Wait T

IDA

Sec ID Query Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX88H

Address: 5555H

Wait T

IDA

Software Product ID Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait T

IDA

Read CFI data

X can be VILor VIH, but no other value

Read Sec ID

Figure 22:Software ID/CFI Entry Command Flowcharts

Read Software ID

1223 F21.0

27

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Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Wait T

IDA

Return to normal

operation

X can be VILor VIH, but no other value

Load data: XXF0H

Address: XXH

Wait T

IDA

Return to normal

operation

1223 F18.1

Figure 23:Software ID/CFI Exit Command Flowcharts

28

A

Microchip Technology Company

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Chip-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Wait T

SCE

Chip erased

to FFFFH

Load data: XX30H

Address: SA

Wait T

Sector erased

to FFFFH

X can be VILor VIH, but no other value

X

SE

Load data: XX50H

Address: BA

Wait T

Block erased

to FFFFH

X

BE

1223 F19.0

Figure 24:Erase Command Sequence

29

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

A

Microchip Technology Company

Product Ordering Information

SST 39 VF 1601 - 70 - 4C - EKE

XX XX XXXX - XX - XX

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

-

XXX

Environmental Attribute

E1= non-Pb

Package Modifier

K = 48 balls or leads

Package Type

E = TSOP (type1, die up, 12mm x 20mm) B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Hardware Block Protection

1 = Bottom Boot-Block 2 = Top Boot-Block

Device Density

160 = 16 Mbit 320 = 32 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

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Microchip Technology Company

Valid Combinations for SST39VF1601

SST39VF1601-70-4C-EKE SST39VF1601-70-4C-B3KE SST39VF1601-90-4C-EKE SST39VF1601-90-4C-B3KE

SST39VF1601-70-4I-EKE SST39VF1601-70-4I-B3KE SST39VF1601-90-4I-EKE SST39VF1601-90-4I-B3KE

Valid Combinations for SST39VF1602

SST39VF1602-70-4C-EKE SST39VF1602-70-4C-B3KE SST39VF1602-90-4C-EKE SST39VF1602-90-4C-B3KE

SST39VF1602-70-4I-EKE SST39VF1602-70-4I-B3KE SST39VF1602-90-4I-EKE SST39VF1602-90-4I-B3KE

Valid Combinations for SST39VF3201

SST39VF3201-70-4C-EKE SST39VF3201-70-4C-B3KE SST39VF3201-90-4C-EKE SST39VF3201-90-4C-B3KE

SST39VF3201-70-4I-EKE SST39VF3201-70-4I-B3KE SST39VF3201-90-4I-EKE SST39VF3201-90-4I-B3KE

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Valid Combinations for SST39VF3202

SST39VF3202-70-4C-EKE SST39VF3202-70-4C-B3KE SST39VF3202-90-4C-EKE SST39VF3202-90-4C-B3KE

SST39VF3202-70-4I-EKE SST39VF3202-70-4I-B3KE SST39VF3202-90-4I-EKE SST39VF3202-90-4I-B3KE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combinations.

31

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Microchip Technology Company

Packaging Diagrams

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

1.05

0.95

Pin # 1 Identifier

0.50

BSC

0.27

12.20

11.80

0.17

18.50

18.30

1.20 max.

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

20.20

19.80

Figure 25:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

SST Package Code: EK

0.15

0.05

DETAIL

0°- 5°

0.70

0.50

1mm

48-tsop-EK-8

32

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Microchip Technology Company

6

5

4

3

2

1

ABCDEFGH

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

BOTTOM VIEWTOP VIEW

8.00 0.10

6.00 0.10

4.00

0.80

HGFEDCBA

5.60

0.80

0.45 0.05 (48X)

6

5

4

3

2

1

A1 CORNER

SIDE VIEW

SEATING PLANE

Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

1.10 0.10

0.12

0.35 0.05

A1 CORNER

48-tfbga-B3K-6x8-450mic-5

Figure 26:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

1mm

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Microchip Technology Company

©

Table 19:Revision History

16 Mbit / 32 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 SST39VF1602 / SST39VF3202

Not Recommended for New Designs

Number Description Date

00

01

02

03

04

05

• Initial release

• Corrected Pin 15 from A20 to NC for SST39VF160x in Figure 2 on

page 4

• Changed data sheet title

• 2004 Data Book

• Updated the B3K and B1K package diagrams

• Added non-Pb MPNs and removed footnote. (See page 31)

• Added RoHS compliance information on page 1 and in the “Product

Ordering Information” on page 30

• Corrected the solder temperature profile in “Absolute Maximum Stress Ratings” on page 15

• Changed product status from “Preliminary Specifications” to “Data Sheet”

• Removed 90 ns Read Access Time globally

• EOLed all lead (Pb) valid combinations. See S71223(02)

• EOLed SST39VF6401 and SST39VF6402. See S71223(03)

A

• Changed document status to “Not Recommended for New Designs”

• Applied new document format

• Released document under letter revision system

• Updated Spec number from S71223 to DS25028

Mar 2003

Apr 2003

Jun 2003

Nov 2003

Nov 2005

June 2008

Aug 2011

ISBN:978-1-61341-355-5

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

34

Datasheet SST39VF1601, SST39VF3201, SST39VF1602, SST39VF3202 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Product Description

Block Diagram

Pin Assignment

Table 1: Pin Description

Device Operation

Read

Word-Program Operation

Sector/Block-Erase Operation

Erase-Suspend/Erase-Resume Commands

Chip-Erase Operation

Write Operation Status Detection

Data# Polling (DQ7)

Toggle Bits (DQ6 and DQ2)

Table 2: Write Operation Status

Data Protection

Hardware Data Protection

Hardware Block Protection

Table 3: Boot Block Address Ranges

Hardware Reset (RST#)

Software Data Protection (SDP)

Common Flash Memory Interface (CFI)

Product Identification

Table 4: Product Identification

Product Identification Mode Exit/CFI Mode Exit

Security ID

Operations

Table 5: Operation Modes Selection

Table 6: Software Command Sequence

Table 8: System Interface Information for SST39VF160x/320x

Table 9: Device Geometry Information for SST39VF1601/1602

Table 10:Device Geometry Information for SST39VF3201/3202

Table 11:Operating Range

Table 12:AC Conditions of Test

Table 13:DC Operating Characteristics VDD= 2.7-3.6V

Table 14:Recommended System Power-up Timings

Table 16:Reliability Characteristics

AC Characteristics

Table 17:Read Cycle Timing Parameters VDD= 2.7-3.6V

Table 18:Program/Erase Cycle Timing Parameters

Product Ordering Information

Valid Combinations for SST39VF1601

Valid Combinations for SST39VF1602

Valid Combinations for SST39VF3201

Valid Combinations for SST39VF3202

Packaging Diagrams

Table 19:Revision History