Datasheet SST39VF080-90-4C-EK, SST39VF080-90-4C-EI, SST39VF080-90-4C-B3K, SST39VF080-90-4C-B3I, SST39VF080-70-4I-EK Datasheet (Silicon Storage Technology)
...Page 1
Data Sheet
©2001 Silicon Storage Technology, Inc.
S71146-03-000 6/01 396
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
8 Mbit / 16 Mbit (x8) Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
FEATURES:
• Organized as 1M x8 / 2M x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF080/016
– 2.7-3.6V for SST39VF080/016
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Ac ti ve Current: 15 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Block-Erase Capability
– Uniform 64 KByte blocks
• Fast Read Access Time:
– 55 ns for SST39LF080/016
– 70 and 90 ns for SST39VF080/ 016
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
15 seconds (typical) for SST39LF/VF080
30 seconds (typical) for SST39LF/VF016
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 40-lead TSOP (10mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST39LF/VF080 and SST39LF/VF016 devices are
1M x8 / 2M x8 CMOS Multi-Pur pose Fl ash (MPF) manufactured with SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick
oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39LF080/016 write (Program or Erase) with a 3.0-3.6V
power supply. The SST39VF080/016 write (Program or
Erase) with a 2.7-3.6V power supply. They conform to
JEDEC standar d pino uts f or x8 me mories .
Featuring high p erformance Byte-Program, the SST 39LF/
VF080 and SST39LF/VF016 devices provide a typical
Byte-Program time of 14 µsec. The devices use Toggle Bit
or Data# Polling to indicate the completion of Program
operation. To protect against inad vertent write, they have
on-chip hardware and So ftware Data Prot ection s chem es.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater th an 10 0 years .
The SST39LF/VF080 and SST39LF/VF016 devices are
suited for applications that require convenient and economical updating of program, configuration, or da ta memory.
For all system applicati ons, they significantly improve performance and reliability , while lowering power consumption.
They inherently use less energy during Erase and Program
than alternati ve flash technologies. The total energy consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash techn ology uses less current to pr ogram and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technolog ies . They also im prov e f le xibilit y while l ow ering the cost for program, data, and conf iguration storage
applications.
The SuperFlash te ch no logy pr ovid es fi xed Erase an d P r ogram times, independent o f the num be r of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times inc rease with accumul ated Erase/P rogram cycles .
To meet high density, surface mount requirements, the
SST39LF/VF080 a nd SST39LF/VF016 are offered in 40lead TSOP and 48-ba ll TFBGA packaging. Se e Figures 1
and 2 for pinouts.
SST39LF/VF080 / 0163.0 & 2.7V 8Mb / 16Mb (x8) MPF memories
Page 2
2
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands ar e written to the device
using standard mi croprocessor write sequen ces. A command is written by asse r ting WE# low whil e keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latche d on
the rising edge of WE# or CE#, whichever occurs first.
The SST39LF/VF080 and SST39LF/VF016 also have the
Auto Low Power mode which puts the device in a near
standby mode after da ta has been accessed with a valid
Read operation. This reduces the I
DD
active read current
from typically 15 mA to typically 4 µA. The Auto Low P o wer
mode reduces the typical I
DD
active read current to the
range of 1 mA/MHz of read cycle time. The device exits the
Auto Low Power mode with any addres s transi tion o r control signal transition used to initiate another Read cycle,
with no access time penalty. Note that the device does not
enter Auto Low Power mode after power-up with CE# held
steadily low until the first address transition or CE# is driven
high.
Read
The Read operation of the SST39LF/VF080 and
SST39LF/VF016 is controlled by CE# and OE#, both have
to be low for the system to obtain dat a from the outputs.
CE# is used for device selection. Whe n CE# is high, the
chip is dese lected and onl y standby power is cons umed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is hi gh. Refer to the Rea d cycle t iming
diagram for further details (Figure 3).
Byte-Program Operation
The SST39LF/VF080 and SST39LF/VF016 are programmed on a byte-by-byte basis. Before programming,
one must ensure that the sector, in which the byte which is
being programmed exists, is fully erased. The Program
operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load byte address and byte data. Dur i ng th e
Byte-Program operation, the addresses are latched on the
falling edge of either C E# or WE#, w hichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the inter nal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20
µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. Dur in g the P rogram operat ion, th e only valid reads
are Data# Polling and Toggle Bit. During the inte rnal Program operation, the host is free to perform additional tasks.
Any commands issued during the internal Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF /VF080 and SST39LF/VF016
offer both Sect or- Era se an d Block-Eras e mo de. Th e sec tor
architecture is based on uniform sector size of 4 KByte.
The Block-Erase mode is based on uniform block size of
64 KByte. The Secto r-Erase operation is ini tiated by executing a six-byte-command sequence with Sector-Erase
command (30H) and sector address (SA) in the last bus
cycle. The Block-Erase operation is initiated by executing a
six-byte-command seq uence with Block-Erase command
(50H) and block address (BA ) in the last bus cycle. The
sector or block address is latched on the falling edge of the
sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Era se operation begin s after t he sixth W E# puls e.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. Se e Figures 9
and 10 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39LF/VF080 and SST39LF/VF016 provide a
Chip-Erase operation, wh ich allows the user to erase the
entire memory array to the “1” state. This is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Eras e
operation begins with the rising edge of the sixt h WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is T oggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST39LF/VF080 and SST39LF/VF016 provide two
software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write
cycle time. The software detection includes two status bits:
Data# Polling (DQ
7
) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
Page 3
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
3
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
The actual completion of the nonvolatile write is asynchronous with the system ; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the c ompletion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ
7
or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39LF/VF080 and SST39LF/VF016 are in
the internal Program operation, any attempt to read DQ
7
will produce the co mplement of the true data. Once th e
Program operation is completed, DQ
7
will produce true
data. The device is then ready for the next operation. During intern al Erase ope ration, any atte mpt to re ad DQ
7
will
produce a ‘0’. Once the inter nal Erase operation is com-
pleted, DQ
7
will produce a ‘1’. The Data# Polling is valid
after the risin g e dge of four t h W E# (or CE # ) pul se for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of si x th WE # ( or
CE#) pulse. See Figure 6 for Data# Polling timing dia gram
and Figure 17 for a flowchart.
Toggle Bit (DQ6)
During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ
6
will produce alter nating 1s
and 0s, i.e., toggling between 1 and 0. W hen the internal
Program or Erase operat ion is c omplete d, the DQ
6
bit will
stop toggling. The device is the n re ady for the next ope ration. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operat ion. For Sector-,
Block-, or Chip-Erase, the T oggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diag ram and Figu re 17 f or a fl owc hart.
Data Protection
The SST39LF/VF080 and SST39LF/VF016 provide both
hardware and software features to protect nonvolatile dat a
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of l ess th an 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode:
Forcing OE# low, CE# high, or WE#
high will inhibit the W r it e operation. This prevents inadvertent writes during p ow er-u p or po wer- dow n.
Software Data Protection (SDP)
The SST39LF/VF080 and SST39LF/VF016 provide the
JEDEC approved Software Data Protecti on schem e for all
data alteration operations, i.e., Program and Erase. Any
Program operation req uires t he inc lusion of the thr ee-byte
sequence. The three-byte load sequence is used to initiate
the Program operation, p roviding optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of si x-byte sequence. The SS T39LF/VF080 an d
SST39LF/VF016 devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid commands will abo r t the device to read
mode within T
RC
.
Common Flash Memory Interface (CFI)
The SST39LF/VF080 and SST39LF/VF016 also contain
the CFI information to describe the characteri stics of the
device. In order to enter the CFI Quer y mode, the system
must write three-byte sequence, same as product ID entry
command with 98H (CFI Query command) to address
5555H in the la st byte sequenc e. Once the device en ters
the CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 8. The system must
write the CFI E xit co mmand t o retur n to Read mo de from
the CFI Query mode.
Page 4
4
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
Product Identification
The Product Identification mode identifies the device as the
SST39LF080, SST39VF080, SST39LF016, and
SST39VF016 and manufacturer as SST. This mode may
be accessed by software o perations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when usi ng multipl e manufacturers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry a nd Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flo wchart.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identifica tion mode must be exited. Exi t is acco mplished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnorma lly, e.g.,
not read correctly. Please note that the Soft ware ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform and Figure 18 for a
flowchart.
TABLE 1: P
RODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39LF/VF080 0001H D8H
SST39LF/VF016 0001H D9H
T1.2 396
Y-Decoder
I/O Buffers and Data Latches
396 ILL B1.2
Address Buffer & Latches
X-Decoder
DQ7 - DQ
0
Memory
Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
FUNCTIONAL BLOCK DIAGRAM
Page 5
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
5
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP
FIGURE 2: P
IN ASSIGNMENTS FOR 48-BALL TFBGA
SST39LF/VF080 SST39LF/VF016
A16
A15
A14
A13
A12
A11
A9
A8
WE#
NC
NC
NC
A18
A7
A6
A5
A4
A3
A2
A1
A16
A15
A14
A13
A12
A11
A9
A8
WE#
NC
NC
NC
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
DD
V
DD
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
396 ILL F01.2
Standard Pinout
T op Vie w
Die Up
SST39LF/VF160 SST39LF/VF080
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
DD
V
DD
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
A18
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
A17
A19
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
A20
DQ6
V
DD
V
DD
NC
OE#
V
SS
DQ7
DQ4
NC
DQ1
V
SS
396 ILL F21.1
SST39LF/VF016
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
A18
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
A17
A19
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
V
DD
V
DD
NC
OE#
V
SS
DQ7
DQ4
NC
DQ1
V
SS
396 ILL F20.1
SST39LF/VF080
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
Page 6
6
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
A
MS
1
-A
0
Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines w ill s ele ct the
sector. During Block-Erase A
MS-A16
address lines will select the block.
DQ
7
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V
DD
Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF080/016
2.7-3.6V for SST39VF080/016
V
SS
Ground
NC No Connection Unconnected pins.
T2.3 396
1. AMS = Most significant address
A
MS
= A19 for SST39LF/VF080 and A20 for SST39LF/VF016
TABLE 3: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read V
IL
V
IL
V
IH
D
OUT
A
IN
Program V
IL
V
IH
V
IL
D
IN
A
IN
Erase V
IL
V
IH
V
IL
X
1
1. X can be VIL or VIH, but no other value.
Sector or Block address,
XXH for Chip-Erase
Standby V
IH
XXHigh Z X
Write Inhibit X V
IL
XHigh Z/ D
OUT
X
XXV
IH
High Z/ D
OUT
X
Product Identification
Software Mode V
IL
V
IL
V
IH
See Table 4
T3.4 396
Page 7
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
7
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data
Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA
2
Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA
X
3
30H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA
X
3
50H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry
4,5
5555H AAH 2AAAH 55H 5555H 90H
CFI Query Entry
4
5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit
6
/
CFI Exit
XXH F0H
Software ID Exit
6
/
CFI Exit
5555H AAH 2AAAH 55H 5555H F0H
T4.3 396
1. Address format A14-A0 (Hex),
Addresses A
15
- A19 can be VIL or VIH, but no other value, for the Command sequenc e for SST39LF/VF080.
Addresses A
15
- A20 can be VIL or VIH, but no other value, for the Command sequenc e for SST39LF/VF016.
2. WA = Program Byte address
3. SA
X
for Sector-Erase; uses AMS-A12 address lines
BA
X
, for Block-Erase; uses AMS-A16 address lines
A
MS
= Most significant address
A
MS
= A19 for SST39LF/VF080 and A20 for SST39LF/VF016
4. The device does not remain in Software Product ID Mode if powered down.
5. With A
MS-A1
=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,
SST39LF/VF080 Device ID = D8H, is read with A
0
= 1
SST39LF/VF016 Device ID = D9H, is read with A
0
= 1
6. Both Software ID Exit operations are equivalent
TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/ VF080 AND SS T39LF/VF016
1. Refer to CFI publication 100 for more details.
Address Data Data
10H 51H Query Unique ASCII string “QRY”
11H 52H
12H 59H
13H 01H Primary OEM command set
14H 07H
15H 00H Address for Primary Extended Table
16H 00H
17H 00H Alternate OEM command set (00H = none exists)
18H 00H
19H 00H Address for Alternate OEM extended Table (00H = none exits)
1AH 00H
T5.3 396
Page 8
8
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39VF 320/64 0
Address Data Data
1BH 27H
1
VDD Min (Program/Erase)
30H
1
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 36H V
DD
Max (Program/Erase)
DQ
7
-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 00H V
PP
min. (00H = no VPP pin)
1EH 00H V
PP
max. (00H = no VPP pin)
1FH 04H Typical time out for Byte-Program 2
N
µs (24 = 16 µs)
20H 00H Typical time out for min. size buffer program 2
N
µs (00H = not supported)
21H 04H Typical time out for individual Sector/Bloc k -Er as e 2
N
ms (24 = 16 ms)
22H 06H Typical time out for Chip-Erase 2
N
ms (26 = 64 ms)
23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)
24H 00H Maximum time out for buffer program 2N times typical
25H 01H Maximum time out for individual Sector/Block-Erase 2
N
times typical (21 x 24 = 32 ms)
26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.1 396
1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016
TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080
Address Data Data
27H 14H Device size = 2
N
Bytes (14H = 20; 220 = 1 MBytes)
28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface
29H 00H
2AH 00H Maximum number of byte in multi-byte write = 2
N
(00H = not supported)
2BH 00H
2CH 02H Number of Erase Sector/Block sizes supported by device
2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 00H y = 255 + 1 = 256 sectors (00FFH = 255)
2FH 10H
30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 0FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 00H y = 15 + 1 = 16 blocks (000FH = 15)
33H 00H
34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T7.0 396
Page 9
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
9
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
TABLE 8: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF016
Address Data Data
27H 15H Device size = 2
N
Bytes (15H = 21; 221 = 2 MBytes)
28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface
29H 00H
2AH 00H Maximum number of byte in multi-byte write = 2
N
(00H = not supported)
2BH 00H
2CH 02H Number of Erase Sector/Block sizes supported by device
2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 01H y = 511 + 1 = 512 sectors (01FFH = 511)
2FH 10H
30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 1FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 00H y = 31 + 1 = 32 blocks (001FH = 31)
33H 00H
34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T8.2 396
Page 10
10
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V
DD
+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V
DD
+ 1.0V
Voltage on A
9
Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circ uit Curr ent
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST39L F080/016
Range Ambient Temp V
DD
Commercial 0°C to +70°C 3.0-3.6V
OPERATING RANGE FOR SST39V F080/016
Range Ambient Temp V
DD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . C
L
= 30 pF for SST39LF080/016
Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080/016
See Figures 14 and 15
Page 11
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
11
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
TABLE 9: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39L F080/016 AND 2.7- 3.6V FOR SST39VF 080/016
Symbol Parameter
Limits
Test ConditionsMin Max Units
I
DD
Power Supply Current Address input=VIL/VIH, at f=1/TRC Min
V
DD=VDD
Max
Read 15 mA CE#=OE#=V
IL
, WE#=VIH, all I/Os open
Program and Erase 20 mA CE#=WE#=V
IL
, OE#=V
IH
I
SB
Standby VDD Current 20 µA CE#=V
IHC
, VDD=VDD Max
I
ALP
Auto Low Power 20 µA CE#=V
ILC
, VDD=VDD Max
All inputs=V
IHC
or V
ILC
WE#=V
IHC
I
LI
Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
I
LO
Output Leakage Current 10 µA V
OUT
=GND to VDD, VDD=VDD Max
V
IL
Input Low Voltage 0.8 V VDD=VDD Min
V
ILC
Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
V
IH
Input High Voltage 0.7V
DD
VVDD=VDD Max
V
IHC
Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
V
OL
Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
V
OH
Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T9.2 396
TABLE 10: RECOMMENDED SYSTE M POWER-UP TIMINGS
Symbol Parameter Minimum Units
T
PU-READ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
T
PU-WRITE
1
Power-up to Program/Erase Operation 100 µs
T10.1 396
TABLE 11: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
C
I/O
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance V
I/O
= 0V 12 pF
C
IN
1
Input Capacitance VIN = 0V 6 pF
T11.0 396
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
N
END
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 10,000 Cycles JEDEC Standard A117
T
DR
1
Data Retention 100 Years JEDEC Standard A103
I
LTH
1
Latch Up 100 + I
DD
mA JEDEC Standard 78
T12.1 396
Page 12
12
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
AC CHARACTERISTICS
TABLE 13: READ CYCLE TIMING PARAMETERS
VDD = 3.0-3.6V FOR SST39L F080/016 AND 2.7- 3.6V FOR SST39VF 080/016
Symbol Parameter
SST39LF080/016-55 SST39VF080/016-70 SST39VF080/016-90
UnitsMin Max Min Max Min Max
T
RC
Read Cycle Time 55 70 90 ns
T
CE
Chip Enable Access Time 55 70 90 ns
T
AA
Address Access Time 55 70 90 ns
T
OE
Output En able Access Time 30 35 45 ns
T
CLZ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 0 ns
T
OLZ
1
OE# Low to Active Output 0 0 0 ns
T
CHZ
1
CE# High to High-Z Output 15 20 30 ns
T
OHZ
1
OE# High to High-Z Output 15 20 30 ns
T
OH
1
Output Hold from Address Change 0 0 0 ns
T13.3 396
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
T
BP
Byte-Program Time 20 µs
T
AS
Address Setup Time 0 ns
T
AH
Address Hold Time 30 ns
T
CS
WE# and CE# Setup Time 0 ns
T
CH
WE# and CE# Hold Time 0 ns
T
OES
OE# High Setup Time 0 ns
T
OEH
OE# High Hold Time 10 ns
T
CP
CE# Pulse Width 40 ns
T
WP
WE# Pulse Width 40 ns
T
WPH
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
T
CPH
1
CE# Pulse Width High 30 ns
T
DS
Data Setup Time 30 ns
T
DH
1
Data Hold Time 0 ns
T
IDA
1
Software ID Access and Exit Time 150 ns
T
SE
Sector-Erase 25 ms
T
BE
Block-Erase 25 ms
T
SCE
Chip-Erase 100 ms
T14.0 396
Page 13
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
13
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 3: READ CYCLE TIMING DIAGRAM
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
396 ILL F02.1
ADDRESS A
MS-0
DQ
7-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZV
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
396 ILL F03.1
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
ADDRESS A
MS-0
DQ
7-0
T
DH
T
WPH
T
DS
T
WP
T
AH
T
AS
T
CH
T
CS
CE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
WE#
T
BP
Page 14
14
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
FIGURE 6: DATA# POLLING TIMING DIAGRAM
396 ILL F04.1
ADDRESS A
MS-0
DQ
7-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
T
BP
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
396 ILL F05.1
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
ADDRESS A
MS-0
DQ
7
DATA DATA# DATA# DATA
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Page 15
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
15
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
396 ILL F06.1
ADDRESS A
MS-0
DQ
6
WE#
OE#
CE#
T
OET
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
396 ILL F08.2
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
T
SCE
T
WP
Page 16
16
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
396 ILL F09.2
Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 5055AA 80 AA
BA
X
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
T
BE
T
WP
396 ILL F10.2
ADDRESS A
MS-0
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 3055AA 80 AA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Page 17
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
17
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 11: SOFTWARE ID ENTRY AND READ
FIGURE 12: CFI Q UER Y ENTRY AND READ
396 ILL F11.3
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0
SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
T
WP
T
WPH
T
AA
BF
Device ID
55AA 90
Note: Device ID = D9H for SST39LF/VF016
D8H for SST39LF/VF080
396 ILL F12.0
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0
SW1 SW2
5555 2AAA 5555
OE#
CE#
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
T
WP
T
WPH
T
AA
55AA 98
Page 18
18
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
396 ILL F13.0
ADDRESS A
14-0
DQ
7-0
T
IDA
T
WP
T
WHP
WE#
SW0 SW1 SW2
5555 2AAA 5555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
AA 55 F0
Page 19
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
19
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 15: A TEST LOAD EXAMPLE
396 ILL F14.1
REFERENCE POINTS OUTPUTINPUT
V
IT
V
IHT
V
ILT
V
OT
AC test inputs are driven at V
IHT
(0.9 VDD) for a logic “1” and V
IL T
(0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are V
IT
(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: V
IT
- V
INPUT
Test
V
OT
- V
OUTPUT
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
396 ILL F15.1
TO TESTER
TO DUT
C
L
Page 20
20
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 16: BYTE-PROGRAM ALGORITHM
396 ILL F16.1
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
Page 21
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
21
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 17: WAIT OPTIONS
396 ILL F17.0
Wait TBP,
T
SCE, TSE
or T
BE
Program/Erase
Initiated
Internal Timer
Toggle Bit
Yes
Yes
No
No
Program/Erase
Completed
Does DQ
6
match?
Read same
byte
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read byte
Is DQ7 =
true data?
Read DQ
7
Program/Erase
Initiated
Program/Erase
Initiated
Page 22
22
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS
396 ILL F18.1
Load data: AAH
Address: 5555H
Software Product ID Entry
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 90H
Address: 5555H
Wait T
IDA
Read Software ID
Load data: AAH
Address: 5555H
CFI Query Entry
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 98H
Address: 5555H
Wait T
IDA
Read CFI data
Load data: AAH
Address: 5555H
Software ID Exit/CFI Exit
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: F0H
Address: 5555H
Load data: F0H
Address: XXH
Return to normal
operation
Wait T
IDA
Wait T
IDA
Return to normal
operation
Page 23
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
23
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
FIGURE 19: ERASE COMMAND SEQUENCE
396 ILL F19.1
Load data: AAH
Address: 5555H
Chip-Erase
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: AAH
Address: 5555H
Wait T
SCE
Chip erased
to FFH
Load data: AAH
Address: 5555H
Sector-Erase
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 30H
Address: SA
X
Load data: AAH
Address: 5555H
Wait T
SE
Sector erased
to FFH
Load data: AAH
Address: 5555H
Block-Erase
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 50H
Address: BA
X
Load data: AAH
Address: 5555H
Wait T
BE
Block erased
to FFH
Page 24
24
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
PRODUCT ORDERING INFORMATION
Valid combinations for SST39LF080
SST39LF080-55-4C-EI SST39LF080-55-4C-B3K
Valid combinations for SST39VF080
SST39VF080-70-4C-EI SST39VF080-70-4C-B3K
SST39VF080-90-4C-EI SST39VF080-90-4C-B3K
SST39VF080-70-4I-EI SST39VF080-70-4I-B3K
SST39VF080-90-4I-EI SST39VF080-90-4I-B3K
Valid combinations for SST39LF016
SST39LF016-55-4C-EI SST39LF016-55-4C-B3K
Valid combinations for SST39VF016
SST39VF016-70-4C-EI SST39VF016-70-4C-B3K
SST39VF016-90-4C-EI SST39VF016-90-4C-B3K
SST39VF016-70-4I-EI SST39VF016-70-4I-B3K
SST39VF016-90-4I-EI SST39VF016-90-4I-B3K
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Device Speed Suffix1 Suffix2
SST39V
Fxxx -XX -XX -XX
Package Modifie r
I = 40 leads
K = 48 balls
Package Type
E = TSOP (10mm x 20mm)
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
080 = 8 Megabit
016 = 16 Megabit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Page 25
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
25
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
PACKAGING DIAGRAMS
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM
SST PACKAGE CODE: EI
40.TSOP-EI-ILL.4
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
10.10
9.90
.270
.170
1.05
0.95
.50
BSC
0.15
0.05
18.50
18.30
20.20
19.80
0.70
0.50
Pin # 1 Identifier
Page 26
26
Data Sheet
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
A1 CORNER
H G F E D C B A
A B C D E F G H
BOTTOM VIEW
TOP VIEW
SIDE VIEW
6
5
4
3
2
1
6
5
4
3
2
1
SEATING PLANE
0.35 ± 0.05
1.10 ± 0.10
0.15
6.00 ± 0.20
0.45 ± 0.05
(48X)
A1 CORNER
8.00 ± 0.20
0.80
4.00
0.80
5.60
48ba-TFBGA-B3K-6x8-450mic-ILL.0
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
1mm
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735 -90 36
www.SuperFlash.com or www.ssti.com
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