Datasheet SST39LF080, SST39LF016, SST39VF080, SST39VF016 Datasheet (Silicon Storage Technology)

查询SST39LF016供应商

8 Mbit / 16 Mbit (x8) Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF 016

SST39LF/VF080 / 0163.0 & 2.7V 8Mb / 16Mb (x8) MPF memories

FEATURES:

Data Sheet

• Organized as 1M x8 / 2M x8

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF080/016
– 2.7-3.6V for SST39VF080/016

• Superior Reliability

– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 15 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Fast Read Access Time:

– 55 ns for SST39LF080/0 16
– 70 and 90 ns for SST39VF080/ 016

• Latched Address and Data

PRODUCT DESCRIPTION

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:

15 seconds (typical) for SST39LF/VF 080
30 seconds (typical) for SST39LF/VF 016

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 40-lead TSOP (10mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)

The SST39LF/VF080 and SST39LF/VF016 devices are
1M x8 / 2M x8 CMO S Multi-Pur pose Fl ash (MPF) m anu­factured with SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick
oxide tunneling injector attain better reliability and manufac­turability compared with alternate approaches. The
SST39LF080/016 write (Program or Erase) with a 3.0-3.6V
power supply. The SST39VF080/016 write (Program or
Erase) with a 2.7-3.6V power supply. They conform to
JEDEC standar d pino uts f or x8 me mories .

Featuring high p erformance Byte-Program, the SST 39LF/
VF080 and SST39LF/VF016 devices provide a typical
Byte-Program time of 14 µsec. The devices use Toggle Bit
or Data# Polling to indicate the completion of Program
operation. To protect against inad vertent write, they have
on-chip hardware and So ftware Data Prot ecti on schem es.
Designed, manufactured, and tested for a wide spectrum of
applications, these d evices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater th an 100 y ear s.

The SST39LF/VF080 and SST39LF/VF016 devices are
suited for applications that require convenient and econom­ical updating of program, configuration, or data memory.
For all system applicati ons, they significant ly improve per­formance and reliability , while lowering power consumption.

They inherently use less energy during Erase and Program
than alternati ve flash technologies. The total energy con­sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash techn ology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technolog ies . The y also improv e f le xibilit y while l ow er­ing the cost for program, data, and conf iguration storage
applications.

The SuperFlash te ch nology provides fixed Erase and P r o­gram times, independent o f th e numbe r of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times i ncrease with accumul ated Erase/P ro­gram cycles .

To meet high density, surface mount requirements, the
SST39LF/VF080 a nd SST39LF/VF016 are offered in 40­lead TSOP and 48-ba ll TFBGA packaging. Se e Figures 1
and 2 for pinouts.

©2001 Silicon Storage Technology, Inc.
S71146-03-000 6/01 396

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Device Operation

Commands are used to initiate the memory operation func­tions of the device. Commands are written to the device
using standard microprocess or write sequences. A com­mand is written by asse r ting WE# low whil e keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latc hed o n
the rising edge of WE# or CE#, whichever occurs first.

The SST39LF/VF080 and SST39LF/VF016 also have the
Auto Low Power mode which puts the device in a ne ar
standby mode after da ta has been accessed with a valid
Read operation. This reduces the I
from typically 15 mA to typically 4 µA. The Auto Low P ower
mode reduces the typical I
range of 1 mA/MHz of read cycle time. The device exits the
Auto Low Power mode with any addre ss transi tion o r con­trol signal transition used to initiate another Read cycle,
with no access time penalty. Note that the device does not
enter Auto Low Power mode after power-up with CE# held
steadily low until the first address transition or CE# is driven
high.

active read current to the

DD

active read current

DD

Read

The Read operation of the SST39LF/VF080 and
SST39LF/VF016 is controlled by CE# and OE#, both have
to be low for the system to obtain dat a from the outputs.
CE# is used for device selection. When CE# is high, the
chip is des elected and onl y standby power is cons umed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Rea d cycle t iming
diagram for further details (Figure 3).

Byte-Program Operation

The SST39LF/VF080 and SST39LF/VF016 are pro­grammed on a byte-by-byte basis. Before programming,
one must ensure that the sector, in which the byte which is
being programmed exists, is fully erased. The Program
operation consists of three steps. The first step is the three­byte load sequence for Software Data Protection. The sec­ond step is to load byte address and byte data. Dur i ng th e
Byte-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, w hichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the inter nal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro­gram operation, once initiated, will be completed within 20
µs. See Figures 4 and 5 for WE# and CE# controlled Pro­gram operation timing diagrams and Figure 16 for flow­chart s. Durin g the P rogram operat ion, th e only valid reads

are Data# Polling and Toggle Bit. During the inte rnal Pr o­gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera­tion are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by­block) basis. The SST39LF /VF080 and SST39LF/VF016
offer both Sect or- Era se an d Blo c k-Er as e mode . The s ec tor
architecture is based on uniform sector size of 4 KByte.
The Block-Erase mode is based on uniform block size of
64 KByte. The Secto r-Erase operation is ini tiated by exe­cuting a six-byte-command sequence with Sector-Erase
command (30H) and sector address (SA) in the last bus
cycle. The Block-Erase operation is initiated by executing a
six-byte-command seq uence with Block-Erase command
(50H) and block address ( BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the
sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Era se operati on begin s after t he sixth W E# puls e.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. Se e Figure s 9
and 10 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF/VF080 and SST39LF/VF016 provide a
Chip-Erase operation, wh ich allows the user to era se the
entire memory array to the “1” state. This is useful when the
entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Eras e
operation begins with the rising edge of the sixt h WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is T oggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur­ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF/VF080 and SST39LF/VF016 provide two
software means to detect the completion of a write (Pro­gram or Erase) cycle, in order to optimize the system Write
cycle time. The software detection includes two status bits:
Data# Polling (DQ
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.

) and Toggle Bit (DQ6). The End-of-Write

7

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

2

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet
The actual completion of the nonvolatile write is asynchro-

nous with the sys tem; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the c ompletion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con­flict with either DQ

or DQ6. In order to prevent spurious

7

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec­tion is valid.

Data# Polling (DQ7)

When the SST39LF/VF080 and SST39LF/VF016 are in
the internal Pr ogram operation, any attempt to read DQ
will produce the co mplement of the true data. Once th e
Program operation is completed, DQ
data. The device is then ready for the next operation. Dur­ing intern al Erase ope ration, any atte mpt to re ad DQ
produce a ‘0’. Once the inter nal Erase operation is com-
pleted, DQ

will produce a ‘1’. The Data# Polling is valid

7

after the risin g e dge of four th WE# (or CE#) pul se for Pro­gram operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edg e of six th WE # ( or
CE#) pulse. See Figure 6 for Data# Polling timing dia gram
and Figure 17 for a flowchart.

will produce true

7

will

7

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V
Write Inhibit Mode:

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE#
high will inhibit the W r ite operation. This prevents inadvert­ent writes durin g pow er-u p or po wer- dow n.

Software Data Protection (SDP)

The SST39LF/VF080 and SST39LF/VF016 provide the
JEDEC approved Software Data Protecti on schem e for all
data alteration operations, i.e., Program and Erase. Any

7

Program operation req uires t he inc lusion of the thr ee-byte
sequence. The three-byte load sequence is used to initiate
the Program operation, p roviding optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of si x-byte sequence. The SS T39LF/VF080 an d
SST39LF/VF016 devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid comma nds will abo r t the device to read
mode within T

RC

.

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any con­secutive attempts to read DQ

will produce alter nating 1s

6

and 0s, i.e., toggling between 1 and 0. W hen the internal
Program or Erase operat ion is complete d, the DQ

bit will

6

stop toggling. The device is the n re ady for the next ope ra­tion. The Toggle Bit is valid af ter the rising edge of fourth
WE# (or CE#) pulse for Program operat ion. For Sector-,
Block-, or Chip-Erase, the T oggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diag ram and Fi gure 17 f or a fl owc hart.

Data Protection

The SST39LF/VF080 and SST39LF/VF016 provide both
hardware and software features to protec t nonvolatile data
from inadvertent writes.

Common Flash Memory Interface (CFI)

The SST39LF/VF080 and SST39LF/VF016 also contain
the CFI informatio n to describe the characteri stics of the
device. In order to enter the CFI Quer y mode, the system
must write three-byte sequence, same as product ID entry
command with 98H (CFI Query command) to address
5555H in the la st byte sequenc e. Once the device en ters
the CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 8. The system must
write the CFI Exit co mmand t o retur n to Read mo de from
the CFI Query mode.

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

3

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Product Identification

The Product Identification mode identifies the device as the
SST39LF080, SST39VF080, SST39LF016, and
SST39VF016 and manufacturer as SST. This mode may
be accessed by software o perations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when usi ng multipl e manufactur­ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry a nd Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flo wchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH
Device ID

SST39LF/VF080 0001H D8H
SST39LF/VF016 0001H D9H

FUNCTIONAL BLOCK DIAGRAM

RODUCT IDENTIFICATION

Address Data

T1.2 396

Product Identification Mode Exit/
CFI Mode Exit

In order to return to the standard Read mode, the Software
Product Identific ation mode must be exited. Exit is acco m­plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently caus es the device to behave abnor mally, e.g.,
not read correct ly. Please no te that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform and Figure 18 for a
flowchart.

Memory
Address

WE#

Address Buffer & Latches

CE#
OE#

X-Decoder

Control Logic

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

0

396 ILL B1.2

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

4

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

SST39LF/VF160 SST39LF/VF080

A16
A15
A14
A13
A12
A11

A9
A8

WE#

NC
NC
NC

A18

A7
A6
A5
A4
A3
A2
A1

A16
A15
A14
A13
A12
A11

WE#

NC
NC
NC

A18

1
2
3
4
5

A9
A8

A7
A6
A5
A4
A3
A2
A1

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Standard Pinout

FIGURE 1: PIN ASSIGNMENTS FOR 40-LEA D TSOP

TOP VIEW (balls facing down)

SST39LF/VF080

6

A14

A13

A15

A16

A17

NC

NC

V

5
4
3
2
1

A9

WE#

NC
A7
A3

A8
NC
NC

A18

A4

A11

NC
NC
A6
A2

A12

NC
NC
A5
A1

A19
DQ5
DQ2
DQ0

A0

A10

NC

DQ3

NC

CE#

A B C D E F G H

DQ6
V

DD

V

DD

NC

OE#

SS

DQ7
DQ4

NC
DQ1
V

SS

396 ILL F20.1

T op Vie w

Die Up

SST39LF/VF080 SST39LF/VF016

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A17
V
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
V
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
CE#
A0

396 ILL F01.2

SS

DD
DD

SS

A17
V

SS

A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V

DD

V

DD

NC
DQ3
DQ2
DQ1
DQ0
OE#
V

SS

CE#
A0

TOP VIEW (balls facing down)

SST39LF/VF016

6

A14

A13

A15

A16

A17

NC

A20

V

5
4
3
2
1

A9

WE#

NC
A7
A3

A8
NC
NC

A18

A4

A11

NC
NC
A6
A2

A12

NC
NC
A5
A1

A19
DQ5
DQ2
DQ0

A0

A10

NC

DQ3

NC

CE#

DQ6
V

DD

V

DD

NC

OE#

SS

DQ7
DQ4

NC
DQ1
V

SS

396 ILL F21.1

A B C D E F G H

FIGURE 2: P

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

IN ASSIGNMENTS FOR 48-BALL TFBGA

5

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address
A

MS

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V
Program V
Erase V

Standby V
Write Inhibit X V

Product Identification
Software Mode V

1. X can be VIL or VIH, but no other value.

Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will s ele ct the

0

sector. During Block-Erase A

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

address lines will select the block.

MS-A16

Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF080/016

2.7-3.6V for SST39VF080/016

Ground

= A19 for SST39LF/VF080 and A20 for SST39LF/VF016

IL
IL
IL

V

IL

V

IH

V

IH

V
V
V

D

IH
IL
IL

D
X

OUT
IN

1

A

IN

A

IN

Sector or B lock address,
XXH for Chip-Erase

IH

XXV

IL

XXHigh Z X

IL

V

IL

XHigh Z/ D

High Z/ D

IH

V

IH

OUT
OUT

X
X

See Table 4

Data Sheet

T2.3 396

T3.4 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

6

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command
Sequence

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry
CFI Query Entry
Software ID Exit

4,5

4

6

/

CFI Exit
Software ID Exit

6

/

CFI Exit

1. Address format A14-A0 (Hex),
Addresses A
Addresses A

2. WA = Program Byte address

3. SA

for Sector-Erase; uses AMS-A12 address lines

X

, for Block-Erase; uses AMS-A16 address lines

BA

X

= Most significant address

A

MS

= A19 for SST39LF/VF080 and A20 for SST39LF/VF016

A

MS

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

6. Both Software ID Exit operations are equivalent

- A19 can be VIL or VIH, but no other value, for the Com mand sequence for SST39LF/VF080.

15

- A20 can be VIL or VIH, but no other value, for the Com mand sequence for SST39LF/VF016.

15

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2

Data

3

X

3

X

5555H AAH 2AAAH 55H 5555H 90H
5555H AAH 2AAAH 55H 5555H 98H

XXH F0H

5555H AAH 2AAAH 55H 5555H F0H

SST39LF/VF080 Device ID = D8H, is read with A
SST39LF/VF016 Device ID = D9H, is read with A

0
0

= 1
= 1

30H
50H

T4.3 396

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF /VF080 AND SS T39LF/VF016

Address Data Data

10H 5 1H Query Unique ASCII string “QRY”
11H 52H
12H 59H
13H 01H Primary OEM command set
14H 07H
15H 00H Address for Primary Extended Table
16H 00H
17H 00H Alternate OEM command set (00H = none exists)
18H 00H
19H 00H Address for Alternate OEM extended Table (00H = none exits)

1AH 00H

1. Refer to CFI publication 100 for more details.

T5.3 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

7

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39VF 320/64 0

Address Data Data

1

1BH 27H

30H

1CH 36H V

1DH 00H V
1EH 00H V
1FH 04H Typical time out for Byte-Program 2
20H 00H Typical time out for min. size buffer program 2
21H 04H Typical time out for individual Sector/Block-Er ase 2
22H 06H Typical time out for Chip-Erase 2
23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)
24H 00H Maximum time out for buffer program 2N times typical
25H 01H Maximum time out for individual Sector/Block-Erase 2
26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016

VDD Min (Program/Erase)

1

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

Max (Program/Erase)

DD

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

min. (00H = no VPP pin)

PP

max. (00H = no VPP pin)

PP

N

µs (24 = 16 µs)

N

N

ms (26 = 64 ms)

µs (00H = not supported)

N

ms (24 = 16 ms)

N

times typica l (21 x 24 = 32 ms)

Data Sheet

T6.1 396

TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080

Address Data Data

27H 14H Device size = 2
28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface
29H 00H
2AH 00H Maximum number of byte in multi-byte write = 2
2BH 00H
2CH 02H Number of Erase Sector/Block sizes supported by device
2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 00H y = 255 + 1 = 256 sectors (00FFH = 255)
2FH 10H
30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 0FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 00H y = 15 + 1 = 16 blocks (000FH = 15)
33H 00H
34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

N

Bytes (14H = 20; 220 = 1 MBytes)

N

(00H = not supported)

T7.0 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

8

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

TABLE 8: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF016

Address Data Data

27H 15H Device size = 2
28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface
29H 00H
2AH 00H Maximum number of byte in multi-byte write = 2
2BH 00H
2CH 02H Number of Erase Sector/Block sizes supported by device
2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 01H y = 511 + 1 = 512 sectors (01FFH = 511)
2FH 10H
30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 1FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 00H y = 31 + 1 = 32 blocks (001FH = 31)
33H 00H
34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

N

Bytes (15H = 21; 221 = 2 MBytes)

N

(00H = not supported)

T8.2 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

9

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

OPERATING RANGE FOR SST39L F080/016

Range Ambient Temp V

Commercial 0°C to +70°C 3.0-3.6V

DD

+ 0.5V

DD

+ 1.0V

DD

OPERATING RANGE FOR SST39V F08 0/016

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080/016

See Figures 14 and 15

= 30 pF for SST39LF080/016

L

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

10

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

TABLE 9: DC OPERATING CHARACTERISTICS

VDD = 3.0-3.6V FOR SST39L F080/016 AND 2.7- 3.6V FOR SS T39VF 080/016

Limits

Symbol Parameter

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

Read 15 mA CE#=OE#=V

Program and Erase 20 mA CE#=WE#=V
I
I

I
I
V
V
V
V
V
V

SB
ALP

LI
LO

IL
ILC
IH

IHC
OL
OH

Standby VDD Current 20 µA CE#=V
Auto Low Power 20 µA CE#=V

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
Output Leakage Current 10 µA V
Input Low Voltage 0.8 V VDD=VDD Min
Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
Input High Voltage 0.7V
Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
Output Hi gh Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

DD

Test ConditionsMin Max Units

V

DD=VDD

IHC
ILC

All inputs=V

=GND to VDD, VDD=VDD Max

OUT

VVDD=VDD Max

Max

, WE#=VIH, all I/Os open

IL

, OE#=V

IL

IH

, VDD=VDD Max

, VDD=VDD Max

IHC

or V

WE#=V

ILC

IHC

T9.2 396

TABLE 10: RECOMMENDED SYSTE M POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

1

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs
Power-up to Program/Erase Operation 100 µs

TABLE 11: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 12: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117
Data Retention 100 Years JEDEC Standard A103
Latch Up 100 + I

DD

mA JEDEC Standard 78

T10.1 396

T11.0 396

T12.1 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

11

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

AC CHARACTERISTICS

TABLE 13: READ CYCLE TIMING PARAMETERS

VDD = 3.0-3.6V FOR SST39L F080/016 AND 2.7- 3.6V FOR SS T39VF 080/016

SST39LF080/016-55 SST39VF080/016-70 SST39VF080/016-90

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

T

CLZ

T

OLZ

T

CHZ

T

OHZ

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 55 70 90 ns
Chip Enable Access Time 55 70 90 ns
Address Access Time 55 70 90 ns
Output Enable Access Ti me 30 35 45 ns

1

CE# Low to Active Output 0 0 0 ns

1

OE# Low to Active Output 0 0 0 ns

1

CE# High to High-Z Output 15 20 30 ns

1

OE# High to High-Z Output 15 20 30 ns

1

Output Hold from Addr ess Change 0 0 0 ns

Data Sheet

UnitsMin Max Min Max Min Max

T13.3 396

TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

BE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Byte-Program Time 20 µs
Address Setup Time 0 ns
Address Hold Time 30 ns
WE# and CE# Setup Time 0 ns
WE# and CE# Hold Time 0 ns
OE# High Setup Time 0 ns
OE# High Hold Time 10 ns
CE# Pulse Width 40 ns
WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns
Data Setup Time 30 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns
Sector-Erase 25 ms
Block-Erase 25 ms
Chip-Erase 100 ms

T14.0 396

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

12

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

IH

HIGH-Z

Note: AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 3: READ CYCLE TIMIN G DIAGRAM

T

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

T

OH

DATA VALIDDATA VALID

CHZ

HIGH-Z

396 ILL F02.1

ADDRESS A

MS-0

DQ

WE#

OE#

CE#

7-0

T

AS

Note: AMS = Most significant address

5555 2AAA 5555 ADDR

T

AH

T

WP

T

T

WPH

T

CH

T

CS

AA 55 A0 DATA

SW0 SW1 SW2

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

DS

BYTE

(ADDR/DATA)

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

396 ILL F03.1

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

13

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555 2AAA 5555 ADDR

T

AH

T

CP

T

AS

T

CPH

T

CH

T

CS

T

DS

AA 55 A0 DATA

T

DH

SW0 SW1 SW2

BYTE

(ADDR/DATA)

Note: AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

DQ

T

CE

T

OEH

T

OE

7

DATA DATA# DATA# DATA

396 ILL F04.1

T

OES

Note: AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

396 ILL F05.1

FIGURE 6: DATA# POLLING TIMING DIAGRAM

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

14

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

ADDRESS A

MS-0

CE#

OEH

OE#

WE#

DQ

6

Note: AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 7: TOGGLE BIT TIMING DIAGRAM

T

CE

T

OET

SIX-BYTE CODE FOR CHIP-ERASE

TWO READ CYCLES

WITH SAME OUTPUTS

T

SCE

T

OES

396 ILL F06.1

ADDRESS A

MS-0

CE#

OE#

WE#

DQ

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

5555

55 1055AA 80 AA

396 ILL F08.2

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

15

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

T

SIX-BYTE CODE FOR BLOCK-ERASE

BE

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

BA

X

55 5055AA 80 AA

396 ILL F09.2

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 14)
AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

T

SE

SA

X

55 3055AA 80 AA

396 ILL F10.2

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

16

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

ADDRESS A

DQ

14-0

CE#

OE#

WE#

7-0

5555 2AAA 5555 0000 0001

T

WP

T

WPH

55AA 90

SW0

Note: Device ID = D9H for SST39LF/VF016

SW1 SW2

D8H for SST39LF/VF080

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

BF

AA

Device ID

396 ILL F11.3

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A

DQ

14-0

CE#

OE#

WE#

7-0

5555 2AAA 5555

T

WP

T

WPH

55AA 98

SW0

SW1 SW2

FIGURE 12: CFI Q UER Y ENTRY AND READ

T

IDA

T

AA

396 ILL F12.0

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

17

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

8 Mbit / 16 Mbit Multi-Purpose Flash

Data Sheet

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

5555 2AAA 5555

AA 55 F0

T

WP

T

SW0 SW1 SW2

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

WHP

T

IDA

396 ILL F13.0

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

18

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

V

IHT

V

ILT

AC test inputs are driven at V
for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

396 ILL F14.1

(0.1 VDD) for a logic “0”. Measurement reference points

IL T

Note: V

- V

- V

- V

- V

INPUT

OUTPUT

INPUT

INPUT

Test

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

396 ILL F15.1

FIGURE 15: A TEST LOAD EXAMPLE

C

L

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

19

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

FIGURE 16: BYTE-PROGRAM ALGORITHM

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

396 ILL F16.1

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

20

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE, TSE

or T

BE

Program/Erase

Completed

Program/Erase

No

Toggle Bit

Initiated

Read byte

Read same

byte

Does DQ

match?

Yes

Data# Polling

Program/Erase

Initiated

No

Read DQ

Is DQ7 =

7

true data?

Yes

6

Program/Erase

Completed

Program/Erase

Completed

396 ILL F17.0

FIGURE 17: WAIT OPTIONS

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

21

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

CFI Query Entry

Command Sequence

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 98H

Address: 5555H

Wait T

IDA

Read CFI data

Software Product ID Entry

Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait T

IDA

Read Software ID

Software ID Exit/CFI Exit

Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Load data: F0H

Address: XXH

Wait T

IDA

Return to normal

operation

396 ILL F18.1

FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

22

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Chip-Erase

Command Sequence

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Block-Erase

Command Sequence

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Wait T

SCE

Chip erased

to FFH

Load data: 30H

Address: SA

Wait T

X

SE

Sector erased

to FFH

Load data: 50H

Address: BA

Wait T

X

BE

Block erased

to FFH

396 ILL F19.1

FIGURE 19: ERASE COMMAND SEQUENCE

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

23

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

8 Mbit / 16 Mbit Multi-Purpose Flash

Data Sheet

SST39V

Fxxx -XX -XX -XX

Package Modifi e r

I = 40 leads
K = 48 balls

Package Type

E = TSOP (10mm x 20mm)
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

Temperature Range

C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns
70 = 70 ns
90 = 90 ns

Device Density

080 = 8 Megabit
016 = 16 Megabit

Voltage

L = 3.0-3.6V
V = 2.7-3.6V

Valid combinations for SST39LF080

SST39LF080-55-4C-EI SST39LF080-55-4C-B3K

Valid combinations for SST39VF080

SST39VF080-70-4C-EI SST39VF080-70-4C-B3K
SST39VF080-90-4C-EI SST39VF080-90-4C-B3K

SST39VF080-70-4I-EI SST39VF080-70-4I-B3K
SST39VF080-90-4I-EI SST39VF080-90-4I-B3K

Valid combinations for SST39LF016

SST39LF016-55-4C-EI SST39LF016-55-4C-B3K

Valid combinations for SST39VF016

SST39VF016-70-4C-EI SST39VF016-70-4C-B3K
SST39VF016-90-4C-EI SST39VF016-90-4C-B3K

SST39VF016-70-4I-EI SST39VF016-70-4I-B3K
SST39VF016-90-4I-EI SST39VF016-90-4I-B3K

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

24

8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

PACKAGING DIAGRAMS

Pin # 1 Identifier

1.05

0.95

.50

BSC

.270
.170

10.10

9.90

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

20.20

19.80

40.TSOP-EI-ILL.4

40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM

SST PACKAGE CODE: EI

0.15

0.05

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

25

TOP VIEW

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

BOTTOM VIEW

8.00 ± 0.20

5.60

0.80

6
5
4
3
2
1

A1 CORNER

A B C D E F G H

SIDE VIEW

SEATING PLANE

6.00 ± 0.20

1.10 ± 0.10

0.15

0.35 ± 0.05

4.00

0.80
H G F E D C B A

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K

6
5
4
3
2
1

0.45 ± 0.05
(48X)

A1 CORNER

48ba-TFBGA-B3K-6x8-450mic-ILL.0

1mm

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone [phone] • Fax [phone]

www.SuperFlash.com or www.ssti.com

©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396

26