Datasheet SST39LF512, SST39LF010, SST39LF020, SST39LF040, SST39VF512 Datasheet (Silicon Storage Technology)

查询39LF020供应商

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single V oltage Read and Write Operations

– 3.0-3.6V for SST39LF512/010/020/040
– 2.7-3.6V for SST39VF512/010/020/040

• Superior Reliability

– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical)
– Standby Current: 1 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 45 ns for SST39LF512/010/020/040
– 55 ns for SST39LF020/0 40
– 70 and 90 ns for SST39VF512/ 010/ 020 /040

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:

1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC
– 32- l ead TSOP (8mm x 14mm)
– 48-ball TFBGA (6mm x 8mm) for 1 Mbit

Data Sheet

PRODUCT DESCRIPTION

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick oxide tun­neling injector atta in better reliability and manufacturability
compared with alternate approaches. The SST39LF512 /
010/020/040 devices wr ite (Program or Erase) with a 3.0-

3.6V power supply. The SST39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST39LF512/010/020/040 and SST39VF512/010/020/
040 devices provide a maxi mum Byte -Pr ogram time of 2 0
µsec. These devices use Toggle Bit or Data# Polling to indi­cate the completion of Program operation. To protect
against inadver ten t wri te, they have on-chip hardware an d
Software Data Protection schemes. Designed, manufac­tured, and tested for a wide spe ctr um of appl icatio ns, they
are offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, c onfigu­ration, or data memor y. For all system applica tions, they

significantly improves performance and reliability, while low­ering power consumption. They inherently use less energy
during Erase and P rogram tha n alte r nat ive flash techn olo­gies. The total energy consumed is a function of the
applied voltage, cu rrent, an d time of appli cation. Si nce for
any given voltage range, the Supe rFlash te chnology uses
less current to program and has a shor ter era se time, the
total energy consumed during any Erase or Program oper­ation is less than alternative flash technologies. These
devices also impr ove flexibility while lowering the c ost for
program, data, and configuration storage applications.

The SuperFlash te ch nology provides fixed Erase and P r o­gram times, independent o f th e numbe r of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times i ncrease with accumul ated Erase/P ro­gram cycles .

To meet surface mount requirements, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
39LF/VF010 is also offered in a 48-ball TFBGA package.
See Figures 1 and 2 for pinouts.

©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01 395

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Device Operation

Commands are used to initiate the memory operation func­tions of the device. Commands are written to the device
using standard microprocess or write sequences. A com­mand is written by asse r ting WE# low whil e keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latc hed o n
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation o f the S ST3 9LF 5 12/ 01 0/0 20/ 040 and
SST39VF512/010/020/040 device is controlled by CE#
and OE#, both have to be low for the system to obtain data
from the outputs. C E# is used for device selec tion. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the outp ut pins. The data bus is in hi gh imped­ance state when e ither CE# or OE# is high. Refer to the
Read cycle timing diagra m f or further details (Figur e 4).

Byte-Program Operation

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are programmed on a byte-by-byte basis. Before
programming, one must ens ure that the sector, in which
the byte which is being programmed exists, is fully erased.
The Program operati on consists of three steps. Th e first
step is the three-byte-load sequence for Software Data
Protection. The second step is to load byte ad dress and
byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of ei ther CE# or
WE#, whichever occurs last. The data is latched on the ris­ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operat ion which is initi­ated after the rising edge of the fourth WE# or CE#, which­ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. Se e Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 15 for flowchar ts. During the Program ope ra­tion, the only valid reads are Dat a# Polling and Toggle Bit.
During the inte rnal Program operat ion, the host is fre e to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on unifor m sector size of 4 KByte. The S ector­Erase operation is initiated by executing a six-byte-com­mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#

pulse, while the command (30H) is latched on the rising
edge of the sixth W E # pu ls e. The i nte rnal Erase op eratio n
begins after the sixth WE# pulse. The End-of-Erase can be
determined us ing either Data# Polling or Toggle Bit meth­ods. See Figure 9 for timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.

Chip-Erase Operation

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1s”
state. This is useful when the entire device must be quickly
erased.

The Chip-Erase operation is initiated by executing a six­byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The inter nal Erase operation beg ins with
the rising edge of the sixt h WE # o r CE# , which ever oc cu rs
first. During the internal Erase operation, the only valid read
is T oggle Bit or Data# Polling. See Table 4 f or the command
sequence, Figure 10 for timing diagram, an d Figu re 18 for
the flowchart. Any commands written during the Chip­Erase operation will be ignored.

Write Operation Status Detection

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide two software means to detect the
completion of a Write (Program or Erase) cycle, in order to
optimize the system write cycle time. The software detec­tion includes two s ta tus b it s: Dat a# Polling (DQ
gle Bit (DQ
after the rising edge of WE# which initiates the internal Pro­gram or E rase op erat ion.

The actual comple tion of the n onvolatile write is as ync hro­nous with the sys tem; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous wi th the complet ion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con­flict with either DQ
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec­tion is valid.

). The End-of-Write detection mode is enabled

6

or DQ6. In order to prevent spurious

7

) and Tog-

7

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Data# Polling (DQ7)

When the SST39LF512/010/020/040 and SST39VF512/
010/020/040 are in the internal Program operation, any
attempt to read DQ

will produce the complement of the

7

true data. Onc e the P rogram ope ration is c ompl eted, D Q
will produce true data. The device is then ready for the next
operation. Duri ng inter nal E rase operation, any attempt t o
read DQ
tion is completed, DQ

will produce a ‘0’. Once the internal Erase opera-

7

will produce a ‘1’. The Data# Polling

7

is valid after the r ising edg e of four th WE# (or CE#) p ulse
for Program operation. For Sector- or Chip-Erase, the
Data# Polling is valid after the rising edg e of six th WE # ( or
CE#) pulse. See Figure 7 for Data# Polling timing dia gram
and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any con­secutive attempts to read DQ

will produce alter nating 0s

6

and 1s, i.e., toggling between 0 and 1. W hen the internal
Program or Erase operation is com plete d, t he tog gling wi ll
stop. The device is then rea dy for the next operation. Th e
Toggle Bit is valid after the rising edge of fourth WE # (or
CE#) pulse for Program operation. For Sector- or Chip­Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for T oggle Bit timing dia­gram an d Figur e 16 f or a flo wcha rt.

Data Protection

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide both hardware and software features to
protect non v ol atile d ata fr om inad ve rtent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5
ns will not init iate a Writ e cycle .

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V
Write Inhibit Mode:

high will inhibit the W r ite operation. This prevents inadvert­ent writes during p ow er-up o r pow er- down.

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE#

Software Data Protection (SDP)

The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide the JEDEC approved Software Data Pro­tection scheme for all data alteration operation, i.e., Pro­gram and Erase. Any Program operation requires the

7

inclusion of a series of three byte sequence. The three
byte-load sequence i s used to in itiate the P rogram opera­tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power­down. Any Erase operation requires the inclusion of six
byte load sequence. These devices are shipped with th e
Software Data Protectio n pe rmanently ena bled. Se e Table
4 for the specific software co mmand codes. During SDP
command sequence, invalid commands will abort the
device to read mode, within T

RC

.

Product Identification

The Product Id entification mode ide ntifies the devices as
the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020
and SST39LF/VF040 and manufacturer as SST. This
mode may be accessed by software operations. Users
may use the Software Pro duct Identification operation t o
identify the part (i.e., using the device ID) when using multi­ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 11 for the Software
ID Entry and Read timing diagram, and F igure 17 for the
Software ID entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH
Device ID

SST39LF/VF512 0001H D4H
SST39LF/VF010 0001H D5H
SST39LF/VF020 0001H D6H
SST39LF/VF040 0001H D7H

RODUCT IDENTIFICATION

Address Data

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identific ation mode must be exited. Exit is acco m­plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the S oftware ID Exit command is ig nor e d
during an internal Program or Erase operation. See T able 4
for software command codes, Figure 12 for timing wave­form, and Figure 17 for a flowchart.

T1.1 395

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

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FUNCTIONAL BLOCK DIAGRAM

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Memory Address

Address Buffers & Latches

CE#
OE#

WE#

X-Decoder

Control Logic

A12

A12

A12

A15

A16

A18

A15

A16NCVDDWE#

A15

A16NCVDDWE#

VDDWE#

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

A17

A17

NC

0

395 ILL B1.1

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A12

A15NCNC

SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

4 3 2 1 32 31 30

5
6
7
8

32-lead PLCC

9
10
11
12
13

SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512

T op Vie w

14 15 16 17 18 19 20

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

VDDWE#

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

SS

V

DQ3

DQ4

DQ5

DQ6

SS

V

DQ3

DQ4

DQ5

DQ6

SS

V

DQ3

DQ4

DQ5

DQ6

SS

V

DQ3

DQ4

DQ5

DQ6

395 ILL F02b.3

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512

A11

A9

A8
A13
A14
A17

WE#

V

DD

A18
A16
A15
A12

A7

A6

A5

A4

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

A11

A13
A14

A17
WE#
V

DD

NC
A16
A15
A12

A9
A8

A7
A6
A5
A4

A11

A13
A14

WE#
V

A16
A15
A12

NC

DD
NC

A11
A9
A8

A7
A6
A5
A4

A13

A14

WE#
V

A15

A12

A9
A8

NC

DD
NC

NC

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Standard Pinout

T op Vie w

Die Up

395 ILL F01.0

OE#

32

A10

31

CE#

30

DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

V

24

DQ2

23

DQ1

22

DQ0

21

A0

20

A1

19

A2

18

A3

17

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

FIGURE 3: P

TOP VIEW (balls facing down)

SST39LF/VF010

6

A14

5
4
3
2

WE#

NC

1

A9

A7
A3

A13

A8
NC
NC
NC

A4

A15
A11

NC
NC

A6
A2

A16
A12

NC
NC

A5
A1

NC

NC
DQ5
DQ2
DQ0

A0

NC

A10

NC

DQ3

NC

CE#

NC
DQ6
V

DD

V

DD

NC
OE#

V

SS

DQ7
DQ4

NC
DQ1
V

SS

A B C D E F G H

IN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM) FOR 1 MBIT

395 ILL F01a.0.eps

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address
A

MS

Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will s ele ct the

0

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

sector. During Block-Erase A

MS-A16

Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040

Ground

= A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

Data Sheet

address lines will select the block.

2.7-3.6V for SST39VF512/010/020/040

T2.1 395

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V
Program V
Erase V

Standby V

IL
IL
IL

IH

Write Inhibit X V

XXV
Product Identification
Software Mode V

1. X can be VIL or VIH, but no other value.

IL

V

IL

V

IH

V

IH

V
V
V

D

IH

IL
IL

D
X

OUT
IN

1

A

IN

A

IN

Sector address,
XXH for Chip-Erase

XXHigh Z X

IL

V

IL

XHigh Z/ D

High Z/ D

IH

V

IH

OUT
OUT

X
X

See Table 4

T3.4 395

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

6

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command
Sequence

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry
Software ID Exit
Software ID Exit

1. Address format A14-A0 (Hex),

2. BA = Program Byte address
for Sector-Erase; uses AMS-A12 address lines

3. SA

X

= Most significant address

A

MS

= A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

A

MS

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

6. Both Software ID Exit operations are equivalent

4,5
6
6

Address A
Addresses A
Addresses A
Addresses A

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2

Data

3

X

5555H AAH 2AAAH 55H 5555H 90H

XXH F0H

5555H AAH 2AAAH 55H 5555H F0H

can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512.

15

can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF010.

15-A16

can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF020.

15-A17

can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF040.

15-A18

SST39LF/VF512 Device ID = D4H, is read with A
SST39LF/VF010 Device ID = D5H, is read with A
SST39LF/VF020 Device ID = D6H, is read with A
SST39LF/VF040 Device ID = D7H, is read with A

0
0
0
0

= 1
= 1
= 1
= 1

30H

T4.2 395

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

+ 0.5V

DD

+ 1.0V

DD

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39L F512/010 /020/040

Range Ambient Temp V

Commercial 0°C to +70°C 3.0-3.6V

OPERATING RANGE FOR SST39V F51 2/010/020 /040

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

AC CONDITIONS OF TEST

DD

DD

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load

C

= 30 pF for SST39LF512/010/020/040

L

= 100 pF for SST39VF512/010/020/040

C

L

See Figures 13 and 14

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

TABLE 5: DC OPERATING CHARACTERISTICS

VDD = 3.0-3.6V FOR SST39L F512/010/020/0 40 AND 2.7- 3.6V FOR SST39VF512/010/0 20/040

Symbol Parameter

I

DD

I

SB

I

LI

I

LO

V

IL

V

IH

V

IHC

V

OL

V

OH

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

Read 20 mA CE#=OE#=V
Write 20 mA CE#=WE#=V
Standby VDD Current 15 µA CE#=V
Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
Output Leakage Current 10 µA V
Input Low Voltage 0.8 V VDD=VDD Min
Input High Voltage 0.7V
Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
Output Hi gh Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

DD

Limits

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

VVDD=VDD Max

, WE#=VIH, all I/Os open

IL

, OE#=V

IL

IH

Data Sheet

T5.2 395

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T
T

1

PU-READ
PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs
Power-up to Program/Erase Operation 100 µs

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117
Data Retention 100 Years JEDEC Standard A103
Latch Up 100 + I

DD

mA JEDEC Standard 78

T6.1 395

T7.0 395

T8.2 395

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

8

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS

VDD = 3.0-3.6V FOR SST39L F512/010/020/0 40 AND 2.7- 3.6V FOR SST39VF512/010/0 20/040

SST39LF512-45
SST39LF010-45
SST39LF020-45
SST39LF040-45

SST39LF020-55
SST39LF040-55

Symbol Parameter

T
T
T
T
T
T
T
T
T

RC

CE
AA
OE

CLZ
OLZ

CHZ
OHZ
OH

Read Cycle Time 45 55 70 90 ns
Chip Enable Access Time 45 55 70 90 ns
Address Access Time 45 55 70 90 ns
Output Enable Access Time 30 30 35 45 ns

1

CE# Low to Active Output 0 0 0 0 ns

1

OE# Low to Active Output 0 0 0 0 ns

1

CE# High to High-Z Output 15 15 25 30 ns

1

OE# High to High-Z Output 15 15 25 30 ns

1

Output Hold from Address Change

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

0000ns

SST39VF512-70
SST39VF010-70
SST39VF020-70
SST39VF040-70

SST39VF512-90
SST39VF010-90
SST39VF020-90
SST39VF040-90

UnitsMin Max Min Max Min Max Min Max

T9.2 395

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Byte-Program Time 20 µs
Address Setup Time 0 ns
Address Hold Time 30 ns
WE# and CE# Setup Time 0 ns
WE# and CE# Hold Time 0 ns
OE# High Setup Time 0 ns
OE# High Hold Time 10 ns
CE# Pulse Width 40 ns
WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns
Data Setup Time 40 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns
Sector-Erase 25 ms
Chip-Erase 100 ms

T10.1 395

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

9

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

ADDRESS A

MS-0

CE#

OE#

WE#

DQ

7-0

Note: AMS = Most significant address

IH

HIGH-Z

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010,

A17 for SST39LF/VF020 and A18 for SST39LF/VF040

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

T

OH

DAT A V ALIDDAT A V ALID

CHZ

HIGH-Z

395 ILL F03.0

ADDRESS A

MS-0

WE#

T

AS

OE#

CE#

DQ

7-0

Note: AMS = Most significant address

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010,

5555 2AAA 5555 ADDR

T

AH

T

WP

T

T

WPH

T

CH

T

CS

AA 55 A0 DATA

SW0 SW1 SW2

A17 for SST39LF/VF020 and A18 for SST39LF/VF040

DS

BYTE

(ADDR/DATA)

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

395 ILL F04.0

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

10

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

T

AS

5555 2AAA 5555 ADDR

T

AH

T

CP

T

T

CPH

T

CH

T

CS

AA 55 A0 DATA

DS

T

DH

T

BP

SW0 SW1 SW2

Note: AMS = Most significant address

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010,

A17 for SST39LF/VF020 and A18 for SST39LF/VF040

BYTE

(ADDR/DATA)

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

T

OEH

T

CE

T

OE

395 ILL F05.0

T

OES

DQ

7

Note: AMS = Most significant address

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010,

DD# D# D

395 ILL F06.0

A17 for SST39LF/VF020 and A18 for SST39LF/VF040

FIGURE 7: DATA# POLLING TIMING DIAGRAM

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

11

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

ADDRESS A

MS-0

CE#

OEH

OE#

WE#

DQ

6

Note: AMS = Most significant address

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010,

A17 for SST39LF/VF020 and A18 for SST39LF/VF040

FIGURE 8: TO GGL E BIT TIMING DIAGRAM

T

CE

T

T

OET

TWO READ CYCLES

WITH SAME OUTPUTS

OES

395 ILL F07.0

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESS A

MS-0

DQ

CE#

OE#

WE#

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)
SAX = Sector Address

AMS = Most significant address
AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

T

SE

SA

X

55 3055AA 80 AA

334 ILL F08.0

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

12

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

SIX-BYTE CODE FOR CHIP-ERASE

T

SCE

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)
AMS = Most significant address

AMS =A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

5555

55 1055AA 80 AA

334 ILL F17.0

Three-byte sequence for

Software ID Entry

ADDRESS A

DQ

14-0

CE#

OE#

WE#

7-0

5555 2AAA 5555 0000 0001

T

WP

T

WPH

55AA 90

SW0 SW1 SW2

Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

BF

Device ID

395 ILL F09.2

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

13

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

Data Sheet

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

5555 2AAA 5555

AA 55 F0

T

WP

T

WHP

SW0 SW1 SW2

FIGURE 12: SOFTWARE ID EXIT AND RESET

T

IDA

395 ILL F10.0

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

V

IHT

V

ILT

AC test inputs are driven at V
for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

395 ILL F12.1

(0.1 VDD) for a logic “0”. Measurement reference points

IL T

Note: V

- V

- V

- V

- V

INPUT

OUTPUT

INPUT

INPUT

Test

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

395 ILL F11.1

FIGURE 14: A TEST LOAD EXAMPLE

C

L

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

15

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Start

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

FIGURE 15: BYTE-PROGRAM ALGORITHM

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

395 ILL F13.1

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

16

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Internal Timer

Byte-Program/

Erase

Initiated

Wait TBP,

T

SCE, or TSE

Program/Erase

Completed

No

Toggle Bit

Byte-Program/

Erase

Initiated

Read byte

Read same

byte

Does DQ

6

match?

Yes

No

Data# Polling

Byte-Program/

Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Yes

Program/Erase

Completed

Program/Erase

Completed

395 ILL F14.0

FIGURE 16: WAIT OPTIONS

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

17

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Software ID Entry

Command Sequence

Load data: AAH
Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait T

IDA

Read Software ID

Software ID Exit &

Reset Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Load data: F0H

Address: XXH

Wait T

IDA

Return to normal

operation

395 ILL F15.2

FIGURE 17: SOFTWARE ID COMMAND FLOWCHARTS

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

18

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Chip-Erase

Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Wait T

SCE

Chip erased

to FFH

FIGURE 18: ERASE COMMAND SEQUENCE

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

19

Load data: 30H

Address: SA

Wait T

X

SE

Sector erased

to FFH

395 ILL F16.1

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

Data Sheet

SST39x

Fxxx -XX -XX -XX

Package Modifi e r

H = 32 leads
K = 48 balls
Numeric = Die modifier

Package Type

N = PLCC
W = TSOP (die up) (8mm x 14mm)
B3 = TFBGA (6mm x 8mm)

Temperature Range

C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns

Device Density

512 = 512 Kilobit
010 = 1 Megabit
020 = 2 Megabit
040 = 4 Megabit

Voltage

L = 3.0-3.6V
V = 2.7-3.6V

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

20

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Valid combinations for SST39LF512

SST39LF512-45-4C-NH SST39LF512-45-4C-WH

Valid combinations for SST39VF512

SST39VF512-70-4C-NH SST39VF512-70-4C-WH
SST39VF512-90-4C-NH SST39VF512-90-4C-WH

SST39VF512-90-4C-U4
SST39VF512-70-4I-NH SST39VF512-70-4I-WH
SST39VF512-90-4I-NH SST39VF512-90-4I-WH

Valid combinations for SST39LF010

SST39LF010-45-4C-NH SST39LF010-45-4C-WH SST39LF010-45-4C-B3K

Valid combinations for SST39VF010

SST39VF010-70-4C-NH SST39VF010-70-4C-WH SST39VF010-70-4C-B3K
SST39VF010-90-4C-NH SST39VF010-90-4C-WH SST39VF010-90-4C-B3K

SST39VF010-90-4C-U4
SST39VF010-70-4I-NH SST39VF010-70-4I-WH SST39VF010-70-4I-B3K
SST39VF010-90-4I-NH SST39VF010-90-4I-WH SST39VF010-90-4I-B3K

Valid combinations for SST39LF020

SST39LF020-45-4C-NH SST39LF020-45-4C-WH
SST39LF020-55-4C-NH SST39LF020-55-4C-WH

Valid combinations for SST39VF020

SST39VF020-70-4C-NH SST39VF020-70-4C-WH
SST39VF020-90-4C-NH SST39VF020-90-4C-WH

SST39VF020-90-4C-U4
SST39VF020-70-4I-NH SST39VF020-70-4I-WH
SST39VF020-90-4I-NH SST39VF020-90-4I-WH

Valid combinations for SST39LF040

SST39LF040-45-4C-NH SST39LF040-45-4C-WH
SST39LF040-55-4C-NH SST39LF040-55-4C-WH

Valid combinations for SST39VF040

SST39VF040-70-4C-NH SST39VF040-70-4C-WH
SST39VF040-90-4C-NH SST39VF040-90-4C-WH

SST39VF040-90-4C-U1
SST39VF040-70-4I-NH SST39VF040-70-4I-WH
SST39VF040-90-4I-NH SST39VF040-90-4I-WH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

21

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTT OM VIEW

.485
.495

Optional

Pin #1 Identifier

.042
.048

.447
.453

1232

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

.106
.112

.020 R.
MAX.

.023
.029

x 30˚

.030
.040

R.

.042
.048

.547

.585

.553

.595

.050
BSC.

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.026
.032

.050
BSC.

32-LEAD PLASTI C LEA D CHIP CARRIER (PLCC)

ACKAGE CODE: NH

SST P

Pin # 1 Identifier

.125
.140

.075
.095

.013
.021

.400
BSC

.015 Min.

8.10

7.90

.490
.530

1.05

0.95

.50

BSC

.270
.170

.026
.032

32.PLCC.NH-ILL.2

12.50

12.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

32-

LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

14.20

13.80

32.TSOP-WH-ILL.4

0.15

0.05

SST PACKAGE CODE: WH

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

22

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

BOTTOM VIEW

8.00 ± 0.20

TOP VIEW

5.60

0.80

6
5
4
3
2
1

A1 CORNER

A B C D E F G H

SIDE VIEW

SEATING PLANE

6.00 ± 0.20

1.10 ± 0.10

0.15

0.35 ± 0.05

4.00

0.80
H G F E D C B A

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K

6
5
4
3
2
1

0.45 ± 0.05
(48X)

A1 CORNER

48ba-TFBGA-B3K-6x8-450mic-ILL.0

1mm

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

23

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone [phone] • Fax [phone]

www.SuperFlash.com or www.ssti.com

©2001 Silicon Storage Technology, Inc. S71150-03-000 6/01 395

24