Datasheet SST39SF512-90-4I-WH, SST39SF512-90-4I-UH, SST39SF512-90-4I-PH, SST39SF512-90-4I-NH, SST39SF512-90-4C-WH Datasheet (Silicon Storage Technology)

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

SST39SF512 / SST39SF010

FEATURES:

• Organized as 64K x8 / 128K x8

• Single 5.0V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low P ower Consumption:

– Ac ti ve Current: 20 mA (typical) – Standby Current: 10 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 70 ns – 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 7 ms (typical) – Chip-Erase Time: 15 ms (typical) – Byte-Program Time: 20 µs (typical) – Chip Rewrite Time:

2 seconds (typical) for SST39SF512 3 seconds (typical) for SST39SF010

• Automatic Write Timing

– Internal V

PP

Generation

• End-of-Write Detection

– Toggle Bit – Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF512/010 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high perfor- mance CMOS SuperFl ash technology. The split-gate cell design and thi ck oxide tunneling injector a ttain better reliability and manufacturability compared with alternate approaches. The SST39SF512/010 devices write (Program or Erase) with a 5.0V-only power supply. The SST39SF512/010 device conforms to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39SF512/010 devices provide a maximum Byte-Program time of 30 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. T o protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater th an 10 0 years .

The SST39SF51 2/010 devices are suited for applica tions that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption . They inherently use less energy during erase and program than alternative flash technologies. Th e total energy consumed is a

function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is l ess than altern ative flash technologies. These devices also im prove flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash te ch no logy pr ovid es fi xed Erase an d P r ogram times, independent o f the num be r of Erase/ Pro gram cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times inc rease with accumul ated Erase/P rogram cycles .

To meet high density, surface mount requirements, the SST39SF512/010 are offered in 32-pin PLCC packages, 32-pin TSOP, and a 600 mil, 32-pin PDIP is also av ailable. See Figures 1, 2, and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands ar e written to the device using standard mi croprocessor write sequen ces. A command is written by asse r ting WE# low whil e keeping CE#

SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories

2

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. T he data bus is latche d on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST3 9SF512/0 10 is contr olled by CE# and OE#, both have to be low for the syste m to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is desele cted and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for fur ther details (Figure 4).

Byte-Program Operation

The SST39SF512/010 are programmed on a byte-by-byte basis. The Program ope ration c on si sts of thr e e s te ps. Th e first step i s t he th ree- b yte -loa d se quen ce for Soft w are D ata Protection. The second step is to load byte ad dress and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of ei ther CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operatio n which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 30 µs. Se e Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowchar ts. During the Program ope ration, the only valid reads are Dat a# Polling and Toggle Bit. During the inte rnal Program operat ion, the host is fre e to perform additional tasks. Any commands written during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device o n a sector-by-sector basis. The sector architecture is based on unifor m sector size of 4 KByte. The S ectorErase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase com mand (30 H) and sec tor addre ss (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising ed ge of the six th WE# pulse. Th e internal Era se operation begin s after t he sixth W E# puls e. The end of Erase can be deter mined using either Data # Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the SectorErase operation will be ignored.

Chip-Erase Operation

The SST39SF512/010 provide Chip-Erase operation, which allows the user to erase the en tire memor y array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The Erase operation begins wi th the ri s ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the Chip-Erase operation will be ignored.

Write Operation Status Detection

The SST39SF512/010 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the syste m Write cycle time. The software detection includes two status bits: Data# Polling (DQ

7

) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the r ising edge of WE#, which initiates the program or erase cycle.

The actual comple tion of the nonvolatile wr ite is as ynchr onous with the system ; therefore, either a Data# Polling or Tog gle Bit read may be simultaneous with th e completio n of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ

7

or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If bo th reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39S F512/010 are in the inter nal Program operation, any attemp t to read DQ

7

will produce the complement of the true da ta. Once the Program operation is completed, D Q

7

will produce true data. The device is then ready for the next operation. Dur ing inter nal Erase ope ration, any attempt to read DQ

7

will produce a ‘0’. Once the

internal Erase operation is compl eted, DQ

7

will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program Operation. For sector or Chip-Erase, the Data# Polling is valid after the r ising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

3

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ

6

will produce alter nating 0s and 1s, i.e., toggling be tween 0 and 1. T he Toggle Bit will begin with “1”. When the internal Program or Erase opera- tion is complete d, the to ggl in g will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39SF512/010 provide both hardware and software features to protect nonvolatile data from inadverten t writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of l ess th an 5 ns will not init iate a Writ e cycle .

V

DD

Power Up/Down Detection: The write operation is

inhibited when V

DD

is less than 2.5V.

Write Inhibit Mode:

Forcing OE# low, CE# high, or WE# high will inhibit the W r it e operation. This prevents inadvertent writes during p owe r-up o r pow er- down.

Software Data Protection (SDP)

The SST39SF512 /01 0 p rovi de th e J EDEC approved Software Data Protection s che me for all da ta altera tion operations, i.e., Program and Erase. Any Program operation requires the inclusio n of a series of three byte sequenc e. The three byte-load seq uence is used to initi ate the Program operation, providing optimal protection from inadvertent write operations, e.g., d uring the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF512 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T

RC

.

Product Identification

The product identification mode identifies the device as the SST39SF512 and SST39SF010 and manufacturer as SST. This mode may be accessed by software operations. Users may use the software product identification operation to identify the par t (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 f or software operation, Figure 11 for the software ID entr y and read timing diagram and Figure 17 for the ID entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software Product Identifica tion mode must be exited. Exi t is acco mplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the s oftware reset command is ignored during an internal Program or Erase operation. See T ab le 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart.

TABLE 1: P

RODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH Device ID SST39LF/VF512 0001H B4H SST39LF/VF010 0001H B5H

T1.1 394

4

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

Y-Decoder

I/O Buffers and Data Latches

394 ILL B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ

0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

SST39SF512SST39SF010

SST39SF512 SST39SF010

SST39SF512SST39SF010

SST39SF512 SST39SF010

5 6 7 8 9 10 11 12 13

29 28 27 26 25 24 23 22 21

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A14 A13 A8 A9 A11 OE# A10 CE# DQ7

4 3 2 1 32 31 30

A12

A15NCNC

VDDWE#

NC

A12

A15

A16NCVDDWE#

NC

32-pin PLCC

T op Vie w

394 ILL F02b.4

14 15 16 17 18 19 20

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

5

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

FIGURE 3: P

IN ASSIGNMENTS FOR 32-PIN PDIP

A11

A9

A8 A13 A14

NC WE# V

DD

NC

A15 A12

A7 A6 A5 A4

A11

A9

A8 A13 A14

NC WE# V

DD

NC

A16 A15 A12

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

394 ILL F01.2

Standard Pinout

T op Vie w

Die Up

SST39SF512SST39SF010

SST39SF512 SST39SF010

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-pin PDIP

T op Vie w

394 ILL F02a.3

NC

NC A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

SST39SF512SST39SF010 SST39SF512 SST39SF010

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

V

DD

WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

V

DD

WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

6

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A

MS

1

-A

0

Address Inputs To provide memory addresses.

During Sector-Erase A

MS-A12

address lines will select the sector.

DQ

7

-DQ

0

Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V

DD

Power Supply To provide 5.0V supply (±10%)

V

SS

Ground

NC No Connection Unconnected pins.

T2.3 394

1. AMS = Most significant address A

MS

= A15 for SST39SF512 and A16 for SST39SF010

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

IL

V

IL

VIHD

OUT

A

IN

Program V

IL

V

IH

VILD

IN

A

IN

Erase V

IL

V

IH

VILX

1

1. X can be VIL or VIH, but no other value.

Sector address, XXH for Chip-Erase

Standby V

IH

X X High Z X

Write Inhibit X V

IL

X High Z/ D

OUT

X

XXV

IH

High Z/ D

OUT

X Product Identification Software Mode V

IL

V

IL

V

IH

See Table 4

T3.4 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

7

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA

2

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

X

3

30H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry

4,5

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit

6

XXH F0H

Software ID Exit

6

5555H AAH 2AAAH 55H 5555H F0H

T4.3 394

1. Address format A14-A0 (Hex), Addres s A15 can be VIL or VIH, but no other value, for the Command sequence for SST39SF512. Addresses A

15

- A16 can be VIL or VIH, but no other value, for the Command sequence for

SST39SF010.

2. BA = Program Byte address

3. SA

X

for Sector-Erase; uses AMS-A12 address lines

A

MS

= Most significant address

A

MS

= A15 for SST39SF512 and A16 for SST39SF010

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

MS-A1

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

SST39LF/VF512 Device ID = B4H, is read with A

0

= 1

SST39LF/VF010 Device ID = B5H, is read with A

0

= 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

DD

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

DD

+ 1.0V

Voltage on A

9

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circ uit Curr ent

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp V

DD

Commercial 0°C to +70°C5.0V±10% Industrial -40°C to +85°C5.0V±10%

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

L

= 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

L

= 100 pF for 90 ns

See Figures 13 and 14

8

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10%

Symbol Parameter

Limits

Test ConditionsMin Max Units

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

V

DD=VDD

Max

Read 30 mA CE#=OE#=V

IL

, WE#=VIH, all I/Os open

Write 50 mA CE#=WE#=V

IL

, OE#=V

IH

I

SB1

Standby VDD Current (TTL input)

3µACE#=VIH, VDD=VDD Max

I

SB2

Standby VDD Current (CMOS input)

50 µA CE#=V

DD

-0.3V, VDD=VDD Max

I

LI

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

I

LO

Output Leakage Current 10 µA V

OUT

=GND to VDD, VDD=VDD Max

V

IL

Input Low Voltage 0.8 V VDD=VDD Min

V

IH

Input High Voltage 2.0 V VDD=VDD Max

V

OL

Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

V

OH

Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

V

H

Supervoltage for A9 pin 11.4 12.6 V CE#=OE#=VIL, WE#=V

IH

I

H

Supervoltage Current for A9 pin 200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T5.3 394

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

T

PU-WRITE

1

Power-up to Program/Erase Operation 100 µs

T6.1 394

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

C

I/O

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

I/O

= 0V 12 pF

C

IN

1

Input Capacitance VIN = 0V 6 pF

T7.0 394

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

N

END

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

T

DR

1

Data Retention 100 Years JEDEC Standard A103

I

LTH

1

Latch Up 100 + I

DD

mA JEDEC Standard 78

T8.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

9

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 5.0V±10%

Symbol Parameter

SST39SF512/010-70 SST39SF512/010-90

UnitsMinMaxMinMax

T

RC

Read Cycle Time 70 90 ns

T

CE

Chip Enable Access Time 70 90 ns

T

AA

Address Access Time 70 90 ns

T

OE

Output Enable Access Time 35 45 ns

T

CLZ

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

T

OLZ

1

OE# Low to Active Output 0 0 ns

T

CHZ

1

CE# High to High-Z Output 25 30 ns

T

OHZ

1

OE# High to High-Z Output 25 30 ns

T

OH

1

Output Hold from Address Change 0 0 ns

T9.2 394

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

Byte-Program Time 20 µs

T

AS

Address Setup Time 0 ns

T

AH

Address Hold Time 30 ns

T

CS

WE# and CE# Setup Time 0 ns

T

CH

WE# and CE# Hold Time 0 ns

T

OES

OE# High Setup Time 0 ns

T

OEH

OE# High Hold Time 10 ns

T

CP

CE# Pulse Width 40 ns

T

WP

WE# Pulse Width 40 ns

T

WPH

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

T

CPH

1

CE# Pulse Width High 30 ns

T

DS

Data Setup Time 30 ns

T

DH

1

Data Hold Time 0 ns

T

IDA

1

Software ID Access and Exit Time 150 ns

T

SE

Sector-Erase 10 ms

T

SCE

Chip-Erase 20 ms

T10.0 394

10

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

394 ILL F03.1

ADDRESS A

MS-0

DQ

7-0

WE#

OE#

CE#

T

CE

T

RC

T

AA

T

OE

T

OLZV

IH

HIGH-Z

T

CLZ

T

OH

T

CHZ

HIGH-Z

DATA V ALIDDATA V ALID

T

OHZ

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F04.1

ADDRESS A

MS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ

7-0

T

DH

T

WPH

T

DS

T

WP

T

AH

T

AS

T

CH

T

CS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

T

BP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

11

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING TIMING DIAGRAM

394 ILL F05.1

ADDRESS A

MS-0

DQ

7-0

T

DH

T

CPH

T

DS

T

CP

T

AH

T

AS

T

CH

T

CS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

T

BP

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F06.1

ADDRESS A

MS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ

7

DD# D# D

WE#

OE#

CE#

T

OEH

T

OE

T

CE

T

OES

12

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

394 ILL F07.1

ADDRESS A

MS-0

DQ

6

WE#

OE#

CE#

T

OET

OEH

T

CE

T

OES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggle bit output is always high first.

AMS = Most significant address AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F08.2

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address

AMS = Most significant address AMS = A15 for SST39SF512 and A16 for SST39SF010

ADDRESS A

MS-0

DQ

7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SA

X

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

T

SE

T

WP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

13

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

394 ILL F17.1

ADDRESS A

MS-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address

AMS = Most significant address AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ

7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

T

SCE

T

WP

394 ILL F09.2

ADDRESS A

14-0

T

IDA

DQ

7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte sequence for

Software ID Entry

T

WP

T

WPH

T

AA

BF

Device ID

55AA 90

Device ID = B5H for SST39SF010 and B6H for SST39SF020

14

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 12: SOFTWARE ID EXIT AND RESET

394 ILL F10.0

ADDRESS A

14-0

DQ

7-0

T

IDA

T

WP

T

WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

15

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

394 ILL F11.0

REFERENCE POINTS OUTPUTINPUT

V

HT

V

LT

V

HT

V

LT

V

IHT

V

ILT

AC test inputs are driven at V

IHT

(2.4V) for a logic “1” and V

IL T

(0.4 V) for a logic “0”. Measurement reference points for

inputs and outputs are V

HT

(2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: V

HT

- V

HIGH

Test

V

LT

- V

LOW

Test

V

IHT

- V

INPUT

HIGH Test

V

ILT

- V

INPUT

LOW Test

394 ILL F12.1

TEST LOAD EXAMPLE

TO TESTER

TO DUT

C

L

R

L LOW

RL

HIGH

V

DD

16

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 15: BYTE-PROGRAM ALGORITHM

394 ILL F13.1

Start

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Byte

Address/Byte

Data

Wait for end of Program (TBP'

Data# Polling

bit or Toggle bit

operation)

Program

Completed

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

17

FIGURE 16: WAIT OPTIONS

394 ILL F14.0

Wait TBP,

T

SCE, or TSE

Program/Erase

Initiated

Internal Timer

Toggle Bit

Yes

No

Program/Erase

Completed

Does DQ

6

match?

Read same

byte

Data# Polling

Write

Completed

Write

Completed

Read byte

Is DQ7 =

true data?

Read DQ

7

Byte-Program

Initiated

Byte-Program/

Sector Erase

Initiated

18

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

394 ILL F15.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait T

IDA

Read Software ID

Load data: AAH Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

Wait T

IDA

Wait T

IDA

Return to normal

operation

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

19

FIGURE 18: ERASE COMMAND SEQUENCE

394 ILL F16.1

Load data: AAH Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH Address: 5555H

Wait T

SCE

Chip-Erase

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SA

X

Load data: AAH

Address: 5555H

Wait T

SE

Sector-Erase

to FFH

20

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

SST39SF512 Valid combinations

SST39SF512-70-4C-NH SST39SF512-70-4C-WH SST39SF512-70-4C-PH SST39SF512-90-4C-NH SST39SF512-90-4C-WH SST39SF512-90-4C-PH SST39SF512-90-4C-U3

SST39SF512-70-4I-NH SST39SF512-70-4I-WH SST39SF512-90-4I-NH SST39SF512-90-4I-WH

SST39SF010 Valid combinations

SST39SF010-70-4C-NH SST39SF010-70-4C-WH SST39SF010-70-4C-PH SST39SF010-90-4C-NH SST39SF010-90-4C-WH SST39SF010-90-4C-PH SST39SF010-90-4C-U4

SST39SF010-90-4I-NH SST39SF010-90-4I-WH

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST39SFxxx

-XX -XX -XX

Package Modifie r

H = 32 pins Numeric = Die modifier

Package Type

N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP U = Unencapsulated die

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns 90 = 90 ns

Device Density

512 = 512 Kilobit 010 = 1 Megabit

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010

21

PACKAGING DIAGRAMS

32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST P

ACKAGE CODE: NH

32-

PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

.030 .040

.013 .021

.490 .530

.075 .095

.015 Min.

.125 .140

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.026 .032

.400 BSC

32.PLCC.NH-ILL.2

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050 BSC.

.026 .032

.023 .029

.447 .453

.042 .048

Optional

Pin #1 Identifier

.547 .553

.585 .595

.485 .495

.020 R. MAX.

.106 .112

R.

x 30˚

32.TSOP-WH-ILL.4

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

8.10

7.90

.270 .170

1.05

0.95

.50

BSC

0.15

0.05

12.50

12.30

Pin # 1 Identifier

14.20

13.80

0.70

0.50

22

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST P

ACKAGE CODE: PH

32.pdipPH-ILL.2

Pin #1 Identifier

C

L

32

1

Base Plane

Seating Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.170 .200

7˚

4 PLCS.

.600 BSC

.100 BSC

.120 .150

.016 .022

.045 .065

.070 .080

.015 .050

.065 .075

1.645

1.655

.008 .012

0˚

15˚

.600 .625

.530 .550

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735 -90 36

www.SuperFlash.com or www.ssti.com