Datasheet SST39SF010A, SST39SF020A, SST39SF040 Datasheet (Silicon Storage Technology)

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

FEATURES:

SST39SF010A / SST39SF020A / SST39SF040

SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories

Data Sheet

• Organized as 128K x8 / 256K x8 / 512K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption (typical values at 14 MHz)

– Active Current: 10 mA (typical) – Standby Current: 30 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 45 ns – 70 ns

• Latched Address and Data

PRODUCT DESCRIPTION

• Fast Erase and Byte-Program

– Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time:

2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bit – Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP

The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-lead PLCC and 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2, and 3 for pin assignments.

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram (Figure 4) for further details.

Byte-Program Operation

The SST39SF010A/020A/040 are programmed on a byteby-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the ByteProgram operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H)

is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the SectorErase operation will be ignored.

Chip-Erase Operation

The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored.

Write Operation Status Detection

The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ

) and Toggle Bit (DQ6). The End-of-Write detection

7

mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

or DQ6. In order to prevent spurious

7

2

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Data# Polling (DQ7)

When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ

will produce the

7

complement of the true data. Once the Program operation is completed, DQ though DQ

7

will produce true data. Note that even

7

may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ internal Erase operation is completed, DQ

will produce a ‘0’. Once the

7

will produce a

7

‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ

will produce alternating 0s

6

and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

V

Power Up/Down Detection: The Write operation is

DD

inhibited when V

Write Inhibit Mode: high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

is less than 2.5V.

DD

Forcing OE# low, CE# high, or WE#

Software Data Protection (SDP)

The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST39SF010A/ 020A/040 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T

RC.

Product Identification

The Product Identification mode identifies the device as the SST39SF040, SST39SF010A, or SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH

Device ID

SST39SF010A 0001H B5H

SST39SF020A 0001H B6H

SST39SF040 0001H B7H

RODUCT IDENTIFICATION

Address Data

T1.2 1147

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart.

3

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Memory Address

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

Address Buffers & Latches

CE#

OE#

WE#

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

SST39SF010A

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

SST39SF020ASST39SF040

X-Decoder

Control Logic

A12

A15

A16

A18

VDDWE#

A12

A15

SST39SF020A SST39SF040

SST39SF010A

4 3 2 1 32 31 30

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20

A16NCVDDWE#

A12

A15

A16NCVDDWE#

32-lead PLCC

Top View

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

A17

NC

SST39SF010A

29

28

27

26

25

24

23

22

21

SST39SF020A SST39SF040

A14

A13

A8

A9

A11

OE#

A10

CE#

DQ7

A14

A13

A8

A9

A11

OE#

A10

CE#

DQ7

0

1147 B1.2

A14

A13

A8

A9

A11

OE#

A10

CE#

DQ7

DQ1

SST39SF010A

DQ1

SST39SF020ASST39SF040

DQ1

DQ2

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

DQ6

1147 32-plcc P2.4

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

4

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

DD NC

A9 A8

A7 A6 A5 A4

SST39SF010A

A11

A9

A8 A13 A14

NC WE# V

DD

NC

A16 A15 A12

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Standard Pinout

Top View

Die Up

A11

A13 A14

A17 WE# V

DD

A18

A16

A15

A12

SST39SF020ASST39SF040

A11 A9 A8

A13

A14

A17

WE# V

A16

A15

A12 A7 A6 A5 A4

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

SST39SF010A

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-pin

PDIP

Top View

SST39SF010A

32

V

31

WE#

30

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

DD

1147 32-pdip P3.2

SST39SF040

A18 A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

SST39SF020A

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

SST39SF010A

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

SST39SF040

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

SST39SF020A SST39SF040

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

1147 32-tsop P1.1

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

FIGURE 3: P

IN ASSIGNMENTS FOR 32-PIN PDIP

5

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

A

-A

MS

DQ

-DQ

7

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address A

MS

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

Program V

Erase V

Standby V

Write Inhibit X V

Product Identification

Software Mode V

1. X can be VIL or VIH, but no other value.

Address Inputs To provide memory addresses.

0

During Sector-Erase A

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

address lines will select the sector.

MS-A12

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide 5.0V supply (4.5-5.5V)

Ground

= A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

IL

V

IL

V

IH

V

IH

V

D

IH

IL

D

X

OUT

IN

1

A

IN

A

IN

Sector address, XXH for Chip-Erase

IH

XXV

IL

X X High Z X

IL

V

IL

X High Z/ D

High Z/ D

IH

V

IH

OUT

X

See Table 4

T2.2 1147

T3.3 1147

6

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry

Software ID Exit

1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. A

= Most significant address

MS

= A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

A

MS

2. BA = Program Byte address

3. SA

for Sector-Erase; uses AMS-A12 address lines

X

4. The device does not remain in Software Product ID mode if powered down.

5. With A

6. Both Software ID Exit operations are equivalent

4,5

6

= 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

1

Addr

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2nd Bus

Write Cycle

3rd Bus

Write Cycle

5555H AAH 2AAAH 55H 5555H 90H

XXH F0H

5555H AAH 2AAAH 55H 5555H F0H

SST39SF010A Device ID = B5H, is read with A SST39SF020A Device ID = B6H, is read with A SST39SF040 Device ID = B7H, is read with A

0

= 1

0

= 1

0

= 1

4th Bus

Write Cycle

2

Data

5th Bus

Write Cycle

6th Bus

Write Cycle

3

30H

X

T4.2 1147

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

DD

+0.5V +2.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 45 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

See Figures 13 and 14

= 100 pF for 70 ns

L

7

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V

Limits

Symbol Parameter

I

DD

I

SB1

I

SB2

I

LI

I

LO

V

IL

V

IH

V

IHC

V

OL

V

OH

1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C

2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

Power Supply Current Address input=V

2

Read

Program and Erase 35 mA CE#=WE#=V

Standby VDD Current (TTL input)

Standby VDD Current (CMOS input)

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

Output Leakage Current 10 µA V

Input Low Voltage 0.8 V VDD=VDD Min

Input High Voltage 2.0 V VDD=VDD Max

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

(room temperature), and V

= 5V for SF devices. Not 100% tested.

DD

1

Test ConditionsMin Max Units

VDD=VDD Max

25 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

3mACE#=V

100 µA CE#=V

, VDD=VDD Max

IH

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

OUT

ILT/VIHT

, OE#=V

IL

, at f=1/TRC Min

IH

T5.10 1147

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

1

PU-READ

PU-WRITE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

1

Power-up to Program/Erase Operation 100 µs

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1,2

N

END

1

T

DR

1

I

LT H

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. N

END

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

DD

mA JEDEC Standard 78

T6.1 1147

T7.0 1147

T8.2 1147

8

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V

SST39SF010A/020A/040-45 SST39SF010A/020A/040-70

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

T

CLZ

T

OLZ

T

CHZ

T

OHZ

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 45 70 ns

Chip Enable Access Time 45 70 ns

Address Access Time 45 70 ns

Output Enable Access Time 25 35 ns

1

CE# Low to Active Output 0 0 ns

1

OE# Low to Active Output 0 0 ns

1

CE# High to High-Z Output 15 25 ns

1

OE# High to High-Z Output 15 25 ns

1

Output Hold from Address Change 0 0 ns

Data Sheet

UnitsMin Max Min Max

T9.4 1147

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

T

CPH

T

DS

T

DH

T

IDA

T

SE

T

SCE

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Byte-Program Time 20 µs

Address Setup Time 0 ns

Address Hold Time 30 ns

WE# and CE# Setup Time 0 ns

WE# and CE# Hold Time 0 ns

OE# High Setup Time 0 ns

OE# High Hold Time 10 ns

CE# Pulse Width 40 ns

WE# Pulse Width 40 ns

1

WE# Pulse Width High 30 ns

1

CE# Pulse Width High 30 ns

Data Setup Time 40 ns

1

Data Hold Time 0 ns

1

Software ID Access and Exit Time 150 ns

Sector-Erase 25 ms

Chip-Erase 100 ms

T10.1 1147

9

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

ADDRESS A

MS-0

OE#

WE#

DQ

CE#

7-0

IH

HIGH-Z

Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

DATA VALIDDATA VALID

CHZ

HIGH-Z

1147 F03.1

ADDRESS A

MS-0

WE#

DQ

OE#

CE#

7-0

T

AS

Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

5555 2AAA 5555 ADDR

T

AH

T

WP

T

WPH

T

CH

T

CS

AA 55 A0 DATA

SW0 SW1 SW2

DS

BYTE

(ADDR/DATA)

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

1147 F04.1

10

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

T

AS

5555 2AAA 5555 ADDR

T

AH

T

CP

T

CPH

T

CH

T

CS

AA 55 A0 DATA

DS

INTERNAL PROGRAM OPERATION STARTS

T

BP

T

DH

Data Sheet

SW0 SW1 SW2

Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

BYTE

(ADDR/DATA)

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

CE#

OE#

WE#

T

OEH

T

CE

T

OE

1147 F05.1

T

OES

DQ

7

Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

DD# D# D

1147 F06.1

FIGURE 7: DATA# POLLING TIMING DIAGRAM

11

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

ADDRESS A

MS-0

CE#

OEH

OE#

WE#

DQ

6

Note: Toggle bit output is always high first. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

Note

T

CE

T

OET

TWO READ CYCLES

WITH SAME OUTPUTS

1147 F07.1

OES

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESS A

MS-0

5555 2AAA 2AAA5555 5555

CE#

OE#

T

WP

WE#

DQ

7-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address

AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

T

SE

SA

X

55 3055AA 80 AA

1147 F08.1

12

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

SIX-BYTE CODE FOR CHIP-ERASE

T

Data Sheet

SCE

ADDRESS A

MS-0

WE#

DQ

CE#

OE#

7-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address

AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

5555

55 1055AA 80 AA

1147 F17.1

Three-byte Sequence for

Software ID Entry

ADDRESS A

DQ

14-0

CE#

OE#

WE#

7-0

5555 2AAA 5555 0000 0001

T

WP

T

WPH

55AA 90

SW0

Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040

SW1 SW2

FIGURE 11: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

BF

Device ID

1147 F09.2

13

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A

DQ

14-0

7-0

CE#

OE#

WE#

5555 2AAA 5555

AA 55 F0

T

WP

T

WHP

SW0 SW1 SW2

FIGURE 12: SOFTWARE ID EXIT AND RESET

T

IDA

1147 F10.0

14

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

V

IHT

Data Sheet

V

ILT

AC test inputs are driven at V and outputs are V

(1.5V) and VOT (1.5V). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

V

IT

(3.0V) for a logic “1” and V

IHT

REFERENCE POINTS OUTPUTINPUT

ILT

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

V

OT

1147 F11.1

(0V) for a logic “0”. Measurement reference points for inputs

Note: V

V V V

V

RL

IT

OT

IHT

ILT

DD

- V

HIGH

INPUT

OUTPUT

INPUT

Te s t

HIGH Test

LOW Test

FIGURE 14: A TEST LOAD EXAMPLE

C

L

R

L LOW

1147 F12.0

15

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

FIGURE 15: BYTE-PROGRAM ALGORITHM

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1147 F13.1

16

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Internal Timer

Byte

Program/Erase

Initiated

Wait TBP,

T

SCE, or TSE

Program/Erase

Completed

Program/Erase

No

Toggle Bit

Byte

Initiated

Read byte

Read same

byte

Does DQ

6

match?

Ye s

No

Program/Erase

Data# Polling

Byte

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Ye s

Completed

FIGURE 16: WAIT OPTIONS

Program/Erase

Completed

1147 F14.0

17

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Software Product ID Entry

Command Sequence

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait T

IDA

Read Software ID

Software Product ID Exit &

Reset Command Sequence

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Load data: F0H

Address: XXH

Wait T

IDA

Return to normal

operation

1147 F15.1

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

18

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Chip-Erase

Command Sequence

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: AAH Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Wait T

SCE

Chip erased

to FFH

Load data: 30H

Address: SA

Wait T

X

SE

Sector erased

to FFH

1147 F16.1

FIGURE 18: ERASE COMMAND SEQUENCE

19

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

PRODUCT ORDERING INFORMATION

SST 39 SF 010A - 45 - 4C - NH E

XX

XXXXXX -XXX -XX- XXX X

Environmental Attribute

E = non-Pb

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns 70 = 70 ns

Version

A = Special Feature Version

Device Density

040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit

Volt ag e

S = 4.5-5.5V

Product Series

39 = Multi-Purpose Flash

20

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Valid combinations for SST39SF010A

SST39SF010A-45-4C-NH SST39SF010A-45-4C-WH

SST39SF010A-45-4C-NHE SST39SF010A-45-4C-WHE

SST39SF010A-70-4C-NH SST39SF010A-70-4C-WH SST39SF010A-70-4C-PH

SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-70-4C-PHE

SST39SF010A-45-4I-NH SST39SF010A-45-4I-WH

SST39SF010A-45-4I-NHE SST39SF010A-45-4I-WHE

SST39SF010A-70-4I-NH SST39SF010A-70-4I-WH

SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE

Valid combinations for SST39SF020A

SST39SF020A-45-4C-NH SST39SF020A-45-4C-WH

SST39SF020A-45-4C-NHE SST39SF020A-45-4C-WHE

SST39SF020A-70-4C-NH SST39SF020A-70-4C-WH SST39SF020A-70-4C-PH

SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-70-4C-PHE

SST39SF020A-45-4I-NH SST39SF020A-45-4I-WH

SST39SF020A-45-4I-NHE SST39SF020A-45-4I-WHE

SST39SF020A-70-4I-NH SST39SF020A-70-4I-WH

SST39SF020A-70-4I-NHE SST39SF020A-70-4I-WHE

Data Sheet

Valid combinations for SST39SF040

SST39SF040-45-4C-NH SST39SF040-45-4C-WH

SST39SF040-45-4C-NHE SST39SF040-45-4C-WHE

SST39SF040-70-4C-NH SST39SF040-70-4C-WH SST39SF040-70-4C-PH

SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-70-4C-PHE

SST39SF040-45-4I-NH SST39SF040-45-4I-WH

SST39SF040-45-4I-NHE SST39SF040-45-4I-WHE

SST39SF040-70-4I-NH SST39SF040-70-4I-WH

SST39SF040-70-4I-NHE SST39SF040-70-4I-WHE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

21

Data Sheet

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTTOM VIEW

.495 .485

Optional

Pin #1

Identifier

.048 .042

.453 .447

1232

.020 R. MAX.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

.112 .106

.029 .023

x 30˚

.040 .030

R.

.042 .048

.553

.595

.547

.585

.050 BSC

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.032 .026

.050 BSC

.140 .125

.021 .013

.095 .075

.400

.530

BSC

.490

.015 Min.

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST P

ACKAGE CODE: NH

.032 .026

32-plcc-NH-3

22

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Pin # 1 Identifier

Data Sheet

1.05

0.95

0.50

BSC

8.10

7.90

12.50

12.30

1.20

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

14.20

13.80

max.

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH

DETAIL

1mm

0.27

0.17

0.15

0.05

0˚- 5˚

0.70

0.50

32-tsop-WH-7

23

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

32

C

L

.080 .070

1

.065 .045

1.655

1.645

.022 .016

.100 BSC

.200 .170

.150 .120

7˚

4 PLCS.

.012 .008

.625 .600

.550 .530

.600 BSC

32-pdip-PH-3

Pin #1 Identifier

.075 .065

Base

Plane

Seating

Plane

.050 .015

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST P

ACKAGE CODE: PH

TABLE 11: R

EVISION HISTORY

Number Description Date

02

03

• 2002 Data Book

• Changes to Table 5 on page 8

May 2002

Mar 2003

– Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters

04

05

– Clarified I

• Document status changed from “Preliminary Specification” to “Data Sheet”

• Changed I

• 2004 Data Book

Write to be Program and Erase

DD

Program and Erase max values from 25 to 35 in Table 5 on page 8

DD

Oct 2003

Nov 2003

• Added non-Pb MPNs and removed footnote (See page 21)

06

• Corrected Revision History for Version 04: I

max value was incorrectly stated as 30 mA instead of 35 mA

DD

Aug 2004

0˚

15˚

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

24

Datasheet SST39SF010A, SST39SF020A, SST39SF040 Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual